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add verbose output option to configure port disable timing writer

This commit is contained in:
tangxifan 2020-05-17 19:36:57 -06:00
parent 6177921d4c
commit 8915d10d27
4 changed files with 22 additions and 12 deletions
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4
openfpga/src/base/openfpga_sdc.cpp
View File

@ -149,6 +149,7 @@ int write_sdc_disable_timing_configure_ports(const OpenfpgaContext& openfpga_ctx
/* Get command options */
CommandOptionId opt_output_dir = cmd.option("file");
CommandOptionId opt_flatten_names = cmd.option("flatten_names");
CommandOptionId opt_verbose = cmd.option("verbose");
std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
@ -158,7 +159,8 @@ int write_sdc_disable_timing_configure_ports(const OpenfpgaContext& openfpga_ctx
cmd_context.option_enable(cmd, opt_flatten_names),
openfpga_ctx.mux_lib(),
openfpga_ctx.arch().circuit_lib,
openfpga_ctx.module_graph())) {
openfpga_ctx.module_graph(),
cmd_context.option_enable(cmd, opt_verbose))) {
return CMD_EXEC_FATAL_ERROR;
}

3
openfpga/src/base/openfpga_sdc_command.cpp
View File

@ -138,6 +138,9 @@ ShellCommandId add_openfpga_write_sdc_disable_timing_configure_ports_command(ope
/* Add an option '--flatten_name' */
shell_cmd.add_option("flatten_names", false, "Use flatten names (no wildcards) in SDC files");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose outputs");
/* Add command 'write_configuration_chain_sdc' to the Shell */
ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files to disable timing for configure ports across FPGA fabric");
shell.set_command_class(shell_cmd_id, cmd_class_id);

24
openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
View File

@ -183,7 +183,8 @@ int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
const bool& flatten_names,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager) {
const ModuleManager& module_manager,
const bool& verbose) {
/* Create the directory */
create_directory(find_path_dir_name(sdc_fname));
@ -205,41 +206,44 @@ int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
VTR_ASSERT(true == module_manager.valid_module_id(top_module));
/* Disable timing for the configure ports of all the Look-Up Tables */
VTR_LOG("Write disable timing for Look-Up Tables...");
VTR_LOGV(verbose, "Write disable timing for Look-Up Tables...");
if (CMD_EXEC_FATAL_ERROR == print_sdc_disable_lut_configure_ports(fp,
flatten_names,
circuit_lib,
module_manager,
top_module)) {
VTR_LOG("Fatal errors occurred\n");
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Fatal errors occurred\n");
return CMD_EXEC_FATAL_ERROR;
}
VTR_LOG("Done\n");
VTR_LOGV(verbose, "Done\n");
/* Disable timing for the configure ports of all the routing multiplexer */
VTR_LOG("Write disable timing for routing multiplexers...");
VTR_LOGV(verbose, "Write disable timing for routing multiplexers...");
if (CMD_EXEC_FATAL_ERROR == print_sdc_disable_routing_multiplexer_configure_ports(fp,
flatten_names,
mux_lib,
circuit_lib,
module_manager,
top_module)) {
VTR_LOG("Fatal errors occurred\n");
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Fatal errors occurred\n");
return CMD_EXEC_FATAL_ERROR;
}
VTR_LOG("Done\n");
VTR_LOGV(verbose, "Done\n");
/* Disable timing for the other programmable circuit models */
VTR_LOG("Write disable timing for other programmable modules...");
VTR_LOGV(verbose, "Write disable timing for other programmable modules...");
if (CMD_EXEC_FATAL_ERROR == print_sdc_disable_non_mux_circuit_configure_ports(fp,
flatten_names,
circuit_lib,
module_manager,
top_module)) {
VTR_LOG("Fatal errors occurred\n");
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Fatal errors occurred\n");
return CMD_EXEC_FATAL_ERROR;
}
VTR_LOG("Done\n");
VTR_LOGV(verbose, "Done\n");
/* Close file handler */
fp.close();

3
openfpga/src/fpga_sdc/configure_port_sdc_writer.h
View File

@ -19,7 +19,8 @@ int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
const bool& flatten_names,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager);
const ModuleManager& module_manager,
const bool& verbose);
} /* end namespace openfpga */