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now use explicit port mapping in the verilog testbenches for reference benchmarks

This commit is contained in:
tangxifan 2020-05-01 21:18:14 -06:00
parent 889bc8dbe8
commit 1e2226e1c3
4 changed files with 30 additions and 3 deletions
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7
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -108,13 +108,17 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
/* Do NOT use explicit port mapping here:
* VPR added a prefix of "out_" to the output ports of input benchmark
*/
std::vector<std::string> prefix_to_remove;
prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX));
print_verilog_testbench_benchmark_instance(fp, reference_verilog_top_name,
std::string(BENCHMARK_INSTANCE_NAME),
std::string(),
std::string(),
prefix_to_remove,
std::string(BENCHMARK_PORT_POSTFIX),
atom_ctx, netlist_annotation,
false);
true);
print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@ -146,6 +150,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
std::string(FPGA_INSTANCE_NAME),
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
std::vector<std::string>(),
std::string(FPGA_PORT_POSTFIX),
atom_ctx, netlist_annotation,
true);

16
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -57,6 +57,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& instance_name,
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::string& output_port_postfix,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
@ -97,8 +98,21 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
} else {
VTR_ASSERT_SAFE(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
fp << "\t\t";
/* Note that VPR added a prefix "out_" or "out:" to the name of output blocks
* We can remove this when specified through input argument
*/
std::string output_block_name = block_name;
for (const std::string& prefix_to_remove : output_port_prefix_to_remove) {
if (!prefix_to_remove.empty()) {
if (0 == output_block_name.find(prefix_to_remove)) {
output_block_name.erase(0, prefix_to_remove.length());
break;
}
}
}
if (true == use_explicit_port_map) {
fp << "." << block_name << module_output_port_postfix << "(";
fp << "." << output_block_name << module_output_port_postfix << "(";
}
fp << block_name << output_port_postfix;
if (true == use_explicit_port_map) {

4
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -20,6 +20,9 @@
/* begin namespace openfpga */
namespace openfpga {
constexpr char* VPR_BENCHMARK_OUT_PORT_PREFIX = "out:";
constexpr char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_";
void print_verilog_testbench_fpga_instance(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
@ -30,6 +33,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& instance_name,
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::string& output_port_postfix,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,

6
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -458,13 +458,17 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
/* Do NOT use explicit port mapping here:
* VPR added a prefix of "out_" to the output ports of input benchmark
*/
std::vector<std::string> prefix_to_remove;
prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX));
print_verilog_testbench_benchmark_instance(fp, reference_verilog_top_name,
std::string(TOP_TESTBENCH_REFERENCE_INSTANCE_NAME),
std::string(),
std::string(),
prefix_to_remove,
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
atom_ctx, netlist_annotation,
false);
true);
print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));