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debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports

This commit is contained in:
tangxifan 2020-02-27 13:24:26 -07:00
parent f558405887
commit 078f72320f
6 changed files with 24 additions and 19 deletions
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4
openfpga/src/base/openfpga_verilog.cpp
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@ -57,7 +57,7 @@ void write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context) {
CommandOptionId opt_output_dir = cmd.option("file");
CommandOptionId opt_reference_benchmark = cmd.option("reference_verilog_file_path");
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_print_top_testbench = cmd.option("print_top_testbench");
CommandOptionId opt_print_formal_verification_top_netlist = cmd.option("print_formal_verification_top_netlist");
CommandOptionId opt_print_preconfig_top_testbench = cmd.option("print_preconfig_top_testbench");
@ -69,7 +69,7 @@ void write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
*/
VerilogTestbenchOption options;
options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
options.set_reference_verilog_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
options.set_print_formal_verification_top_netlist(cmd_context.option_enable(cmd, opt_print_formal_verification_top_netlist));
options.set_print_preconfig_top_testbench(cmd_context.option_enable(cmd, opt_print_preconfig_top_testbench));
options.set_print_top_testbench(cmd_context.option_enable(cmd, opt_print_top_testbench));

7
openfpga/src/base/openfpga_verilog_command.cpp
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@ -48,7 +48,7 @@ void add_openfpga_write_fabric_verilog_command(openfpga::Shell<OpenfpgaContext>&
/* Add command 'write_fabric_verilog' to the Shell */
ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate Verilog netlists modeling full FPGA fabric");
shell.set_command_class(shell_cmd_id, cmd_class_id);
shell.set_command_execute_function(shell_cmd_id, write_verilog_testbench);
shell.set_command_execute_function(shell_cmd_id, write_fabric_verilog);
/* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
std::vector<ShellCommandId> cmd_dependency;
@ -83,8 +83,7 @@ void add_openfpga_write_verilog_testbench_command(openfpga::Shell<OpenfpgaContex
shell_cmd.add_option("print_formal_verification_top_netlist", false, "Generate a top-level module which can be used in formal verification");
/* Add an option '--print_preconfig_top_testbench' */
CommandOptionId preconfig_tb_opt = shell_cmd.add_option("print_preconfig_top_testbench", false, "Generate a pre-configured testbench for top-level fabric module with autocheck capability");
shell_cmd.set_option_require_value(preconfig_tb_opt, openfpga::OPT_STRING);
shell_cmd.add_option("print_preconfig_top_testbench", false, "Generate a pre-configured testbench for top-level fabric module with autocheck capability");
/* Add an option '--print_simulation_ini' */
CommandOptionId sim_ini_opt = shell_cmd.add_option("print_simulation_ini", false, "Generate a .ini file as an exchangeable file to enable HDL simulations");
@ -96,7 +95,7 @@ void add_openfpga_write_verilog_testbench_command(openfpga::Shell<OpenfpgaContex
/* Add command to the Shell */
ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate Verilog testbenches for full FPGA fabric");
shell.set_command_class(shell_cmd_id, cmd_class_id);
shell.set_command_execute_function(shell_cmd_id, write_fabric_verilog);
shell.set_command_execute_function(shell_cmd_id, write_verilog_testbench);
/* The command should NOT be executed before 'build_fabric' */
std::vector<ShellCommandId> cmd_dependency;

2
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -220,7 +220,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
/* Generate a Verilog file including all the netlists that have been generated */
print_include_netlists(src_dir_path,
netlist_name,
options.reference_verilog_file_path(),
options.reference_benchmark_file_path(),
circuit_lib);
}

19
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
View File

@ -13,7 +13,7 @@ namespace openfpga {
*************************************************/
VerilogTestbenchOption::VerilogTestbenchOption() {
output_directory_.clear();
reference_verilog_file_path_.clear();
reference_benchmark_file_path_.clear();
print_preconfig_top_testbench_ = false;
print_formal_verification_top_netlist_ = false;
print_top_testbench_ = false;
@ -28,8 +28,8 @@ std::string VerilogTestbenchOption::output_directory() const {
return output_directory_;
}
std::string VerilogTestbenchOption::reference_verilog_file_path() const {
return reference_verilog_file_path_;
std::string VerilogTestbenchOption::reference_benchmark_file_path() const {
return reference_benchmark_file_path_;
}
bool VerilogTestbenchOption::print_formal_verification_top_netlist() const {
@ -63,8 +63,8 @@ void VerilogTestbenchOption::set_output_directory(const std::string& output_dir)
output_directory_ = output_dir;
}
void VerilogTestbenchOption::set_reference_verilog_file_path(const std::string& reference_verilog_file_path) {
reference_verilog_file_path_ = reference_verilog_file_path;
void VerilogTestbenchOption::set_reference_benchmark_file_path(const std::string& reference_benchmark_file_path) {
reference_benchmark_file_path_ = reference_benchmark_file_path;
/* Chain effect on other options:
* Enable/disable the print_preconfig_top_testbench and print_top_testbench
*/
@ -78,12 +78,15 @@ void VerilogTestbenchOption::set_print_formal_verification_top_netlist(const boo
void VerilogTestbenchOption::set_print_preconfig_top_testbench(const bool& enabled) {
print_preconfig_top_testbench_ = enabled
&& print_formal_verification_top_netlist_
&& (!reference_verilog_file_path_.empty());
&& (!reference_benchmark_file_path_.empty());
/* Enable print formal verification top_netlist if this is enabled */
if (true == print_preconfig_top_testbench_) {
print_formal_verification_top_netlist_ = true;
}
}
void VerilogTestbenchOption::set_print_top_testbench(const bool& enabled) {
print_top_testbench_ = enabled && (!reference_verilog_file_path_.empty());
print_top_testbench_ = enabled && (!reference_benchmark_file_path_.empty());
}
void VerilogTestbenchOption::set_print_simulation_ini(const std::string& simulation_ini_path) {

6
openfpga/src/fpga_verilog/verilog_testbench_options.h
View File

@ -23,7 +23,7 @@ class VerilogTestbenchOption {
VerilogTestbenchOption();
public: /* Public accessors */
std::string output_directory() const;
std::string reference_verilog_file_path() const;
std::string reference_benchmark_file_path() const;
bool print_formal_verification_top_netlist() const;
bool print_preconfig_top_testbench() const;
bool print_top_testbench() const;
@ -39,7 +39,7 @@ class VerilogTestbenchOption {
* - print_top_testbench
* If the file path is empty, the above testbench generation will not be enabled
*/
void set_reference_verilog_file_path(const std::string& reference_verilog_file_path);
void set_reference_benchmark_file_path(const std::string& reference_benchmark_file_path);
void set_print_formal_verification_top_netlist(const bool& enabled);
/* The preconfig top testbench generation can be enabled only when formal verification top netlist is enabled */
void set_print_preconfig_top_testbench(const bool& enabled);
@ -48,7 +48,7 @@ class VerilogTestbenchOption {
void set_verbose_output(const bool& enabled);
private: /* Internal Data */
std::string output_directory_;
std::string reference_verilog_file_path_;
std::string reference_benchmark_file_path_;
bool print_formal_verification_top_netlist_;
bool print_preconfig_top_testbench_;
bool print_top_testbench_;

5
openfpga/test_script/s298_k6_frac.openfpga
View File

@ -33,9 +33,12 @@ repack #--verbose
# - Output the fabric-independent bitstream to a file
fpga_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
# Write the Verilog netlit for FPGA fabric
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
# Write the Verilog testbench for FPGA fabric
write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src --reference_benchmark_file_path /var/tmp/xtang/s298.v --print_top_testbench --print_preconfig_top_testbench
# Finish and exit OpenFPGA
exit