438bcc68c0
Add regression test for #2824 .
2021-06-11 12:06:35 +01:00
55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails
...
Fixing old e-mail addresses and deadnames
2021-06-09 13:22:52 +02:00
0ff4fb1eb3
More deadname stuff
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-06-09 12:40:33 +02:00
a734face3a
More deadname stuff
2021-06-09 12:33:41 +02:00
0ada13cbe2
Use HTTPS for website links, gatecat email
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git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g ;
2021-06-09 12:16:56 +02:00
92e705cb51
Fix files with CRLF line endings
2021-06-09 12:16:33 +02:00
2e697f5655
verilog: check for module scope identifiers during width detection
...
The recent fix for case expression width detection causes the width of
the expressions to be queried before they are simplified. Because the
logic supporting module scope identifiers only existed in simplify,
looking them up would fail during width detection. This moves the logic
to a common helper used in both simplify() and detectSignWidthWorker().
2021-06-08 15:03:16 -04:00
c79fbfe0a1
mem2reg: tolerate out of bounds constant accesses
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This brings the mem2reg behavior in line with the nomem2reg behavior.
2021-06-08 15:02:57 -04:00
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
8cfed1a979
sv: support tasks and functions within packages
2021-06-01 13:17:41 -04:00
13b901bf1c
memory_map: Improve start_offset handling.
...
Fixes #2775 .
2021-05-31 17:45:21 +02:00
18806f1ef6
memory_bram: Reuse extract_rdff helper for make_outreg.
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Also properly skip read ports with init value or reset when not making
use of make_outreg. Proper support for matching those will land later.
2021-05-25 22:42:03 +02:00
0795b3ec07
verilog: fix case expression sign and width handling
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- The case expression and case item expressions are extended to the
maximum width among them, and are only interpreted as signed if all of
them are signed
- Add overall width and sign detection for AST_CASE
- Add sign argument to genWidthRTLIL helper
- Coverage for both const and non-const case statements
2021-05-25 16:16:46 -04:00
15f35d6754
sv: support remaining assignment operators
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- Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
- Unify existing support for: +=, -=, &=, |=, ^=
2021-05-25 16:15:57 -04:00
5628f5a88f
opt_mem_feedback: Respect write port priority.
2021-05-25 15:59:41 +02:00
835688bf80
opt_mem_feedback: Rewrite feedback path finding logic.
...
Fixes #2766 .
2021-05-24 23:20:30 +02:00
1eea06bcc0
Add new helper class for merging FFs into cells, use for memory_dff.
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Fixes #1854 .
2021-05-23 14:46:59 +02:00
a23d9409e7
opt_mem: Remove write ports with const-0 EN.
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Fixes #2765 .
2021-05-23 14:30:56 +02:00
4240498f71
tests/blif: Add missing gitignore
2021-05-20 12:49:51 +02:00
34a08750fa
intel_alm: Fix illegal carry chains
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
eb106732d9
intel_alm: Add global buffer insertion
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
5dba138c87
intel_alm: Add IO buffer insertion
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
4452080861
sv: check validity of package end label
2021-05-10 14:37:32 -04:00
32a0ce9d68
blif: Use library cells' start_offset and upto for wideports.
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Fixes #2729 .
2021-05-08 15:50:03 +02:00
5c1e6a0e20
opt_dff: Fix NOT gates wired in reverse.
2021-05-04 21:03:40 +02:00
8aee80040d
Add default assignments to SB_LUT4
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-04-20 12:46:21 +02:00
dce037a62c
quicklogic: ABC9 synthesis
2021-04-17 20:54:58 +02:00
0ccc7229c0
preproc: test coverage for #2712
2021-03-30 12:23:18 -04:00
8c5f379435
abc9: uniquify blackboxes like whiteboxes ( #2695 )
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* abc9_ops: uniquify blackboxes too
* abc9_ops: update comment
* abc9_ops: allow bypass for param-less blackboxes
* Add tests
2021-03-29 22:02:06 -07:00
55dc5a4e4f
abc9: fix SCC issues ( #2694 )
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* xilinx: add SCC test for DSP48E1
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
* abc9 to break SCCs using $__ABC9_SCC_BREAKER module
* Add test
* abc9_ops: remove refs to (* abc9_keep *) on wires
* abc9_ops: do not bypass cells in an SCC
* Add myself to CODEOWNERS for abc9*
* Fix compile
* abc9_ops: run -prep_hier before scc
* Fix tests
* Remove bug reference pending fix
* abc9: fix for -prep_hier -dff
* xaiger: restore PI handling
* abc9_ops: -prep_xaiger sigmap
* abc9_ops: -mark_scc -> -break_scc
* abc9: eliminate hard-coded abc9.box from tests
Also tidy up
* Address review
2021-03-29 22:01:57 -07:00
4a35f244aa
quicklogic: Add .gitignore file for test outputs.
2021-03-23 17:35:00 +01:00
92d5550a90
verilog: check entire user type stack for type definition
2021-03-21 19:35:13 -04:00
4f4e70876f
sv: allow typenames as function return types
2021-03-19 12:08:43 -04:00
f4298b057a
quicklogic: PolarPro 3 support
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Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-18 13:28:16 +01:00
8740fdf1d7
ast: Use better parameter serialization for paramod names.
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Calling log_signal is problematic for several reasons:
- with recent changes, empty string is serialized as { }, which violates
the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
functionally different values and potentially introducing a subtle
elaboration bug
Instead, use a custom simple serialization scheme.
2021-03-18 00:52:00 +01:00
cae905f551
Blackbox all whiteboxes after synthesis
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This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
f71c2dcca6
sv: carry over global typedefs from previous files
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This breaks the ability to use a global typename as a standard
identifier in a subsequent input file. This is otherwise backwards
compatible, including for sources which previously included conflicting
typedefs in each input file.
2021-03-17 15:53:52 -04:00
092e923330
verilog: fix buf/not primitives with multiple outputs
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From IEEE1364-2005, section 7.3 buf and not gates:
> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.
yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.
2021-03-17 11:44:03 -04:00
dd6d34f461
blackbox: Include whiteboxed modules
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 13:58:04 +00:00
4f187d53c5
verilog: support module scope identifiers in parametric modules
2021-03-16 11:01:30 -04:00
a55bf6375b
proc_arst: Add special-casing of clock signal in conditionals.
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The already-existing special case for conditionals on clock has been
remade as follows:
- now triggered for the last remaining edge trigger after all others
have been converted to async reset, not just when there is only one
sync rule in the first place
- does not require all contained assignments to be constant, as opposed
to a reset conditional — merely const-folds the condition
In addition, the code has been refactored a bit; as a bonus, the
priority order of async resets found is now preserved in resulting sync
rule ordering (though this is not yet respected by proc_dff).
Fixes #2656 .
2021-03-15 17:17:29 +01:00
3af871f969
opt_clean: Remove init attribute bits together with removed DFFs.
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Fixes #2546 .
2021-03-15 17:16:53 +01:00
f965b3fa54
rtlil: Disallow 0-width chunks in SigSpec.
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Among other problems, this also fixes equality comparisons between
SigSpec by enforcing a canonical form.
Also fix another minor issue with possible non-canonical SigSpec.
Fixes #2623 .
2021-03-15 17:16:24 +01:00
640b9927fa
sv: allow globals in one file to depend on globals in another
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This defers the simplification of globals so that globals in one file
may depend on globals in other files. Adds a simplify() call downstream
because globals are appended at the end.
2021-03-12 11:22:41 -05:00
cb9f3b6abf
verilog: disallow overriding global parameters
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It was previously possible to override global parameters on a
per-instance basis. This could be dangerous when using positional
parameter bindings, hiding oversupplied parameters.
2021-03-11 12:36:51 -05:00
a3528649c8
memory_dff: Remove now-useless write port handling.
2021-03-08 20:16:29 +01:00
760284033d
proc_dff: Fix emitted FF when a register is not assigned in async reset
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Fixes #2619 .
2021-03-08 17:01:43 +01:00
d555454969
tests/bram: Do not generate write address collisions.
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These have no defined semantics, making the tests non-deterministic.
2021-03-08 16:53:03 +01:00
9bb839c613
Merge pull request #2626 from zachjs/param-no-default
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sv: support for parameters without default values
2021-03-07 05:48:03 -08:00
72ae15c77c
Merge pull request #2632 from zachjs/width-limit
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verilog: impose limit on maximum expression width
2021-03-07 03:45:41 -08:00
b1a8e73a60
sv: fix some edge cases for unbased unsized literals
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- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
2021-03-06 15:20:34 -05:00
c18ddbcd82
verilog: impose limit on maximum expression width
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Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
2021-03-04 15:20:52 -05:00
d738b2c127
sv: support for parameters without default values
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- Modules with a parameter without a default value will be automatically
deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations
2021-03-02 10:43:53 -05:00
10a6bc9b81
verilog: fix sizing of ports with int types in module headers
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Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.
2021-03-01 13:39:05 -05:00
1ec5994100
verilog: fix handling of nested ifdef directives
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- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
2021-03-01 12:28:33 -05:00
b6904a8e53
Set aside extraneous tests in simple_abc9 test suite
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New test cases on one branch may be automatically copied from simple/ to
simple_abc9/, causing failures when switching to another branch. This
updates the simple_abc9 script to set aside extraneous tests in a
non-destructive way.
2021-03-01 12:13:11 -05:00
ca5f5ffcd6
Merge pull request #2615 from zachjs/genrtlil-conflict
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genrtlil: improve name conflict error messaging
2021-03-01 08:10:19 -08:00
0f5b646ab8
sv: extended support for integer types
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- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths
2021-02-28 16:31:56 -05:00
bbff844acd
genrtlil: improve name conflict error messaging
2021-02-26 18:08:23 -05:00
d56b76bd7c
Add tests for $countbits
2021-02-26 12:28:58 -05:00
dcd9f0af23
Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off ( #2566 )
2021-02-24 15:48:15 -05:00
b05b98521c
Add tests for some common techmap files.
2021-02-24 01:07:34 +01:00
ad2960adb7
Merge pull request #2594 from zachjs/func-arg-width
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verilog: fix sizing of constant args for tasks/functions
2021-02-23 21:46:16 +00:00
ae07298a6b
machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.
2021-02-23 17:39:58 +01:00
353ace5034
machxo2: Update tribuf test to reflect active-low OE.
2021-02-23 17:39:58 +01:00
c31b17a2e2
machxo2: Add believed-to-be-correct tribuf test.
2021-02-23 17:39:58 +01:00
c7aaa88f58
machxo2: Add passing fsm, mux, and shifter tests.
2021-02-23 17:39:58 +01:00
453904dd00
machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives.
2021-02-23 17:39:58 +01:00
19b043344c
machxo2: Add dffe test.
2021-02-23 17:39:58 +01:00
84937e9689
machxo2: Add dff.ys test, fix another cells_map.v typo.
2021-02-23 17:39:58 +01:00
9cb0bae1b2
machxo2: Add test/arch/machxo2 directory (test does not pass).
2021-02-23 17:39:58 +01:00
4746ffd7b2
assertpmux: Fix crash on unused $pmux output.
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Fixes #2595 .
2021-02-22 23:30:28 +01:00
01ccb80b70
Merge pull request #2586 from zachjs/tern-recurse
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verilog: support recursive functions using ternary expressions
2021-02-21 20:56:04 +00:00
b6af90fe20
verilog: fix sizing of constant args for tasks/functions
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- Simplify synthetic localparams for normal calls to update their width
- This step was inadvertently removed alongside `added_mod_children`
- Support redeclaration of constant function arguments
- `eval_const_function` never correctly handled this, but the issue
was not exposed in the existing tests until the recent change to
always attempt constant function evaluation when all-const args
are used
- Check asserts in const_arg_loop and const_func tests
- Add coverage for width mismatch error cases
2021-02-21 15:44:43 -05:00
220cb1f7bb
verilog: error on macro invocations with missing argument lists
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This would previously complain about an undefined internal macro if the
unapplied macro had not already been used. If it had, it would
incorrectly use the arguments from the previous invocation.
2021-02-19 09:18:41 -05:00
8de2e863af
verilog: support recursive functions using ternary expressions
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This adds a mechanism for marking certain portions of elaboration as
occurring within unevaluated ternary branches. To enable elaboration of
the overall ternary, this also adds width detection for these
unelaborated function calls.
2021-02-12 14:43:42 -05:00
326f1c9db4
Merge pull request #2573 from zachjs/repeat-call
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verilog: refactored constant function evaluation
2021-02-11 19:56:41 +00:00
73d611990d
Merge pull request #2578 from zachjs/genblk-port
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verlog: allow shadowing module ports within generate blocks
2021-02-11 10:26:49 -05:00
7533534429
Add missing is_signed to type_atom
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-02-11 15:05:38 +01:00
1d5f3fe506
verlog: allow shadowing module ports within generate blocks
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This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
2021-02-07 11:48:39 -05:00
4b2f977331
genrtlil: fix signed port connection codegen failures
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This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.
2021-02-05 19:51:30 -05:00
98c4feb72f
Add check of begin/end labels for genblock
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-02-04 17:16:30 +01:00
b93b6f4285
verilog: refactored constant function evaluation
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Elaboration now attempts constant evaluation of any function call with
only constant arguments, regardless of the context or contents of the
function. This removes the concept of "recommended constant evaluation"
which previously applied to functions with `for` loops or which were
(sometimes erroneously) identified as recursive. Any function call in a
constant context (e.g., `localparam`) or which contains a constant-only
procedural construct (`while` or `repeat`) in its body will fail as
before if constant evaluation does not succeed.
2021-02-04 10:18:27 -05:00
baf1875307
Merge pull request #2529 from zachjs/unnamed-genblk
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verilog: significant block scoping improvements
2021-02-04 09:57:28 +00:00
4bc6995b9a
Merge pull request #2436 from dalance/fix_generate
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Fix begin/end in generate
2021-02-03 09:43:23 +00:00
fe74b0cd95
verilog: significant block scoping improvements
...
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-31 09:42:09 -05:00
27257a419f
verilog: strip leading and trailing spaces in macro args
2021-01-28 11:26:35 -05:00
ea79e16bab
xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
...
The presence of IS_*_INVERTED on FD* cells follows Vivado, which
apparently has been decided by a dice roll. Just assume false if the
parameter doesn't exist.
Fixes #2559 .
2021-01-27 00:32:00 +01:00
ffbd813a8c
Merge pull request #2550 from zachjs/macro-arg-spaces
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verilog: allow spaces in macro arguments
2021-01-25 10:36:07 +00:00
1096b969ef
Allow combination of rand and const modifiers
2021-01-21 08:42:05 -07:00
006c18fc11
sv: fix support wire and var data type modifiers
2021-01-20 09:16:21 -07:00
4fadcc8f25
verilog: allow spaces in macro arguments
2021-01-20 08:49:58 -07:00
e991ceeef3
Merge pull request #2547 from zachjs/plugin-so-dsym
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Add plugin.so.dSYM to .gitignore
2021-01-18 20:21:20 +00:00
4c108b4419
Add plugin.so.dSYM to .gitignore
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This artifact is automatically generated by the builtin clang on macOS
when -g is used.
2021-01-18 11:13:21 -07:00
d69ddf19da
Add typedef input/output test
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-01-18 17:31:22 +01:00
01626e6746
opt_share: Fix X and CO signal width for shifted $alu in opt_share.
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These need to be the same length as actual Y, not visible part of Y.
Fixes #2538 .
2021-01-14 14:54:08 +01:00
bc2de4567c
Merge pull request #2518 from zachjs/recursion
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verilog: improved support for recursive functions
2021-01-01 09:32:26 +00:00
2085d9a55d
verilog: improved support for recursive functions
2020-12-31 18:33:59 -07:00
75abd90829
sv: complete support for implied task/function port directions
2020-12-31 16:17:13 -07:00
750831e3e0
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
1419c8761c
Fix constants bound to redeclared function args
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The changes in #2476 ensured that function inputs like `input x;`
retained their single-bit size when instantiated with a constant
argument and turned into a localparam. That change did not handle the
possibility for an input to be redeclared later on with an explicit
width, such as `integer x;`.
2020-12-26 08:48:01 -07:00
deff6a9546
Merge pull request #2501 from zachjs/genrtlil-tern-sign
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genrtlil: fix mux2rtlil generated wire signedness
2020-12-23 23:15:56 +00:00
8ef6b77dc3
Merge pull request #2476 from zachjs/const-arg-width
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Fix constants bound to single bit arguments (fixes #2383 )
2020-12-23 23:15:30 +00:00
999eec5617
genrtlil: fix mux2rtlil generated wire signedness
2020-12-22 17:49:16 -07:00
8206546c45
Fix constants bound to single bit arguments ( fixes #2383 )
2020-12-22 17:01:03 -07:00
3e67ab1ebb
Merge pull request #2479 from zachjs/const-arg-hint
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Allow constant function calls in constant function arguments
2020-12-22 01:31:25 +00:00
0d8e5d965f
Sign extend port connections where necessary
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- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
signedness information
- Resolves #1418
- Resolves #2265
2020-12-18 20:33:14 -07:00
186d6df4c3
Allow constant function calls in constant function arguments
2020-12-07 13:53:27 -07:00
cf67e6a397
Merge pull request #2133 from dh73/nodev_head
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Adding latch tests for shift&mask AST dynamic part-select enhancements
2020-11-25 09:44:23 +01:00
9f241c9a42
nexus: DSP inference support
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Signed-off-by: David Shah <dave@ds0.me>
2020-11-20 08:45:55 +00:00
84ecb321b4
Fix begin/end in generate
2020-11-11 12:03:37 +09:00
86e0440da9
Update nexus arch tests to new harness
2020-10-29 14:42:07 +01:00
d3b6b7fe98
xilinx: Fix attributes_test.ys
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This test pretty much passes by accident — the `prep` command runs
memory_collect without memory_dff first, which prevents merging read
register into the memory, and thus blocks block RAM inference for a
reason completely unrelated to the attribute.
The attribute setting didn't actually work because it was set on the
containing module instead of the actual memory.
2020-10-24 23:52:37 +02:00
eb76d35e80
memory_dff: Fix needlessly duplicating enable bits.
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When the register being merged into the EN signal happens to be a $sdff,
the current code creates a new $mux for every bit, even if they happen
to be identical (as is usually the case), preventing proper grouping
further down the flow. Fix this by adding a simple cache.
Fixes #2409 .
2020-10-22 13:03:42 +02:00
ac0bd2ffc4
Merge pull request #2397 from daveshah1/nexus
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synth_nexus: Initial implementation
2020-10-19 11:20:56 +02:00
4d584d9319
synth_nexus: Initial implementation
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Signed-off-by: David Shah <dave@ds0.me>
2020-10-15 08:52:15 +01:00
7670a89e1f
opt_clean: Better memory handling.
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Previously, `$memwr` and `$meminit` cells were always preserved (along
with the memory itself). With this change, they are instead part of the
main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr`
cells) is only preserved iff any associated `$memrd` cell needs to be
preserved.
2020-10-08 18:05:51 +02:00
7e2fc2eaeb
Merge pull request #2378 from udif/pr_dollar_high_low
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Added $high(), $low(), $left(), $right()
2020-10-01 18:17:36 +02:00
2412e75495
Merge pull request #2380 from Xiretza/parallel-tests
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Clean up and parallelize testsuite
2020-10-01 18:12:31 +02:00
c4bfbecca6
Update .gitignore
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Signed-off-by: David Shah <dave@ds0.me>
2020-10-01 15:53:14 +01:00
dc4a617694
add tests
2020-09-28 18:16:08 +02:00
bed14241ef
tests: add gitignores for auto-generated makefiles
2020-09-26 16:28:24 +02:00
de79978372
xilinx: do not make DSP48E1 a whitebox for ABC9 by default ( #2325 )
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* xilinx: eliminate SCCs from DSP48E1 model
* xilinx: add SCC test for DSP48E1
* Update techlibs/xilinx/cells_sim.v
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
2020-09-23 09:15:24 -07:00
370243426e
switch argument order to work with macOS getopt
2020-09-23 12:48:26 +02:00
e38b830cbb
tests/simple: remove "nullglob" shopt
2020-09-21 15:07:02 +02:00
01260344d3
tests: Parallelize
2020-09-21 15:07:02 +02:00
acd47bbd52
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
f176bd7778
Merge pull request #2329 from antmicro/arrays-fix-multirange-size
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Rewrite multirange arrays sizes [n] as [n-1:0]
2020-09-17 18:27:05 +02:00
9e937961dc
Merge pull request #2330 from antmicro/arrays-fix-multirange-access
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Fix unsupported subarray access detection
2020-09-17 18:21:53 +02:00
7ed0e23e19
We can now handle array slices (e.g. $size(x[1]) etc. )
2020-09-17 00:55:17 +03:00
b548722bee
Added $high(), $low(), $left(), $right()
2020-09-15 20:49:52 +03:00
da3002e580
Merge pull request #2369 from Xiretza/gitignores
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Add missing gitignores for test artifacts
2020-09-10 13:37:49 +02:00
a10893072b
Merge pull request #2352 from zachjs/const-func-localparam
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Allow localparams in constant functions
2020-09-01 17:31:48 +02:00
3e1840d036
Merge pull request #2353 from zachjs/top-scope
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Module name scope support
2020-09-01 17:30:09 +02:00
452442ac2f
Merge pull request #2365 from zachjs/const-arg-loop-split-type
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Fix constant args used with function ports split across declarations
2020-09-01 17:28:35 +02:00
6224fd9055
Add missing gitignores for test artifacts
2020-08-31 19:43:51 +02:00
ecc5c23b4d
Fix constant args used with function ports split across declarations
2020-08-29 13:31:02 -04:00
2d10d59d93
Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmap
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flatten, techmap: don't canonicalize tpl driven bits via sigmap
2020-08-27 11:28:31 +00:00
1a07b330f8
intel_alm: Add multiply signedness to cells
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Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
2020-08-26 22:50:16 +02:00
9f0892159e
flatten, techmap: don't canonicalize tpl driven bits via sigmap.
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For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:
module foo(inout a, b);
assign a = b;
endmodule
module bar(output c);
foo f(c, 1'b0);
endmodule
Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).
This issue was introduced in 9f772eb9Fixes #2183 .
2020-08-26 16:29:42 +00:00
6127f22788
Module name scope support
2020-08-20 20:15:08 -04:00
74abc3bbfd
Allow localparams in constant functions
2020-08-20 20:10:24 -04:00
d9dd8bc748
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes
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techmap/shift_shiftx: Remove the "shiftx2mux" special path.
2020-08-20 16:25:56 +02:00
a96df40814
Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes
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opt_share: Refactor, fix some bugs.
2020-08-20 16:24:53 +02:00
799076af24
Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed
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peeopt.shiftmul: Add a signedness check.
2020-08-20 16:23:07 +02:00
6a68b8ed54
Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup
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Remove passes redundant with opt_dff
2020-08-20 16:21:58 +02:00
faf8e19511
Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fix
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techmap.CONSTMAP: Handle outputs before inputs.
2020-08-20 16:21:09 +02:00
16bb3fc8bb
Merge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-sign
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peepopt.muldiv: Add a signedness check.
2020-08-20 16:19:37 +02:00
50d532f01c
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
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Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering. This path was needlessly
overcomplicated and contained bugs.
Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling). This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.
Fixes #2346 .
2020-08-20 12:44:09 +02:00
87b9ee330d
Merge pull request #2122 from PeterCrozier/struct_array2
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Support 2D bit arrays in structures. Optimise array indexing.
2020-08-19 17:58:37 +02:00
850f66cfdd
include both power-of-two and non-power-of-two testcases
2020-08-18 18:54:22 +02:00
22765ef0a5
Merge pull request #2339 from zachjs/display-format-0s
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Allow %0s $display format specifier
2020-08-18 17:39:01 +02:00
4aa0dc4dc7
Merge pull request #2338 from zachjs/const-branch-finish
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Propagate const_fold through generate blocks and branches
2020-08-18 17:38:07 +02:00
a9681f4e06
Merge pull request #2317 from zachjs/expand-genblock
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Fix generate scoping issues
2020-08-18 17:37:11 +02:00
7f767bf2b7
Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-08-18 17:29:49 +02:00
5ee9349647
Merge pull request #2281 from zachjs/const-real
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Allow reals as constant function parameters
2020-08-18 17:22:20 +02:00
2b777bbda8
opt_share: Refactor, fix some bugs.
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Fixes #2334 .
Fixes #2335 .
Fixes #2336 .
2020-08-17 17:26:36 +02:00
2ee0b8ebea
Propagate const_fold through generate blocks and branches
2020-08-09 17:21:08 -04:00
96ec9acf84
Allow %0s $display format specifier
2020-08-09 17:19:49 -04:00
5693386a4e
Remove now-redundant dff2dffs pass.
2020-08-07 13:21:34 +02:00
a0e99a9f3f
peepopt: Remove now-redundant dffmux pattern.
2020-08-07 13:21:34 +02:00
9a4f420b4b
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
c1ed1c28be
peeopt.shiftmul: Add a signedness check.
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Fixes #2332 .
2020-08-05 21:01:20 +02:00
b4a4cb081d
techmap.CONSTMAP: Handle outputs before inputs.
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Fixes #2321 .
2020-08-05 12:28:18 +02:00
e89cc9c02f
peepopt.muldiv: Add a signedness check.
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Fixes #2318 .
2020-08-04 16:30:24 +02:00
daee2d967f
Add test for subarray access on multidimensional arrays
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 17:07:33 +02:00
6e78f3a197
Test multirange (unpacked) arrays size
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 15:34:55 +02:00
c3e95eb1ab
Fix generate scoping issues
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- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214 , resolves #1456
2020-07-31 20:32:47 -06:00
18ad56ef41
Add dffunmap pass.
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To be used with backends that cannot deal with fancy FF types (like blif
or smt).
2020-07-31 00:59:51 +02:00
6cd135a5eb
opt_expr: Remove -clkinv option, make it the default.
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Adds -noclkinv option just in case the old behavior was actually useful
to someone.
2020-07-31 00:08:15 +02:00
cf60699884
synth_ice40: Use opt_dff.
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The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:20 +02:00
8501342fc5
synth_xilinx: Use opt_dff.
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The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:09 +02:00
af6623ebb8
Add opt_dff pass.
2020-07-30 18:27:04 +02:00
dc18bf1969
opt_expr: Fix handling of $_XNOR_ cells with A = B.
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Fixes #2311 .
2020-07-29 12:41:43 +02:00
66afed6f55
Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef
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equiv_induct: Fix up assumption for $equiv cells in -undef mode.
2020-07-28 12:56:22 +02:00
a1a0abf52a
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
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Before this fix, equiv_induct only assumed that one of the following is
true:
- defined value of A is equal to defined value of B
- A is undefined
This lets through valuations where A is defined, B is undefined, and
the defined (meaningless) value of B happens to match the defined value
of A. Instead, tighten this up to OR of the following:
- defined value of A is equal to defined value of B, and B is not
undefined
- A is undefined
2020-07-27 18:36:13 +02:00
a2fb84fd0c
intel_alm: direct M10K instantiation
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This reverts commit a3a90f6377
2020-07-27 15:39:06 +02:00
62311b7ec0
intel_alm: increase abc9 -W
2020-07-26 23:56:54 +02:00
9bcde4d82b
Merge pull request #2299 from zachjs/arg-loop
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Avoid generating wires for function args which are constant
2020-07-26 21:34:55 +02:00
f69daf4830
Allow blocks with declarations within constant functions
2020-07-25 10:16:12 -06:00
59c4ad8ed3
Avoid generating wires for function args which are constant
2020-07-24 21:18:24 -06:00
1c8483b7dd
zinit: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
abe4e9e607
clk2fflogic: Support all FF types.
2020-07-24 03:19:48 +02:00
0c6d0d4b5d
satgen: Add support for dffe, sdff, sdffe, sdffce cells.
2020-07-24 03:19:21 +02:00
c0ad522cf6
Merge pull request #2285 from YosysHQ/mwk/techmap-cellname
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techmap: Add _TECHMAP_CELLNAME_ special parameter.
2020-07-23 18:39:42 +02:00
4d9d90079c
intel_alm: add additional ABC9 timings
2020-07-23 11:57:07 +01:00
dc07ae9677
techmap: Add _TECHMAP_CELLNAME_ special parameter.
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This parameter will resolve to the name of the cell being mapped. The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
2020-07-21 15:00:54 +02:00
f285f7b769
Allow reals as constant function parameters
2020-07-19 20:27:09 -06:00
910f421324
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic
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anlogic: Use dfflegalize.
2020-07-16 18:07:58 +02:00
021ce8e596
Merge pull request #2257 from antmicro/fix-conflicts
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Restore #2203 and #2244 and fix parser conflicts
2020-07-15 11:49:09 +02:00
3050454d6e
anlogic: Use dfflegalize.
2020-07-14 05:02:50 +02:00
a3a90f6377
Revert "intel_alm: direct M10K instantiation"
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This reverts commit 09ecb9b2cf
2020-07-13 18:05:38 +02:00
347dd01c2f
xilinx: Fix srl regression.
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Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9. Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
2020-07-12 23:41:27 +02:00
de649b9194
Revert "Revert PRs #2203 and #2244."
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This reverts commit 9c120b89ac
2020-07-10 09:59:48 +02:00
9c120b89ac
Revert PRs #2203 and #2244 .
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This reverts commit 7e83a51fc9b422f2e4d07cb56f34b06f9be939bd76a34dc5f3
2020-07-09 19:36:32 +00:00
7ed9d18907
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
32d2cc8c28
clkbufmap: improve input pad handling.
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- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
buffer
2020-07-09 18:48:01 +02:00
802671b22e
Merge pull request #2244 from antmicro/logic
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Add logic type support to parameters
2020-07-09 18:39:30 +02:00
03e28f7ab4
clk2fflogic: Consistently treat async control signals as negative hold.
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This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
2020-07-09 18:12:47 +02:00
e9c2c1b717
dfflegalize: Add special support for const-D latches.
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Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q. Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.
2020-07-09 18:11:32 +02:00
c73ebeb90e
gowin: Use dfflegalize.
2020-07-06 12:27:46 +02:00
b422f2e4d0
Add logic param and integer bad syntax tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-06 09:18:48 +02:00
09ecb9b2cf
intel_alm: direct M10K instantiation
2020-07-05 23:28:59 +02:00
7f45cab27a
synth_gowin: ABC9 support
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This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
2020-07-05 22:07:17 +02:00
0d4c2f0a65
intel_alm: add Cyclone 10 GX tests
2020-07-05 21:36:38 +02:00
7afcb72c98
opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.
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Fixes #2221 .
2020-07-05 06:31:58 +02:00
b004f09018
intel_alm: DSP inference
2020-07-05 05:39:20 +02:00
3ca2de0f77
synth_intel_alm: Use dfflegalize.
2020-07-04 22:56:16 +02:00
c6765443fd
Improve MISTRAL_FF specify rules
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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2020-07-04 19:45:10 +02:00
52fbaeca07
tests: update fsm.ys resource count
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Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862 ?
2020-07-04 19:45:10 +02:00
5428666151
Merge pull request #2186 from YosysHQ/mwk/dfflegalize
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Add dfflegalize pass.
2020-07-02 17:46:11 +02:00
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar
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Signed and macro grammar update
2020-07-01 16:41:32 +02:00
8ce4f8790e
Merge pull request #2179 from splhack/static-cast
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Support SystemVerilog Static Cast
2020-07-01 16:40:20 +02:00
6b42819a37
dfflegalize: Add tests.
2020-07-01 01:57:15 +02:00
27cec16cda
Allow constant function calls in for loops and generate if and case
2020-06-29 16:06:17 -06:00
76a34dc5f3
Add signed/unsigned tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-26 15:38:20 +02:00
39c39848a2
Add sub-assign and and-assign tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-25 14:32:05 +02:00
470df03f3d
Move combined assign tests to single file
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-25 14:19:16 +02:00
f6d06c9f7b
Add xor-assignment test
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 14:46:21 +02:00
a5ca4eeefb
Add or-assignment and plus-assignment tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:56:26 +02:00
88e7f90663
Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
6bf75be73b
static cast: add tests
2020-06-19 17:40:38 -07:00
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
8b4eb78849
intel_alm: fix DFFE matching
2020-06-11 19:55:51 +02:00
d68a8f9e2b
Removing trailing whitespace
2020-06-10 10:35:40 -05:00
b3b515087d
Fix tests/opt/opt_rmdff
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This only passed before because "prep" was also running opt_rmdff
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 22:48:26 +02:00
3c2a1171ff
Adding latch tests for shift&mask AST dynamic part-select enhancements
2020-06-09 15:17:01 -05:00
01ec681373
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 20:34:52 +01:00
76c499db71
Support packed arrays in struct/union.
2020-06-07 18:33:11 +01:00
7112f187cd
Add missing .gitignore file
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 22:25:47 +02:00
352731df4e
Merge pull request #2041 from PeterCrozier/struct
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Implementation of SV structs.
2020-06-04 18:26:07 +02:00
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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abc9: -dff improvements
2020-06-04 08:15:25 -07:00
45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
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abc9: fixes around handling combinatorial loops
2020-06-03 17:35:46 -07:00
0d3f7ea011
Merge branch 'master' into struct
2020-06-03 17:19:28 +01:00
8a11019d38
tests: tidy up testcase
2020-06-03 08:41:55 -07:00
46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings
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tests: reduce test warnings
2020-06-03 08:37:07 -07:00
0a88f002e5
allow range for mux test
2020-06-01 13:48:19 +02:00
ea4374a223
abc9_ops: update messaging (credit to @Xiretza for spotting)
2020-05-30 08:57:48 -07:00
d3b53bc495
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
2020-05-29 17:17:40 -07:00
0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
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ast/simplify: don't bitblast async ROMs declared as `logic`
2020-05-29 16:52:11 +02:00
6a2bac21d3
Expand tests/simple/constmuldivmod.v
2020-05-28 22:59:04 +02:00
abac0ab28e
Merge pull request #2091 from boqwxp/printattrs
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Add `printattrs` command to print attributes of currently selected objects.
2020-05-28 10:25:34 +00:00
6228b10c9f
printattrs: Add test.
2020-05-27 08:00:00 +00:00
1dce798dc5
tests: add ecp5 latch testcase with -abc9
2020-05-25 16:39:16 -07:00
a7f2ef6d34
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
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xilinx: tidy up cells_sim.v a little
2020-05-25 14:21:10 -07:00
08221edbc1
tests: xilinx macc test to have initval, shorten BMC depth for runtime
2020-05-25 10:09:05 -07:00
60aa804915
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
9c6d216a06
tests: add test for abc9 -dff removing a redundant flop entirely
2020-05-25 08:43:33 -07:00
8dd93e389e
tests: add testcase for abc9 -dff preserving flop names
2020-05-25 08:43:33 -07:00
95dcd7e785
test: add attribute-before-stmt test from @nakengelhardt
2020-05-25 07:36:53 -07:00
1c117ac023
verilog: do not warn for attributes on null statements
2020-05-25 07:36:53 -07:00
29d84339bf
tests: add an generate-else test too
2020-05-25 07:36:53 -07:00
589775538c
tests: add #2037 testcase
2020-05-25 07:36:53 -07:00
33b03ce904
xaiger: add testcase
2020-05-24 08:48:23 -07:00
574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
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verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
2020-05-21 11:00:36 -07:00
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
e7fd8912f0
tests: attributes before task enable
2020-05-14 16:09:41 -07:00
73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
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opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
2020-05-14 11:56:22 -07:00
13f9d65b6f
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
2020-05-14 10:33:57 -07:00
7cd3f4a79b
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
2020-05-14 10:33:56 -07:00
722540dbf9
abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
2020-05-14 10:33:56 -07:00
5ad3a85288
abc9: test to use box file instead of auto
2020-05-14 10:33:56 -07:00
48052ad813
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
2020-05-14 10:33:56 -07:00
8d7b3c06b2
abc9: suppress warnings when no compatible + used flop boxes formed
2020-05-14 10:33:56 -07:00
cdd250ef16
xilinx: update abc9_dff tests
2020-05-14 10:33:56 -07:00
762b6ad74a
xilinx: remove no-longer-relevant test
2020-05-14 10:33:56 -07:00
5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042
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verilog: error if no direction given for task arguments, default to input in SV mode
2020-05-14 09:45:54 -07:00
140e9a8e06
Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes
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opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
2020-05-14 18:31:16 +02:00
ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
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ast: swap range regardless of range_left >= 0
2020-05-14 18:06:18 +02:00
56a5b1d2da
test: add another testcase as per @nakengelhardt
2020-05-14 08:36:36 -07:00
5be4b00a0d
opt_clean: improve warning message
2020-05-14 00:59:38 -07:00
aa4a69f89b
opt_clean: add init test
2020-05-14 00:31:08 -07:00
0d2c33f9f4
tests: update/extend task argument tests
2020-05-13 10:11:45 -07:00
17f050d3c6
Allow structs within structs.
2020-05-12 17:20:34 +01:00
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
e5ce5a4fd5
tests: add #2042 testcase
2020-05-11 11:05:19 -07:00
b11cf67a81
Setup tests/verilog properly
2020-05-11 10:31:02 -07:00
49e64ad492
test: update opt_expr_alu test
2020-05-08 11:12:58 -07:00
495acf9815
tests: opt_expr tests that depend on consumex
2020-05-08 11:07:11 -07:00
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
5b779f7f4e
intel_alm: direct LUTRAM cell instantiation
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By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
a299e606f8
Merge pull request #2028 from zachjs/master
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verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00
8f9bba1bbf
verilog: allow null gen-if then block
2020-05-06 08:43:02 -04:00
004999218f
techlibs/common: more robustness when *_WIDTH = 0
2020-05-05 08:01:27 -07:00
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
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verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
66d0ed2bcc
ast/simplify: don't bitblast async ROMs declared as `logic`.
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Fixes #2020 .
2020-05-05 04:16:59 +00:00
2e911bc806
test: add failing test
2020-05-04 12:18:02 -07:00
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
ad8e7878f6
tests: add tests for primitives' src
2020-05-04 10:21:47 -07:00
5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu
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Fix the other "opt_expr -fine" bug introduced in 213a89558
2020-05-03 11:56:29 +02:00
db13852ed6
test: add test for #2014
2020-05-02 14:22:37 -07:00
2e78daf1ca
tests: aiger test for wire->start_offset != 0
2020-05-02 10:00:32 -07:00
f38d76efbf
Bugfix in partsel.v signed indices test cases
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
749c2ff84a
Add tests based on the test case from #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
7f9ecddb7f
Add testcase for #2010
2020-05-01 14:07:33 -07:00
7f203cb019
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
b5f38f8342
opt_expr: const_xnor replacement to pad Y with 1'b1
2020-04-24 14:13:45 -07:00
ebd6fa945d
tests: opt_expr update xnor/xor tests
2020-04-24 11:16:25 -07:00
90b71eb84b
opt_expr: do not group by X, more fixes
2020-04-23 18:15:07 -07:00
b84415094c
tests: add opt_expr tests
2020-04-23 15:58:36 -07:00
3d149aff73
intel_alm: work around a Quartus ICE
2020-04-23 11:03:28 +02:00
988d47af85
tests: read +/xilinx/cell_sim.v before xilinx_dsp test
2020-04-22 17:50:30 -07:00
db09e96dff
test: ice40_dsp test to read +/ice40/cells_sim.v for default params
2020-04-22 16:35:35 -07:00
f582eb14af
xilinx: xilinx_dffopt to read cells_sim.v; fix test
2020-04-22 16:25:23 -07:00
fa9df06c9d
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
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select: do not select inside black-/white- boxes unless '=' prefix used
2020-04-22 15:35:05 -07:00
db27f2f378
Merge pull request #1973 from YosysHQ/eddie/fix1966
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tests: fix various/plugin.sh when PREFIX != /usr/local/share
2020-04-22 10:19:30 -07:00
281cd10717
tests: update select black/white-box tests
2020-04-22 10:16:14 -07:00
28623f19ee
Merge pull request #1950 from YosysHQ/eddie/design_import
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design: -import to not count black/white-boxes as candidates for top
2020-04-22 09:32:13 -07:00
634b5e2d9f
tests: use `yosys-config --datdir` instead of hard-coded
2020-04-22 08:29:45 -07:00
c32b4bded5
Merge pull request #1976 from YosysHQ/dave/fix-sim-const
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sim: Fix handling of constant-connected cell inputs at startup
2020-04-22 16:57:34 +02:00
846c79b312
hierarchy: Convert positional parameters to named.
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Fixes #1821 .
2020-04-21 19:09:00 +02:00
9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite
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Improved rewrite code for writing to bit slice
2020-04-21 18:46:52 +02:00
abf81c7639
sim: Fix handling of constant-connected cell inputs at startup
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-21 08:58:52 +01:00
38ee59184c
tests: remove write_ilang
2020-04-20 15:42:29 -07:00
caf4071c8b
Remove '-ignore_unknown_cells' option from 'sat'
2020-04-20 11:58:23 -07:00
a1573058e9
Simplify test case script
2020-04-20 11:54:10 -07:00
99a0958601
Remove ununsed files
2020-04-20 11:53:48 -07:00
22f440506b
Modifications of tests as per Eddie's request
2020-04-20 12:45:35 -05:00
34d8ff8b56
abc9: add testcase reduced from #1970
2020-04-20 09:38:29 -07:00
50581d5a94
Wrong fixed value
2020-04-17 10:15:22 -05:00
9eace8f360
design: add test
2020-04-16 12:48:40 -07:00
2ddfb61e65
select: add test for not selecting inside black/white boxes
2020-04-16 12:45:04 -07:00
87910732f1
Adding tests for dynamic part select optimisation
2020-04-16 13:31:05 -05:00
2623e335cc
tests: add select -unset tests
2020-04-16 10:51:58 -07:00
e8a841467f
tests: add design -delete tests
2020-04-16 08:05:18 -07:00
2b57c06360
Merge pull request #1943 from YosysHQ/dave/fix-1919
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ast: Fix handling of identifiers in the global scope
2020-04-16 13:48:20 +01:00
2f8541a92e
opt_expr: Fix X and CO outputs for $alu identity-mapping rules.
2020-04-16 11:48:29 +02:00
4d02505820
ast: Fix handling of identifiers in the global scope
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
33b0ac9269
Merge pull request #1933 from YosysHQ/eddie/zinit_more
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zinit: handle $__DFFS?E?_[NP][NP][01] too
2020-04-15 08:36:25 -07:00
4ee8fc1473
Merge pull request #1930 from YosysHQ/claire/fix1876
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Fix handling of ternary with constant condition
2020-04-15 16:01:19 +02:00
2e37e62e6b
synth_intel_alm: alternative synthesis for Intel FPGAs
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By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
383fe4a4bc
tests: zinit for new types
2020-04-14 13:08:37 -07:00
6c16fd760b
opt_expr: Add more $alu optimizations.
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Detect the places in the $alu where the carry bit is constant (due to
const A[i] == B[i] ^ BI) and split it into smaller $alu at these points.
Also, make the existing const-carry detection for low bits more generic
(now handles cases where both BI and CI are constant, but not equal to
one another).
Fixes #1912 .
2020-04-14 21:48:13 +02:00
e7121cc15c
tests: add testcases from #1876
2020-04-14 12:39:10 -07:00
7a36728b2f
dffinit: Avoid setting init parameter to zero-length value.
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Fixes #1704 .
2020-04-14 19:52:19 +02:00
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl
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support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
b75c5bf743
zinit: resolve one more comment by @mwkmwkmwk
2020-04-13 15:25:37 -07:00
c6afce7638
zinit: fix review comments from @mwkmwkmwk
2020-04-13 15:16:51 -07:00
091297b9ee
tests: zinit on $adff
2020-04-13 14:29:44 -07:00
3c5a9411b1
Add testcase for $_DFF_[NP][NP][01]_
2020-04-13 13:16:49 -07:00
840bb17089
opt_expr: Optimize multiplications with low 0 bits in operands.
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Fixes #1500 .
2020-04-13 16:52:22 +02:00
7f1d83c5db
Add .gitignore to tests/select/
2020-04-12 22:45:45 +02:00
93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style
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ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
2020-04-10 14:51:01 +00:00
f11dd6e208
tests: add a quick plugin test
2020-04-09 09:45:20 -07:00
249876b614
support using previously declared types/localparams/params in package
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(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
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"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
2020-04-03 16:28:25 -07:00
92d70cafec
+/cmp2lcu.v to work efficiently for fully/partially constant inputs
2020-04-03 14:28:22 -07:00
f68d723cdc
Refactor +/cmp2lcu.v into recursive techmap
2020-04-03 14:28:22 -07:00
9b63700678
techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu
2020-04-03 14:28:22 -07:00
763401fc82
ecp5: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
ebee746ad2
ice40: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
2d3753d730
iopadmap: Fix z assignment to inout port
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Fixes #1841 .
2020-04-02 18:15:04 +02:00
4ae7f3a8ed
Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor
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opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
2020-04-01 14:17:01 -07:00
e79bc45975
Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu
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opt_expr: improve performance on $alu and $sub
2020-04-01 14:11:09 -07:00
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
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ast: simplify to fully populate dynamic slicing case transformation
2020-04-01 08:38:14 +02:00
1bb5a5215f
Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup
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opt_merge: speedup
2020-03-31 14:50:32 -07:00
3df66027e0
Add dynamic slicing Verilog testcase
2020-03-31 11:51:31 -07:00
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope
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Support module/package/interface/block scope for typedef names.
2020-03-30 13:55:39 +02:00
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
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This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
590d8eccb7
Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix
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techmap: Fix cell names with _TECHMAP_REPLACE_.*
2020-03-26 19:03:37 +01:00
ecc22f7fed
Support module/package/interface/block scope for typedef names.
2020-03-23 20:07:22 +00:00
3e46faa58c
Merge pull request #1763 from boqwxp/issue1762
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Closes #1762 . Adds warnings for `select` arguments not matching any object and for `add` command when no modules selected
2020-03-23 20:14:13 +01:00
0da65d498b
Do not warn on empty selection with prefixed `arg_memb`.
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Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-03-23 17:50:11 +00:00
ca4e5dd56e
Suppress warnings for empty `select` arguments when `-count` or `-assert-*` options are set.
2020-03-23 17:30:53 +00:00
1b333d49ef
Add tests for `select` command warnings.
2020-03-23 17:30:53 +00:00
b86905d952
Merge pull request #1803 from Grazfather/typedef
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Support standard typedef grammar (Fixed)
2020-03-23 13:43:35 +01:00
c2bf11e42a
techmap: Fix cell names with _TECHMAP_REPLACE_.*
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Fixes #1804 .
2020-03-23 11:17:07 +01:00
6d8d6b402f
Revert typedef tests to standard grammar.
2020-03-22 18:20:46 -07:00
6274f0b075
opt_expr: add failing $xnor test
2020-03-20 14:38:50 -07:00
fa77fb857b
Add test for abc9+mince issue
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-20 20:35:28 +00:00
317c18fc6f
Simplify breaking tests/arch/*/fsm.ys tests
2020-03-20 11:25:17 -07:00
81ca776ea4
opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests
2020-03-19 16:59:11 -07:00
5e2562f1a2
opt_expr: add $alu tests
2020-03-19 14:57:10 -07:00
e91368a5f4
fsm_extract: Initialize celltypes with full design.
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Fixes #1781 .
2020-03-19 18:51:21 +01:00
e03f725ef2
Merge pull request #1774 from boqwxp/exec
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Add `exec` command to allow running shell commands from inside Yosys scripts
2020-03-19 13:14:43 +01:00
644deb708d
fix argument order for macOS compatibility
2020-03-18 15:11:49 +01:00
9f30d7f843
opt_merge: speedup
2020-03-16 12:43:54 -07:00
a09b260c01
Add test for `exec` command.
2020-03-16 07:52:58 +00:00
569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux
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refixed parsing of constant with comment between size and value
2020-03-14 13:34:59 +02:00
dd562f29e7
Add regression tests for new handling of comments in constants
2020-03-14 11:41:09 +01:00
faf4ee69de
Merge pull request #1754 from boqwxp/precise_locations
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Set AST node source location in more parser rules.
2020-03-14 11:18:39 +02:00
5b73e7c63a
Added back tests for logger
2020-03-13 15:00:18 +01:00
3ada82639f
verilog: add test
2020-03-11 06:51:03 -07:00
ddcd87b577
Merge pull request #1721 from YosysHQ/dave/tribuf-unused
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deminout: Don't demote inouts with unused bits
2020-03-10 13:51:40 +00:00
a7cc4673c3
Fix partsel expr bit width handling and add test case
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-08 16:12:12 +01:00
88494e81f5
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
3c2e910bb3
tests: extend tests/arch/run-tests.sh for defines
2020-03-05 08:08:32 -08:00
5cae9c6e16
deminout: Don't demote inouts with unused bits
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-04 18:44:38 +00:00
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
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Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
879124333f
Merge pull request #1519 from YosysHQ/eddie/submod_po
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submod: several bugfixes
2020-03-03 08:19:06 -08:00
968956badb
iopadmap: Look harder for already-present buffers. ( #1731 )
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iopadmap: Look harder for already-present buffers.
Fixes #1720 .
2020-03-02 21:40:09 +01:00
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
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abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
2020-03-02 12:32:27 -08:00
5bba9c3640
ast: fixes #1710 ; do not generate RTLIL for unreachable ternary
2020-02-27 16:55:55 -08:00
a179d918ec
Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"
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This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
2020-02-27 10:17:29 -08:00
f858219c4e
Cleanup tests
2020-02-27 10:17:29 -08:00
717fb492b3
Update bug1630.ys to use -lut 4 instead of lut file
2020-02-27 10:17:29 -08:00
bc97e64b21
Fix tests/arch/xilinx/fsm.ys to count flops only
2020-02-27 10:17:29 -08:00
977262c803
Update simple_abc9 tests
2020-02-27 10:17:29 -08:00
Marcelina Kościelnicka
Claire Xen
Zachary Snow
gatecat
Lofty
Eddie Hung
Xiretza
whitequark
Michael Singer
TimRudy
William D. Jones
Kamil Rakoczy
Claire Xen
David Shah
dalance
Miodrag Milanović
N. Engelhardt
Udi Finkelstein
Lukasz Dalek
Kazuki Sakamoto
diego
Peter Crozier
Alberto Gonzalez
Claire Wolf
Jeff Wang
Rupert Swarbrick
Marcus Comstedt