mirror of https://github.com/YosysHQ/yosys.git
sv: carry over global typedefs from previous files
This breaks the ability to use a global typename as a standard identifier in a subsequent input file. This is otherwise backwards compatible, including for sources which previously included conflicting typedefs in each input file.
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@ -61,8 +61,11 @@ static void add_package_types(dict<std::string, AST::AstNode *> &user_types, std
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}
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}
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}
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user_type_stack.clear();
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user_type_stack.push_back(new UserTypeMap());
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// carry over typedefs from previous files, but allow them to be overridden
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// note that these type maps are currently never reclaimed
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if (user_type_stack.empty() || !user_type_stack.back()->empty())
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user_type_stack.push_back(new UserTypeMap());
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}
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struct VerilogFrontend : public Frontend {
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@ -0,0 +1,23 @@
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read_verilog -sv <<EOF
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typedef logic T;
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EOF
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read_verilog -sv <<EOF
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typedef T [3:0] S;
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EOF
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read_verilog -sv <<EOF
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module top;
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T t;
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S s;
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always @* begin
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assert ($bits(t) == 1);
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assert ($bits(s) == 4);
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end
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endmodule
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EOF
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proc
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opt -full
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select -module top
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sat -verify -seq 1 -tempinduct -prove-asserts -show-all
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@ -0,0 +1,37 @@
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read_verilog -sv <<EOF
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typedef logic T;
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typedef T [3:0] S;
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EOF
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read_verilog -sv <<EOF
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module example;
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// S and T refer to the definitions from the first file
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T t;
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S s;
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always @* begin
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assert ($bits(t) == 1);
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assert ($bits(s) == 4);
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end
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endmodule
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typedef byte T;
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typedef T S;
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module top;
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// S and T refer to the most recent overrides
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T t;
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S s;
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always @* begin
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assert ($bits(t) == 8);
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assert ($bits(s) == 8);
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end
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example e();
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endmodule
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EOF
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hierarchy
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proc
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flatten
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opt -full
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select -module top
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sat -verify -seq 1 -tempinduct -prove-asserts -show-all
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