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Add default assignments to SB_LUT4 

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2021-03-15 23:27:55 +01:00
parent dce037a62c
commit 8aee80040d
2 changed files with 18 additions and 2 deletions
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18
techlibs/ice40/cells_sim.v
View File

@ -2,6 +2,16 @@
`define SB_DFF_REG reg Q = 0
// `define SB_DFF_REG reg Q
`ifndef NO_ICE40_DEFAULT_ASSIGNMENTS
`define ICE40_DEFAULT_ASSIGNMENT_V(v) = v
`define ICE40_DEFAULT_ASSIGNMENT_0 = 1'b0
`define ICE40_DEFAULT_ASSIGNMENT_1 = 1'b1
`else
`define ICE40_DEFAULT_ASSIGNMENT_V(v)
`define ICE40_DEFAULT_ASSIGNMENT_0
`define ICE40_DEFAULT_ASSIGNMENT_1
`endif
// SiliconBlue IO Cells
module SB_IO (
@ -164,7 +174,13 @@ endmodule
// SiliconBlue Logic Cells
(* abc9_lut=1, lib_whitebox *)
module SB_LUT4 (output O, input I0, I1, I2, I3);
module SB_LUT4 (
output O,
input I0 `ICE40_DEFAULT_ASSIGNMENT_0,
input I1 `ICE40_DEFAULT_ASSIGNMENT_0,
input I2 `ICE40_DEFAULT_ASSIGNMENT_0,
input I3 `ICE40_DEFAULT_ASSIGNMENT_0
);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];

2
tests/arch/run-test.sh
View File

@ -11,7 +11,7 @@ for arch in ../../techlibs/*; do
if [ "${defines[$arch_name]}" ]; then
for def in ${defines[$arch_name]}; do
echo -n "Test $path -D$def ->"
iverilog -t null -I$arch -D$def $path
iverilog -t null -I$arch -D$def -DNO_ICE40_DEFAULT_ASSIGNMENTS $path
echo " ok"
done
else