mirror of https://github.com/YosysHQ/yosys.git
sv: extended support for integer types
- Standard data declarations can now use any integer type - Parameters and localparams can now use any integer type - Function returns types can now use any integer type - Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits) - Added longint type (64 bits) - Unified parser source for integer type widths
This commit is contained in:
Zachary Snow
parent
d882b6fe3c
commit
0f5b646ab8
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@ -267,6 +267,7 @@ static bool isUserType(std::string &s)
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"int" { SV_KEYWORD(TOK_INT); }
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"byte" { SV_KEYWORD(TOK_BYTE); }
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"shortint" { SV_KEYWORD(TOK_SHORTINT); }
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"longint" { SV_KEYWORD(TOK_LONGINT); }
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"eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
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"s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
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@ -253,6 +253,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
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struct specify_rise_fall *specify_rise_fall_ptr;
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bool boolean;
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char ch;
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int integer;
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}
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%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
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@ -278,15 +279,17 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
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%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
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%token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
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%token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_UNIQUE0 TOK_PRIORITY
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%token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION
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%token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_LONGINT TOK_UNION
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%token TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AND_ASSIGN TOK_SUB_ASSIGN
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%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
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%type <ast> range range_or_multirange non_opt_range non_opt_multirange
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%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list non_io_wire_type io_wire_type
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%type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
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%type <string> type_name
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%type <ast> opt_enum_init enum_type struct_type non_wire_data_type
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%type <boolean> opt_signed opt_property always_comb_or_latch always_or_always_ff
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%type <ast> opt_enum_init enum_type struct_type non_wire_data_type func_return_type
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%type <boolean> opt_property always_comb_or_latch always_or_always_ff
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%type <boolean> opt_signedness_default_signed opt_signedness_default_unsigned
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%type <integer> integer_atom_type
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%type <al> attr case_attr
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%type <ast> struct_union
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@ -716,12 +719,19 @@ wire_type_token:
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logic_type:
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TOK_LOGIC {
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} |
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TOK_INTEGER {
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astbuf3->range_left = 31;
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integer_atom_type {
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astbuf3->range_left = $1 - 1;
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astbuf3->range_right = 0;
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astbuf3->is_signed = true;
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};
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integer_atom_type:
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TOK_INTEGER { $$ = 32; } |
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TOK_INT { $$ = 32; } |
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TOK_SHORTINT { $$ = 16; } |
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TOK_LONGINT { $$ = 64; } |
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TOK_BYTE { $$ = 8; } ;
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non_opt_range:
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'[' expr ':' expr ']' {
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$$ = new AstNode(AST_RANGE);
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@ -766,11 +776,6 @@ range_or_multirange:
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range { $$ = $1; } |
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non_opt_multirange { $$ = $1; };
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range_or_signed_int:
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range { $$ = $1; }
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| TOK_INTEGER { $$ = makeRange(); }
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;
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module_body:
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module_body module_body_stmt |
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/* the following line makes the generate..endgenrate keywords optional */
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@ -841,29 +846,58 @@ task_func_decl:
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current_function_or_task = NULL;
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ast_stack.pop_back();
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} |
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attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
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attr TOK_FUNCTION opt_automatic func_return_type TOK_ID {
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current_function_or_task = new AstNode(AST_FUNCTION);
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current_function_or_task->str = *$6;
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current_function_or_task->str = *$5;
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append_attr(current_function_or_task, $1);
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ast_stack.back()->children.push_back(current_function_or_task);
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ast_stack.push_back(current_function_or_task);
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AstNode *outreg = new AstNode(AST_WIRE);
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outreg->str = *$6;
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outreg->is_signed = $4;
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outreg->str = *$5;
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outreg->is_signed = false;
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outreg->is_reg = true;
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if ($5 != NULL) {
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outreg->children.push_back($5);
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outreg->is_signed = $4 || $5->is_signed;
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$5->is_signed = false;
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if ($4 != NULL) {
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outreg->children.push_back($4);
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outreg->is_signed = $4->is_signed;
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$4->is_signed = false;
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}
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current_function_or_task->children.push_back(outreg);
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current_function_or_task_port_id = 1;
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delete $6;
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delete $5;
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} task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
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current_function_or_task = NULL;
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ast_stack.pop_back();
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};
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func_return_type:
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opt_type_vec opt_signedness_default_unsigned {
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$$ = makeRange(0, 0, $2);
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} |
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opt_type_vec opt_signedness_default_unsigned non_opt_range {
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$$ = $3;
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$$->is_signed = $2;
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} |
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integer_atom_type opt_signedness_default_signed {
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$$ = makeRange($1 - 1, 0, $2);
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};
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opt_type_vec:
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%empty
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| TOK_REG
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| TOK_LOGIC
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;
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opt_signedness_default_signed:
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%empty { $$ = true; }
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| TOK_SIGNED { $$ = true; }
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| TOK_UNSIGNED { $$ = false; }
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;
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opt_signedness_default_unsigned:
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%empty { $$ = false; }
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| TOK_SIGNED { $$ = true; }
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| TOK_UNSIGNED { $$ = false; }
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;
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dpi_function_arg:
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TOK_ID TOK_ID {
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current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
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@ -889,14 +923,6 @@ opt_automatic:
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TOK_AUTOMATIC |
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%empty;
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opt_signed:
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TOK_SIGNED {
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$$ = true;
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} |
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%empty {
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$$ = false;
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};
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task_func_args_opt:
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'(' ')' | %empty | '(' {
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albuf = nullptr;
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@ -1379,11 +1405,8 @@ param_signed:
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} | %empty;
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param_integer:
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TOK_INTEGER {
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astbuf1->children.push_back(new AstNode(AST_RANGE));
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astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
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astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
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astbuf1->is_signed = true;
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type_atom {
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astbuf1->is_reg = false;
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};
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param_real:
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@ -1399,7 +1422,13 @@ param_range:
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};
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param_integer_type: param_integer param_signed;
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param_range_type: type_vec param_signed param_range;
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param_range_type:
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type_vec param_signed {
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addRange(astbuf1, 0, 0);
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} |
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type_vec param_signed non_opt_range {
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astbuf1->children.push_back($3);
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};
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param_implicit_type: param_signed param_range;
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param_type:
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@ -1496,11 +1525,12 @@ enum_base_type: type_atom type_signing
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| %empty { astbuf1->is_reg = true; addRange(astbuf1); }
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;
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type_atom: TOK_INTEGER { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1); } // 4-state signed
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| TOK_INT { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1); } // 2-state signed
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| TOK_SHORTINT { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1, 15, 0); } // 2-state signed
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| TOK_BYTE { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1, 7, 0); } // 2-state signed
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;
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type_atom:
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integer_atom_type {
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astbuf1->is_reg = true;
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astbuf1->is_signed = true;
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addRange(astbuf1, $1 - 1, 0);
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};
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type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned
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| TOK_LOGIC { astbuf1->is_logic = true; } // unsigned
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@ -0,0 +1,47 @@
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`define TEST(typ, width, is_signed) \
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if (1) begin \
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typ x = -1; \
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localparam typ y = -1; \
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logic [127:0] a = x; \
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logic [127:0] b = y; \
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if ($bits(x) != width) \
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$error(`"typ doesn't have expected size width`"); \
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if ($bits(x) != $bits(y)) \
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$error(`"localparam typ doesn't match size of typ`"); \
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function automatic typ f; \
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input integer x; \
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f = x; \
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endfunction \
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logic [127:0] c = f(-1); \
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always @* begin \
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assert (x == y); \
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assert (a == b); \
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assert (a == c); \
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assert ((a == -1) == is_signed); \
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end \
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end
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`define TEST_INTEGER_ATOM(typ, width) \
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`TEST(typ, width, 1) \
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`TEST(typ signed, width, 1) \
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`TEST(typ unsigned, width, 0)
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`define TEST_INTEGER_VECTOR(typ) \
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`TEST(typ, 1, 0) \
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`TEST(typ signed, 1, 1) \
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`TEST(typ unsigned, 1, 0) \
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`TEST(typ [1:0], 2, 0) \
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`TEST(typ signed [1:0], 2, 1) \
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`TEST(typ unsigned [1:0], 2, 0)
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module top;
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`TEST_INTEGER_ATOM(integer, 32)
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`TEST_INTEGER_ATOM(int, 32)
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`TEST_INTEGER_ATOM(shortint, 16)
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`TEST_INTEGER_ATOM(longint, 64)
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`TEST_INTEGER_ATOM(byte, 8)
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`TEST_INTEGER_VECTOR(reg)
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`TEST_INTEGER_VECTOR(logic)
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`TEST_INTEGER_VECTOR(bit)
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endmodule
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@ -0,0 +1,7 @@
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read_verilog -sv int_types.sv
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hierarchy
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proc
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flatten
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opt -full
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select -module top
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sat -verify -seq 1 -tempinduct -prove-asserts -show-all
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@ -0,0 +1,19 @@
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module gate(out);
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parameter integer a = -1;
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parameter int b = -2;
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parameter shortint c = -3;
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parameter longint d = -4;
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parameter byte e = -5;
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output wire [1023:0] out;
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assign out = {a, b, c, d, e};
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endmodule
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module gold(out);
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integer a = -1;
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int b = -2;
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shortint c = -3;
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longint d = -4;
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byte e = -5;
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output wire [1023:0] out;
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assign out = {a, b, c, d, e};
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endmodule
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@ -0,0 +1,5 @@
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read_verilog -sv param_int_types.sv
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proc
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equiv_make gold gate equiv
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equiv_simple
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equiv_status -assert
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