Eddie Hung
7977574995
New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC
2020-01-21 15:19:41 -08:00
Eddie Hung
cd8f55a911
write_xaiger: fix for (* keep *) on flop output
2020-01-21 09:43:04 -08:00
David Shah
22c967e35e
ast: Add support for $sformatf system function
...
Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 21:20:17 +00:00
Eddie Hung
6a163b5ddd
xilinx_dsp: another typo; move xilinx specific test
2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7
ice40_dsp: fix typo
2020-01-17 16:08:04 -08:00
Eddie Hung
5507c328ff
Add #1644 testcase
2020-01-17 15:57:52 -08:00
Eddie Hung
ad6c49fff1
ice40_dsp: add test
2020-01-17 15:38:26 -08:00
Jeff Wang
8ef5c7d48c
scoped enum tests
2020-01-16 18:13:30 -05:00
Jeff Wang
caf35896da
enum in package test
2020-01-16 18:09:03 -05:00
Jeff Wang
febe7706a2
simple enum test
2020-01-16 18:09:03 -05:00
Eddie Hung
2245afa142
More rigorous test
2020-01-16 09:15:42 -08:00
Eddie Hung
03ce2c72bb
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-15 16:42:16 -08:00
Eddie Hung
5918ede9bd
abc9: aAdd test to check $_NOT_s are absorbed
2020-01-15 14:36:05 -08:00
Eddie Hung
e30b6bbbf8
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-01-15 09:51:31 -08:00
Eddie Hung
53a99ade9c
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-14 11:46:56 -08:00
Eddie Hung
61ffd2d199
Merge pull request #1633 from YosysHQ/eddie/fix_autoname
...
autoname: do not rename ports
2020-01-14 11:40:54 -08:00
Eddie Hung
9fa0e03cc9
Merge pull request #1632 from YosysHQ/eddie/fix1630
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read_aiger: uniquify wires with $aiger<autoidx> prefix
2020-01-14 11:40:40 -08:00
Miodrag Milanović
9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr
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Export wire properties in EDIF
2020-01-14 19:19:32 +01:00
Eddie Hung
00964e999d
autoname: add testcase with $-prefix-ed port
2020-01-14 10:13:03 -08:00
Eddie Hung
565d349dc9
Add #1630 testcase
2020-01-13 21:27:53 -08:00
Eddie Hung
a6d4ea7463
abc9: respect (* keep *) on cells
2020-01-13 19:21:11 -08:00
Eddie Hung
9ec948f396
write_xaiger: add support and test for (* keep *) on wires
2020-01-13 19:07:55 -08:00
Eddie Hung
ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad
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abc9: add some scripts/options into "scratchpad"
2020-01-13 09:04:20 -08:00
Eddie Hung
ae619ba87a
Add #1626 testcase
2020-01-12 15:21:26 -08:00
Eddie Hung
c063436eea
Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad
2020-01-11 17:02:20 -08:00
Miodrag Milanovic
ccfe1e5909
this one is fine
2020-01-10 15:20:50 +01:00
Miodrag Milanovic
af852a0ea8
Fix tests
2020-01-10 14:48:01 +01:00
Eddie Hung
a10016ccc5
Add abc9 sanity test
2020-01-09 18:17:06 -08:00
Eddie Hung
94ab3791ce
Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs
2020-01-07 15:44:18 -08:00
Eddie Hung
0d3f10d3cc
Add testcases
2020-01-07 11:44:20 -08:00
Eddie Hung
7c878bf397
tests/aiger: write Yosys output
2020-01-07 11:44:03 -08:00
Eddie Hung
3df869cc7c
Add testcase from #1459
2020-01-06 16:22:22 -08:00
Eddie Hung
6e866030c2
Combine tests to check multiple clock domains
2020-01-02 14:38:59 -08:00
Eddie Hung
b454735bea
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-02 12:44:06 -08:00
Eddie Hung
9e5ff30d05
Merge pull request #1606 from YosysHQ/eddie/improve_tests
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Fix a few issues in tests/arch/*
2020-01-01 13:31:46 -08:00
Eddie Hung
52fe1e0c44
Revert insertion of 'reg', leave note behind
2020-01-01 09:05:46 -08:00
Miodrag Milanovic
a1344ec06e
Added a test case
2020-01-01 16:24:30 +01:00
Eddie Hung
713484fa66
Do not do call equiv_opt when no sim model exists
2019-12-31 18:40:30 -08:00
Eddie Hung
a59016b146
Fix warnings
2019-12-31 18:40:11 -08:00
Eddie Hung
c082329af3
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
Eddie Hung
ccc0a740d2
Add some abc9 dff tests
2019-12-31 16:16:05 -08:00
Eddie Hung
0c4be94a02
Add -D DFF_MODE to abc9_map test
2019-12-30 20:13:25 -08:00
Eddie Hung
fc4b8b8991
Remove submod changes
2019-12-30 14:56:14 -08:00
Eddie Hung
405e974fe5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
Miodrag Milanović
c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default
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Make iopad option default for all xilinx flows
2019-12-30 20:34:31 +01:00
Eddie Hung
c2c74f9bb0
Merge pull request #1599 from YosysHQ/eddie/retry_1588
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Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
2019-12-30 10:01:02 -08:00
Miodrag Milanovic
f9749c202c
Fix new tests
2019-12-28 16:43:19 +01:00
Miodrag Milanovic
8c3de1d4bd
Merge remote-tracking branch 'origin/master' into iopad_default
2019-12-28 16:23:31 +01:00
Miodrag Milanovic
a82c701668
Make test without iopads
2019-12-28 16:22:24 +01:00
Miodrag Milanovic
509da7ed1a
Revert "Fix xilinx tests, when iopads are default"
...
This reverts commit 477e43d921
.
2019-12-28 16:12:45 +01:00
Eddie Hung
011f749ecf
Update resource count
2019-12-28 02:15:11 -08:00
Eddie Hung
d45869855c
Add #1598 testcase
2019-12-27 16:44:57 -08:00
Marcin Kościelnicki
a24596def3
iopadmap: Emit tristate buffers with const OE for some edge cases.
2019-12-25 17:37:58 +01:00
Eddie Hung
2e21aa59a2
Add DSP cascade tests
2019-12-23 14:58:06 -08:00
Marcin Kościelnicki
666c6128a9
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
Miodrag Milanovic
436fea9e69
Addressed review comments
2019-12-21 20:23:23 +01:00
Miodrag Milanovic
477e43d921
Fix xilinx tests, when iopads are default
2019-12-21 13:18:44 +01:00
Eddie Hung
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Eddie Hung
d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531
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verilog: preserve size of $genval$-s in for loops
2019-12-19 12:21:33 -05:00
Eddie Hung
d675f22f4e
Merge pull request #1571 from YosysHQ/eddie/fix_1570
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mem_arst.v: do not redeclare ANSI port
2019-12-19 12:21:22 -05:00
Eddie Hung
b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass
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add a command to read/modify scratchpad contents
2019-12-18 13:55:44 -05:00
Marcin Kościelnicki
f382164d6e
tests/xilinx: fix flaky mux test
2019-12-18 15:53:29 +01:00
Marcin Kościelnicki
a235250403
xilinx: Add xilinx_dffopt pass ( #1557 )
2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
aff6ad1ce0
xilinx: Improve flip-flop handling.
...
This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
2019-12-18 13:43:43 +01:00
Eddie Hung
a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
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xilinx: add LUTRAM rules for RAM32M, RAM64M
2019-12-16 21:48:21 -08:00
Eddie Hung
aed67dd020
abc9 needs a clean afterwards
2019-12-16 18:42:23 -08:00
Eddie Hung
378d9e6e0c
Add another test
2019-12-16 13:57:55 -08:00
Eddie Hung
db0003410f
Accidentally commented out tests
2019-12-16 13:31:47 -08:00
Eddie Hung
5a00d5578c
Add unconditional match blocks for force RAM
2019-12-16 13:31:15 -08:00
Eddie Hung
e990c013c5
Merge blockram tests
2019-12-16 13:01:51 -08:00
Diego H
87e21b0122
Fixing compiler warning/issues. Moving test script to the correct place
2019-12-16 10:23:45 -06:00
N. Engelhardt
abcd82daca
add assert option to scratchpad command
2019-12-16 14:00:21 +01:00
Diego H
f3f59910eb
Removing fixed attribute value to !ramstyle rules
2019-12-15 23:51:58 -06:00
Diego H
b35559fc33
Merging attribute rules into a single match block; Adding tests
2019-12-15 23:33:09 -06:00
Eddie Hung
a5764a1236
Disable RAM16X1D test
2019-12-13 10:28:13 -08:00
Eddie Hung
d86d073ad6
Add testcase
2019-12-13 10:26:30 -08:00
Diego H
1c96345587
Renaming BRAM memory tests for the sake of uniformity
2019-12-13 09:33:18 -06:00
Eddie Hung
d0ee4cd88f
Remove extraneous synth_xilinx call
2019-12-12 19:00:26 -08:00
Eddie Hung
01116f0f0a
Add tests for these new models
2019-12-12 18:52:48 -08:00
Eddie Hung
037d1a03df
Add #1460 testcase
2019-12-12 17:49:55 -08:00
Eddie Hung
caab66111e
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
Diego H
751a18d7e9
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
2019-12-12 17:32:58 -06:00
Eddie Hung
bea15b537b
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-12 14:57:17 -08:00
Eddie Hung
47ac1b01e6
Add test
2019-12-12 14:43:13 -08:00
Diego H
e33f407655
Adding a note (TODO) in the memory_params.ys check file
2019-12-12 16:06:46 -06:00
N. Engelhardt
1187e91c2f
add test and make help message more verbose
2019-12-12 20:51:59 +01:00
Diego H
937ec1ee78
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
2019-12-12 13:50:36 -06:00
Eddie Hung
23fcfd0adb
Make SV2017 compliant courtesy of @wsnyder
2019-12-12 07:34:07 -08:00
Eddie Hung
4a80510877
Even more obvious testcase
2019-12-11 23:52:05 -08:00
Eddie Hung
61a1f3f49b
Make testcase clearer with \o having its own init
2019-12-11 23:48:09 -08:00
Eddie Hung
151f7533e8
Add testcase
2019-12-11 16:52:37 -08:00
Eddie Hung
e75ca29b19
Add test: 'Warning: ignoring initial value on non-register: \o'
2019-12-11 11:26:54 -08:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
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Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
2019-12-09 17:38:48 -08:00
Eddie Hung
eff858cd33
unmap $__ICE40_CARRY_WRAPPER in test
2019-12-09 14:20:35 -08:00
Eddie Hung
705e520a52
Add a quick testcase for unknown modules as inout
2019-12-09 13:14:46 -08:00
Eddie Hung
e05372778a
ice40_wrapcarry to really preserve attributes via -unwrap option
2019-12-09 11:48:28 -08:00
Miodrag Milanovic
49c9b63e0f
Fix for non-deterministic test
2019-12-07 11:09:25 +01:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
946d5854c0
Drop keep=0 attributes on SB_CARRY
2019-12-06 17:27:47 -08:00
Jan Kowalewski
dcb30b5f4a
tests: arch: xilinx: Change order of arguments in macc.sh
2019-12-06 09:15:49 +01:00
Eddie Hung
d8fbf88980
Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER
2019-12-05 07:01:02 -08:00
Eddie Hung
19bc429482
abc9_map.v to transform INIT=1 to INIT=0
2019-12-04 21:36:41 -08:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. ( #1527 )
...
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
2019-12-04 08:44:08 +01:00
Eddie Hung
67f1ce2d43
Check SB_CARRY name also preserved
2019-12-03 14:51:39 -08:00
Eddie Hung
8de17877d4
Add testcase
2019-12-03 14:48:00 -08:00
Clifford Wolf
2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit
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Gowin: add and test DFF init values
2019-12-03 08:43:18 -08:00
Pepijn de Vos
a7d34a7cb5
update test
2019-12-03 16:56:15 +01:00
Pepijn de Vos
a3b25b4af8
Use -match-init to not synth contradicting init values
2019-12-03 15:12:25 +01:00
David Shah
e9ce4e658b
abc9: Fix breaking of SCCs
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Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 20:44:56 +00:00
Eddie Hung
c61186dd9d
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 13:24:03 -08:00
Eddie Hung
ff1e357682
Add multiple driver testcase
2019-11-27 13:22:26 -08:00
Eddie Hung
4bac6b13be
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 10:17:10 -08:00
Eddie Hung
6464dc35ec
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
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xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
2019-11-27 08:00:22 -08:00
Clifford Wolf
f43c0bd8ba
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
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opt_share: Fix handling of fine cells.
2019-11-27 11:23:16 +01:00
Eddie Hung
f6c0ec1d09
Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
2019-11-27 01:03:33 -08:00
Eddie Hung
6338615aa1
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 01:02:16 -08:00
Eddie Hung
8c813632b6
Revert "submod to bitty rather bussy, for bussy wires used as input and output"
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This reverts commit cba3073026
.
2019-11-27 00:48:22 -08:00
Eddie Hung
6318e3ce6d
Fix wire width
2019-11-26 23:38:49 -08:00
Eddie Hung
de3476cc23
No need for -abc9
2019-11-26 23:08:14 -08:00
Marcin Kościelnicki
fdcbda195b
opt_share: Fix handling of fine cells.
...
Fixes #1525 .
2019-11-27 08:01:07 +01:00
Eddie Hung
4a0198128e
Add citation
2019-11-26 22:51:16 -08:00
Eddie Hung
15042eaf57
Remove notes
2019-11-26 22:41:35 -08:00
Eddie Hung
222e199b73
Add testcase derived from fastfir_dynamictaps benchmark
2019-11-26 21:26:30 -08:00
Eddie Hung
dd317c9280
Add testcase where \init is copied
2019-11-25 16:07:35 -08:00
Eddie Hung
d087024caf
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 12:42:09 -08:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Marcin Kościelnicki
7562e7304e
xilinx: Use INV instead of LUT1 when applicable
2019-11-25 20:40:39 +01:00
Pepijn de Vos
72d03dc910
attempt to fix formatting
2019-11-25 14:50:34 +01:00
Pepijn de Vos
6c79abbf5a
gowin: add and test dff init values
2019-11-25 14:33:21 +01:00
Eddie Hung
b46e636c91
Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff
2019-11-23 08:38:48 -08:00
Eddie Hung
d223e11a72
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 22:28:35 -08:00
Eddie Hung
5cd3d3db0a
Remove redundant flatten
2019-11-22 22:28:10 -08:00
Eddie Hung
08f85e6438
Stray dump
2019-11-22 20:53:48 -08:00
Eddie Hung
2c5dfd802d
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 17:24:45 -08:00
Eddie Hung
4fdcf8f7d7
Add another test with constant driver
2019-11-22 17:23:34 -08:00
Eddie Hung
74ea438136
Add testcase for signal used as part input part output
2019-11-22 16:52:55 -08:00
Eddie Hung
0806b8e398
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 16:50:56 -08:00
Eddie Hung
8779faf789
Cleanup spacing
2019-11-22 16:50:09 -08:00
Eddie Hung
2ef2e2c040
Add testcase
2019-11-22 16:48:11 -08:00
Eddie Hung
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
Eddie Hung
c761fa49b7
Missing endmodule
2019-11-22 12:37:57 -08:00
Clifford Wolf
72d2ef6fd0
Merge pull request #1511 from YosysHQ/dave/always
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sv: Error checking for always_comb, always_latch and always_ff
2019-11-22 15:32:29 +01:00
Marcin Kościelnicki
e110df9c48
gowin: Remove show command from tests.
2019-11-22 14:49:35 +01:00
Eddie Hung
6841e3b1c2
Another sloppy mistake!
2019-11-21 16:33:20 -08:00
Eddie Hung
fe36275234
Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff
2019-11-21 16:32:52 -08:00
Eddie Hung
39fdcb892b
async2sync -> clk2fflogic
2019-11-21 16:27:34 -08:00
Eddie Hung
5a30e3ac3b
Merge branch 'eddie/xaig_dff_adff' into xaig_dff
2019-11-21 16:15:25 -08:00
Eddie Hung
911a152b39
Add test
2019-11-21 16:13:28 -08:00
David Shah
49b670ca38
sv: Add tests for SV always types
...
Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 21:06:28 +00:00
Eddie Hung
cd9e830b67
Add multi clock test
2019-11-20 13:28:55 -08:00
Eddie Hung
1cc106452f
Add a equiv test too
2019-11-19 17:05:14 -08:00
Eddie Hung
90c5ca330c
Add two tests
2019-11-19 16:57:58 -08:00
Clifford Wolf
7ea0a5937b
Merge pull request #1449 from pepijndevos/gowin
...
Improvements for gowin support
2019-11-19 17:29:27 +01:00
Marcin Kościelnicki
15232a48af
Fix #1462 , #1480 .
2019-11-19 08:57:39 +01:00
Marcin Kościelnicki
38e72d6e13
Fix #1496 .
2019-11-18 04:16:48 +01:00
Pepijn de Vos
32f0296df1
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
2019-11-16 12:43:17 +01:00
Pepijn de Vos
ab8c521030
fix fsm test with proper clock enable polarity
2019-11-11 17:51:26 +01:00
Miodrag Milanovic
3e0ffe05a7
Fixed tests
2019-11-11 15:41:33 +01:00
Pepijn de Vos
0e5dbc4abc
fix wide luts
2019-11-06 19:48:18 +01:00
Pepijn de Vos
df8390f5df
don't cound exact luts in big muxes; futile and fragile
2019-10-30 14:58:25 +01:00
Pepijn de Vos
903f997391
add tristate buffer and test
2019-10-28 15:18:01 +01:00
Pepijn de Vos
9517525224
do not use wide luts in testcase
2019-10-28 14:40:12 +01:00
Pepijn de Vos
8226f2db0b
ALU sim tweaks
2019-10-24 13:39:43 +02:00
Pepijn de Vos
83fbfe0964
Add some tests
...
Copied from Efinix.
* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
2019-10-21 16:25:15 +02:00
Miodrag Milanovic
190b40341a
fixed error
2019-10-18 13:15:36 +02:00
Miodrag Milanovic
9bd9db56c8
Unify verilog style
2019-10-18 12:50:24 +02:00
Miodrag Milanovic
12383f37b2
Common memory test now shared
2019-10-18 12:33:35 +02:00
Miodrag Milanovic
477702b8c9
Remove not needed tests
2019-10-18 12:20:35 +02:00
Miodrag Milanovic
5603595e5c
Share common tests
2019-10-18 12:19:59 +02:00
Miodrag Milanovic
ab98f2dccf
fix yosys path
2019-10-18 11:18:53 +02:00
Miodrag Milanovic
56f9482675
Fix path to yosys
2019-10-18 11:12:03 +02:00
Miodrag Milanovic
c2ec7ca703
Moved all tests in arch sub directory
2019-10-18 11:06:12 +02:00
Miodrag Milanovic
3c41599ee1
Add async2sync
2019-10-18 11:00:27 +02:00
Miodrag Milanović
b4d7650548
Merge branch 'master' into mmicko/efinix
2019-10-18 10:54:28 +02:00
Miodrag Milanović
66fca65b58
Merge branch 'master' into mmicko/anlogic
2019-10-18 10:53:56 +02:00
Miodrag Milanović
0b0b0cc0d9
Merge branch 'master' into eddie/pr1352
2019-10-18 10:52:50 +02:00
Miodrag Milanovic
b659082e4a
hierarchy - proc reorder
2019-10-18 09:13:06 +02:00
Miodrag Milanovic
46af9a0ff7
hierarchy - proc reorder
2019-10-18 09:06:43 +02:00
Miodrag Milanovic
0d60902fd9
hierarchy - proc reorder
2019-10-18 09:04:02 +02:00
Miodrag Milanovic
e6ad714d20
hierarchy - proc reorder
2019-10-18 08:06:57 +02:00
Miodrag Milanovic
980df499ab
Make equivalence work with latest master
2019-10-17 17:24:53 +02:00
Miodrag Milanovic
b2f0d75807
remove not needed top module
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
1a399c6456
remove not needed top module
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
a198bcdd4f
split muxes synth per type
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
36af102801
Test dffs separetely
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
487b38b124
Split latches into separete tests
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
fba6229718
Fix formatting
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
53bc499a90
Clean verilog code from not used define block
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
d37cd267a5
Removed alu and div_mod test as agreed, ignore generated files
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
a7fbc8c3fe
Test per flip-flop type
2019-10-17 17:10:42 +02:00
Eddie Hung
3b44084320
Add -assert
2019-10-17 17:10:42 +02:00
Eddie Hung
8422ad3e3a
Use built-in async2sync call as per #1417
2019-10-17 17:10:42 +02:00
Eddie Hung
5b7bc3ab85
Update mul test to DSP48E1
2019-10-17 17:10:02 +02:00
Eddie Hung
08bd1816e3
Update area for div_mod
2019-10-17 17:10:02 +02:00
Eddie Hung
a12801843b
Add comment for lack of tristate logic pointing to #1225
2019-10-17 17:10:02 +02:00
Eddie Hung
eded90b6b4
Move $x to end as 7f0eec8
2019-10-17 17:10:02 +02:00
SergeyDegtyar
305672170b
adffs test update (equiv_opt -multiclock)
2019-10-17 17:10:02 +02:00
Sergey
bb70eb977d
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
68f9239c57
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
df6d0b95da
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
c340d54657
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
205f52ffe5
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
df7fe40529
Fix div_mod test
2019-10-17 17:10:02 +02:00
SergeyDegtyar
7bc8f0c2e2
Add comment with expected behavior for latches,tribuf tests;Update adffs test
2019-10-17 17:10:02 +02:00
SergeyDegtyar
489444bcba
Fix latches.ys test
2019-10-17 17:10:02 +02:00
SergeyDegtyar
6331fa5b02
Remove xilinx_ug901 tests (will be moved to yosys-tests)
2019-10-17 17:10:02 +02:00
SergeyDegtyar
757c476f62
Add smoke tests to tests/xilinx
2019-10-17 17:10:02 +02:00
SergeyDegtyar
ca7a58bcc8
Add comments for unproven cells.
2019-10-17 17:08:38 +02:00
SergeyDegtyar
2ae7dec530
Add tests for Xilinx UG901 examples
2019-10-17 17:08:38 +02:00
Clifford Wolf
e84cedfae4
Use "(id)" instead of "id" for types as temporary hack
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-14 05:24:31 +02:00
Eddie Hung
3fb604c75d
Revert "Add test that is expecting to fail"
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This reverts commit c28d4b8047
.
2019-10-08 12:41:26 -07:00
Eddie Hung
cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427
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Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-08 12:38:29 -07:00
Eddie Hung
4c89a4e642
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync
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async2sync to be called by equiv_opt only when -async2sync given
2019-10-08 10:53:44 -07:00
Eddie Hung
5c68da4150
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-05 09:27:12 -07:00
Miodrag Milanovic
c0fa6f3e1a
Split mux tests per type
2019-10-04 13:05:16 +02:00
Miodrag Milanovic
1b80489486
Split latch check
2019-10-04 13:00:09 +02:00
Miodrag Milanovic
2c3e140246
split rest od ff's
2019-10-04 12:51:45 +02:00
Miodrag Milanovic
3de7889d08
Separate check for ff's types
2019-10-04 12:48:27 +02:00
Miodrag Milanovic
286a272872
Cleaned tests
2019-10-04 12:42:06 +02:00
Miodrag Milanovic
f94dc2c072
Remove not needed tests
2019-10-04 12:41:41 +02:00
Miodrag Milanovic
ef417fb1b3
Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys into mmicko/efinix
2019-10-04 12:20:49 +02:00
Miodrag Milanovic
03a3deec43
Cleanup and formating
2019-10-04 11:09:59 +02:00
Miodrag Milanovic
a5844e3ceb
split latches into separate checks
2019-10-04 11:08:42 +02:00
Miodrag Milanovic
3238ee7d35
check muxes per type
2019-10-04 11:04:18 +02:00
Miodrag Milanovic
91ad3ab717
check ff's separately
2019-10-04 11:00:49 +02:00
Miodrag Milanovic
3d3479b0af
Cleanup top modules and not used defines
2019-10-04 10:57:47 +02:00
Miodrag Milanovic
1435b9bf97
remove alu test
2019-10-04 10:55:13 +02:00
Miodrag Milanovic
b932654964
Merge branch 'SergeyDegtyar/anlogic' of https://github.com/SergeyDegtyar/yosys into mmicko/anlogic
2019-10-04 10:52:16 +02:00
Miodrag Milanovic
7785f23719
Check latches type one by one
2019-10-04 10:31:51 +02:00
Miodrag Milanovic
3358b2f185
Removed top module where not needed
2019-10-04 09:53:54 +02:00
Miodrag Milanovic
3c40c81030
Test muxes synth one by one
2019-10-04 08:52:54 +02:00
Miodrag Milanovic
d6ef9b1a6b
Cleaned verilog code from not used defines
2019-10-04 08:45:58 +02:00
Miodrag Milanovic
abb5a3a44d
Check for MULT18X18D, since that is working now
2019-10-04 08:44:10 +02:00
Miodrag Milanovic
9e8175fc75
Check flops one by one
2019-10-04 08:42:29 +02:00
Miodrag Milanovic
d19f765a58
Removed alu and div_mod tests as agreed
2019-10-04 08:41:53 +02:00
Eddie Hung
045f344038
Use `sat -tempinduct` and comments for why equiv_opt not sufficient
2019-10-03 11:11:50 -07:00
Eddie Hung
bd5889640b
Disable equiv check for ice40 latches
2019-10-03 10:45:53 -07:00
Eddie Hung
5d680590d6
Use equiv_opt -async2sync for xilinx
2019-10-03 10:30:33 -07:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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Add -select option to aigmap
2019-10-03 11:54:04 +02:00
David Shah
9b9d24f15b
sv: Improve tests
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:45 +01:00
David Shah
abc155715d
sv: Add test scripts for typedefs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
af25585170
sv: Add support for memories of a typedef
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
30d2326030
sv: Add support for memory typedefs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
e70e4afb60
sv: Fix typedefs in packages
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
c962951612
sv: Fix typedef parameters
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
f6b5e47e40
sv: Switch parser to glr, prep for typedef
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
Eddie Hung
e9645c7fa7
Fix broken CI, check reset even for constants, trim rstmux
2019-10-02 21:26:26 -07:00
Eddie Hung
e4bd5aaebf
Fix test
2019-10-02 18:12:25 -07:00
Eddie Hung
c6a55d948a
Merge branch 'eddie/fix_sat_init' into eddie/fix1427
2019-10-02 18:07:38 -07:00
Eddie Hung
f6fabc8fda
Update test
2019-10-02 18:03:45 -07:00
Eddie Hung
e730a595ee
Add test
2019-10-02 18:01:41 -07:00
Eddie Hung
c28d4b8047
Add test that is expecting to fail
2019-10-02 14:52:40 -07:00
Eddie Hung
a4f2f7d23c
Extend test with renaming cells with prefix too
2019-10-02 12:43:18 -07:00
Sergey
eb750670e3
run-test.sh Move $x at end of line.
2019-10-01 11:14:12 +03:00
Sergey
e092c4ae6b
Merge branch 'master' into SergeyDegtyar/efinix
2019-10-01 11:04:32 +03:00
Sergey
d99b1e3261
Merge branch 'master' into SergeyDegtyar/anlogic
2019-10-01 10:57:09 +03:00
Sergey
fc56459746
run-test.sh Move $x at end of line.
2019-10-01 10:55:34 +03:00
Eddie Hung
1caaf51492
equiv_opt with -assert
2019-09-30 19:54:59 -07:00
Eddie Hung
f8d5e11aa7
Update resource count for alu.ys
2019-09-30 19:54:04 -07:00
Eddie Hung
369652d4b9
Add test
2019-09-30 17:20:39 -07:00
Eddie Hung
8b239ee707
Add quick test
2019-09-30 15:34:04 -07:00
Eddie Hung
d992858318
Move $x to end as per 7f0eec8
2019-09-30 15:15:14 -07:00
Eddie Hung
eeb86247c5
Update fsm.ys resource count
2019-09-30 15:14:41 -07:00
Eddie Hung
0bbd1b6364
Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys into eddie/pr1352
2019-09-30 14:57:55 -07:00
whitequark
5c5881695d
Merge pull request #1406 from whitequark/connect_rpc
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rpc: new frontend
2019-09-30 17:38:20 +00:00
whitequark
99a7f39084
rpc: new frontend.
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A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.
Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
2019-09-30 15:53:11 +00:00
Eddie Hung
6216e45eda
Add latch test modified from #1363
2019-09-30 12:52:43 +02:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Marcin Kościelnicki
fd0e3a2c43
Fix _TECHMAP_REMOVEINIT_ handling.
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Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396 .
2019-09-27 18:34:12 +02:00
Miodrag Milanovic
7f0eec8270
Change order of parameters, to work on other os
2019-09-27 11:31:55 +02:00
Eddie Hung
a009314597
Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40
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ICE40 tests. adffs test update (equiv_opt -multiclock).
2019-09-25 16:43:24 -07:00
SergeyDegtyar
b66364ada2
Change sync controls to async.
2019-09-25 14:43:26 +03:00
SergeyDegtyar
fc6ebf8268
adffs test update (equiv_opt -multiclock).
2019-09-24 14:55:32 +03:00
Eddie Hung
bcee87a457
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-23 10:58:28 -07:00
SergeyDegtyar
1070f2e90b
Add new tests for Efinix architecture.
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Problems/questions:
- fsm.ys. equiv_opt -assert failed because of unproven cells;
- latches.ys,tribuf.ys - internal cells present;
- memory.ys - sat called with -verify and proof did fail.
2019-09-23 15:51:41 +03:00
SergeyDegtyar
27377c4663
Add new tests for Anlogic architecture
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Problems/questions:
- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
- Internal cell type $_TBUF_ is present.
2019-09-23 12:12:02 +03:00
Eddie Hung
7c8de1dd18
Hell let's add the original #1381 testcase too
2019-09-20 17:58:51 -07:00
Eddie Hung
6258e6a7e2
Add testcase
2019-09-20 17:51:45 -07:00
Eddie Hung
4100825b81
Add more complicated macc testcase
2019-09-19 22:39:15 -07:00
Eddie Hung
2f98f9deee
Add mac.sh and macc_tb.v for testing
2019-09-19 18:08:16 -07:00
Eddie Hung
b88f0f6450
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
2019-09-19 15:47:41 -07:00
Eddie Hung
65fa8adf6c
Format macc.v
2019-09-19 11:02:14 -07:00
Marcin Kościelnicki
c9f9518de4
Added extractinv pass
2019-09-19 04:02:48 +02:00
Eddie Hung
c663a3680b
Remove stat
2019-09-18 12:44:34 -07:00
Eddie Hung
f7dbfef792
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 12:40:21 -07:00
Eddie Hung
b66c99ece0
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
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peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
2019-09-18 12:40:08 -07:00
Eddie Hung
c9fe4d7992
Add .gitignore
2019-09-18 12:11:33 -07:00
Eddie Hung
c3cba7ab93
Refine macc testcase
2019-09-18 12:07:25 -07:00
SergeyDegtyar
5eb91fa69f
Add comment to dpram test about related issue.
2019-09-18 12:16:04 +03:00
SergeyDegtyar
c597c2f2ae
adffs test update (equiv_opt -multiclock). div_mod test fix
2019-09-17 12:19:31 +03:00
Eddie Hung
f492567c87
Oops
2019-09-13 18:19:07 -07:00
Eddie Hung
a2eee9ebef
Add counter-example from @cliffordwolf
2019-09-13 16:41:10 -07:00
Eddie Hung
14d72c39c3
Revert "Make one check $shift(x)? only; change testcase to be 8b"
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This reverts commit e2c2d784c8
.
2019-09-13 16:33:18 -07:00
Eddie Hung
a1123b095c
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-12 12:11:11 -07:00
David Shah
6044fff074
Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock
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Add equiv_opt -multiclock
2019-09-12 12:26:28 +01:00
Eddie Hung
7d644f40ed
Add AREG=2 BREG=2 test
2019-09-11 17:05:47 -07:00
Eddie Hung
c0f26c2da8
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 13:37:11 -07:00
Eddie Hung
bdb5e0f29c
Cope with presence of reset muxes too
2019-09-11 13:36:37 -07:00
Eddie Hung
f46ef47893
Add more tests
2019-09-11 13:22:41 -07:00