Eddie Hung
|
04bc287271
|
Refactor using subpattern in_dffe
|
2019-09-09 15:51:14 -07:00 |
Eddie Hung
|
e2c2d784c8
|
Make one check $shift(x)? only; change testcase to be 8b
|
2019-09-06 22:48:23 -07:00 |
Eddie Hung
|
74a5c802f7
|
Pack CREG
|
2019-09-06 21:01:36 -07:00 |
Eddie Hung
|
6a9205280f
|
Use unextend lambda
|
2019-09-06 18:40:11 -07:00 |
Eddie Hung
|
b69512a5b9
|
Fix ffP just like ffPmux
|
2019-09-06 15:51:21 -07:00 |
Eddie Hung
|
5344bfe637
|
Perform D replacement properly
|
2019-09-06 15:46:15 -07:00 |
Eddie Hung
|
74eac76699
|
Add support for DREG
|
2019-09-06 15:32:26 -07:00 |
Eddie Hung
|
ef56f8596f
|
Fine tune nusers when postAdd
|
2019-09-06 15:11:41 -07:00 |
Eddie Hung
|
0d1d8b4d24
|
Fix macc and mul tests
|
2019-09-06 14:57:36 -07:00 |
Eddie Hung
|
8246062acf
|
Fix enable polarity
|
2019-09-06 14:36:10 -07:00 |
Eddie Hung
|
2c32056990
|
Logging for ffAD
|
2019-09-06 14:10:12 -07:00 |
Eddie Hung
|
e926f2973e
|
Add support for pre-adder and AD register
|
2019-09-06 14:06:57 -07:00 |
Eddie Hung
|
da8fe83f7a
|
Tidy up ice40_dsp some more
|
2019-09-06 12:16:40 -07:00 |
Eddie Hung
|
776d769941
|
Use more index patterns
|
2019-09-06 12:07:35 -07:00 |
Eddie Hung
|
a945f6c7ef
|
Fix ffPmux to cope with offset
|
2019-09-06 11:58:56 -07:00 |
Eddie Hung
|
fbf1b74946
|
Simplify filter expressions
|
2019-09-06 11:39:20 -07:00 |
Eddie Hung
|
39a5d046ea
|
Fix nusers condition in ffP
|
2019-09-06 11:38:19 -07:00 |
Eddie Hung
|
cdc1e1f5c2
|
Check adder is <= 48 bits before packing
|
2019-09-06 10:35:06 -07:00 |
Eddie Hung
|
91f68c4de2
|
Check nusers for M and P enable muxes
|
2019-09-06 09:59:35 -07:00 |
Eddie Hung
|
4fe24b20f9
|
More nusers() checks for A and B enable muxes
|
2019-09-06 09:47:32 -07:00 |
Eddie Hung
|
dc10559f31
|
Cleanup
|
2019-09-05 21:39:52 -07:00 |
Eddie Hung
|
174edbcb96
|
Sensitive to CEB CEM CEP polarity
|
2019-09-05 21:38:35 -07:00 |
Eddie Hung
|
53ca536d67
|
ffAmuxAB -> ffAenpol
|
2019-09-05 21:28:28 -07:00 |
Eddie Hung
|
5a2fc6fcb5
|
Refactor ice40_dsp
|
2019-09-05 18:06:59 -07:00 |
Eddie Hung
|
888ae1d05e
|
Fix broken ice40_dsp
|
2019-09-05 17:58:19 -07:00 |
Eddie Hung
|
38e73a3788
|
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
|
2019-09-05 13:01:34 -07:00 |
Eddie Hung
|
a32b14a55f
|
Do not check signedness of post-adder (assume taken care of by DSP)
|
2019-09-05 12:38:47 -07:00 |
Eddie Hung
|
7bd55f379c
|
Use filter instead of index; support wide enable muxes
|
2019-09-05 11:55:14 -07:00 |
Eddie Hung
|
fe5a1324c9
|
Do not make ff[MP]mux semioptional, use sigmap
|
2019-09-05 11:46:38 -07:00 |
Eddie Hung
|
447a31e75d
|
Add support for CEP
|
2019-09-05 11:00:27 -07:00 |
Eddie Hung
|
05282afc25
|
Add support for CEB, remove check on nusers
|
2019-09-05 10:46:33 -07:00 |
Eddie Hung
|
0166e02e78
|
Cleanup
|
2019-09-05 10:07:56 -07:00 |
Eddie Hung
|
aa462da395
|
Support CEA
|
2019-09-05 10:07:26 -07:00 |
Eddie Hung
|
09c26c55bb
|
Get rid of sigBset too
|
2019-09-04 17:22:02 -07:00 |
Eddie Hung
|
91ef4457b0
|
Get rid of sigAset
|
2019-09-04 17:18:49 -07:00 |
Eddie Hung
|
42548d9790
|
Get rid of sigPused
|
2019-09-04 17:06:17 -07:00 |
Eddie Hung
|
93d798272d
|
Compute sigP properly
|
2019-09-04 16:59:57 -07:00 |
Eddie Hung
|
433b0c677c
|
Remove log_cell() calls
|
2019-09-04 13:42:44 -07:00 |
Eddie Hung
|
229e54568e
|
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
|
2019-09-04 12:37:48 -07:00 |
Eddie Hung
|
2b86055848
|
Add peepopt_dffmuxext
|
2019-09-04 12:35:15 -07:00 |
Eddie Hung
|
e67e4a5ed6
|
Support CEM
|
2019-09-04 10:52:51 -07:00 |
Eddie Hung
|
80aec0f006
|
st.ffP from if to assert
|
2019-09-03 16:37:59 -07:00 |
Eddie Hung
|
16316aa05d
|
Rename muxAB to postAddMux
|
2019-09-03 16:24:59 -07:00 |
Eddie Hung
|
cd002ad3fb
|
Use choices for addAB, now called postAdd
|
2019-09-03 16:10:16 -07:00 |
Eddie Hung
|
2d80866daf
|
Add support for load value into DSP48E1.P
|
2019-09-03 15:53:10 -07:00 |
Eddie Hung
|
682153de4b
|
Process post-adder first since C could be used for load-P
|
2019-09-03 14:57:59 -07:00 |
Eddie Hung
|
97d11708e0
|
Use feedback path for MACC
|
2019-09-03 14:37:32 -07:00 |
Eddie Hung
|
4aa505d1b2
|
Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc
ice40_dsp to allow signed multipliers
|
2019-09-01 10:11:33 -07:00 |
Eddie Hung
|
a09e69dd56
|
Fine tune xilinx_dsp pattern matcher
|
2019-08-30 16:18:58 -07:00 |
Eddie Hung
|
8f503fe3e6
|
autoremove ffM
|
2019-08-30 15:30:04 -07:00 |
Eddie Hung
|
e67f049e3b
|
Remove debug
|
2019-08-30 15:03:43 -07:00 |
Eddie Hung
|
15bab02a1b
|
ffM before addAB
|
2019-08-30 15:03:12 -07:00 |
Eddie Hung
|
c497114e94
|
Another oops
|
2019-08-30 15:02:53 -07:00 |
Eddie Hung
|
44a35015b3
|
Update commented out
|
2019-08-30 15:01:38 -07:00 |
Eddie Hung
|
390cf34d0a
|
Add support for ffM
|
2019-08-30 15:00:56 -07:00 |
Eddie Hung
|
2983a35dc0
|
Update comment
|
2019-08-30 15:00:40 -07:00 |
Eddie Hung
|
17b77fd411
|
Missing dep for test_pmgen
|
2019-08-30 14:01:07 -07:00 |
Eddie Hung
|
89359b6927
|
Missing dep for test_pmgen
|
2019-08-30 14:00:40 -07:00 |
Eddie Hung
|
723815b384
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-08-30 13:26:19 -07:00 |
Eddie Hung
|
c1459bc748
|
Do not restrict multiplier to unsigned
|
2019-08-30 12:22:14 -07:00 |
Eddie Hung
|
4e782f1509
|
New pmgen requires explicit accept
|
2019-08-30 11:02:10 -07:00 |
Eddie Hung
|
295c18bd6b
|
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
|
2019-08-30 09:50:20 -07:00 |
David Shah
|
6919c0f9b0
|
Merge branch 'master' into xc7dsp
|
2019-08-30 13:57:15 +01:00 |
Eddie Hung
|
4eb5847dbd
|
Cleanup
|
2019-08-28 18:10:33 -07:00 |
Eddie Hung
|
0af64df10c
|
Account for D port being a constant
|
2019-08-28 15:32:38 -07:00 |
Eddie Hung
|
52c4655de3
|
No need to replace Q of slice since $shiftx is autoremove-d
|
2019-08-28 11:06:11 -07:00 |
Eddie Hung
|
11e3eb1009
|
More cleanup
|
2019-08-28 10:19:35 -07:00 |
Eddie Hung
|
86b538bd02
|
More cleanup
|
2019-08-28 10:11:09 -07:00 |
Eddie Hung
|
c4d1bd988b
|
Do not use default_params dict, hardcode default values, cleanup
|
2019-08-28 10:06:40 -07:00 |
Eddie Hung
|
c3e9627afe
|
Always generate if no match
|
2019-08-28 09:54:56 -07:00 |
Eddie Hung
|
0ebe2c9831
|
Rename test_pmgen arg xilinx_srl.{fixed,variable}
|
2019-08-28 09:27:03 -07:00 |
Eddie Hung
|
9172d4a674
|
Missing close bracket
|
2019-08-26 21:02:52 -07:00 |
Eddie Hung
|
54422c5bb4
|
Remove leftover header
|
2019-08-26 17:51:13 -07:00 |
Eddie Hung
|
e95fb24574
|
Improve xilinx_srl.fixed generate, add .variable generate
|
2019-08-26 17:49:08 -07:00 |
Eddie Hung
|
45c34c87ee
|
Account for maxsubcnt overflowing
|
2019-08-26 17:48:54 -07:00 |
Eddie Hung
|
b32d6bf403
|
Add xilinx_srl_pm.variable to test_pmgen
|
2019-08-26 17:44:57 -07:00 |
Eddie Hung
|
e574edc3e9
|
Populate generate for xilinx_srl.fixed pattern
|
2019-08-26 14:21:17 -07:00 |
Eddie Hung
|
cf9e017127
|
Add xilinx_srl_fixed, fix typos
|
2019-08-26 14:20:06 -07:00 |
Eddie Hung
|
7911143827
|
Create new $__XILINX_SHREG_ cell for variable length too
|
2019-08-23 18:15:49 -07:00 |
Eddie Hung
|
a048fc93e8
|
Do not allow Q of last cell of variable length SRL to be (* keep *)
|
2019-08-23 18:15:24 -07:00 |
Eddie Hung
|
ee9f6e6243
|
Also add first.Q to chain_bits since variable length
|
2019-08-23 18:14:06 -07:00 |
Eddie Hung
|
70ce3d0670
|
Do not enforce !EN_POLARITY on $dffe
|
2019-08-23 18:11:28 -07:00 |
Eddie Hung
|
188b49378a
|
Create new cell for fixed length SRL
|
2019-08-23 17:25:30 -07:00 |
Eddie Hung
|
e081303ee8
|
Cleanup FDRE matching
|
2019-08-23 17:23:52 -07:00 |
Eddie Hung
|
54488cfb82
|
Oops don't need a finally block
|
2019-08-23 16:39:37 -07:00 |
Eddie Hung
|
83e2d87fb8
|
Keep track of bits in variable length chain, to check for taps
|
2019-08-23 16:21:10 -07:00 |
Eddie Hung
|
f2d4814284
|
Don't forget $dff has no EN
|
2019-08-23 16:14:57 -07:00 |
Eddie Hung
|
2217d926a9
|
Same for variable length
|
2019-08-23 16:13:16 -07:00 |
Eddie Hung
|
b1caf7be5e
|
Filter on en_port for fixed length
|
2019-08-23 16:09:46 -07:00 |
Eddie Hung
|
513af10d77
|
Check clock is consistent
|
2019-08-23 15:18:26 -07:00 |
Eddie Hung
|
c762618783
|
Fix last_cell.D
|
2019-08-23 15:08:49 -07:00 |
Eddie Hung
|
ca5de78e76
|
Revert "Add a unique argument to pmgen's nusers()"
This reverts commit 1d88887cfd .
|
2019-08-23 15:04:00 -07:00 |
Eddie Hung
|
e85e6e8d45
|
Revert "Fix polarity"
This reverts commit 9cd23cf0fe .
|
2019-08-23 15:03:42 -07:00 |
Eddie Hung
|
9cd23cf0fe
|
Fix polarity
|
2019-08-23 14:49:34 -07:00 |
Eddie Hung
|
c2757613b6
|
Check for non unique nusers/fanouts
|
2019-08-23 14:32:36 -07:00 |
Eddie Hung
|
1d88887cfd
|
Add a unique argument to pmgen's nusers()
|
2019-08-23 14:32:17 -07:00 |
Eddie Hung
|
8ecfd55d5a
|
Update doc
|
2019-08-23 14:16:41 -07:00 |
Eddie Hung
|
3d7f4aa0c8
|
Remove (* init *) entry when consumed into SRL
|
2019-08-23 13:56:01 -07:00 |
Eddie Hung
|
967a36c125
|
indo -> into
|
2019-08-23 13:16:50 -07:00 |
Eddie Hung
|
a1f78eab04
|
indo -> into
|
2019-08-23 13:15:41 -07:00 |
Eddie Hung
|
5939ffdc07
|
Forgot to slice
|
2019-08-23 13:06:59 -07:00 |
Eddie Hung
|
242b3083ea
|
Cope with possibility that D could connect to Q on same cell
|
2019-08-23 13:06:31 -07:00 |
Eddie Hung
|
18b64609c2
|
xilinx_srl to use 'slice' features of pmgen for word level
|
2019-08-23 12:22:06 -07:00 |
Eddie Hung
|
f4fd41d5d2
|
Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl
|
2019-08-23 11:35:06 -07:00 |
Clifford Wolf
|
55bf8f69e0
|
Fix port hanlding in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-23 16:26:54 +02:00 |
Clifford Wolf
|
adb81ba386
|
Add pmgen slices and choices
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-23 16:15:50 +02:00 |
Eddie Hung
|
6e8fda8bf0
|
Add doc
|
2019-08-22 11:52:24 -07:00 |
Eddie Hung
|
cabadb85e2
|
Add copyright
|
2019-08-22 11:25:19 -07:00 |
Eddie Hung
|
9f3ed1726e
|
pmgen to also iterate over all module ports
|
2019-08-22 11:15:16 -07:00 |
Eddie Hung
|
74bd190d3b
|
Remove output_bits
|
2019-08-22 11:14:59 -07:00 |
Eddie Hung
|
231ddbf95c
|
Forgot to set ud_variable.minlen
|
2019-08-22 11:02:17 -07:00 |
Eddie Hung
|
61639d5387
|
Do not run xilinx_srl_pm in fixed loop
|
2019-08-22 10:51:04 -07:00 |
Eddie Hung
|
d0b2973413
|
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
|
2019-08-22 10:32:06 -07:00 |
Eddie Hung
|
7d02d17b16
|
Reuse var
|
2019-08-21 19:18:40 -07:00 |
Eddie Hung
|
5c8344363f
|
Revert "Trim shiftx_width when upper bits are 1'bx"
This reverts commit 7e7965ca7b .
|
2019-08-21 19:18:27 -07:00 |
Eddie Hung
|
7e7965ca7b
|
Trim shiftx_width when upper bits are 1'bx
|
2019-08-21 18:43:17 -07:00 |
Eddie Hung
|
ed7be3e6b6
|
Add comment
|
2019-08-21 17:36:38 -07:00 |
Eddie Hung
|
15188033da
|
Add variable length support to xilinx_srl
|
2019-08-21 17:34:40 -07:00 |
Eddie Hung
|
6d76ae4c65
|
Rename pattern to fixed
|
2019-08-21 15:46:58 -07:00 |
Eddie Hung
|
b0a3b430bf
|
attribute -> attr
|
2019-08-21 15:44:07 -07:00 |
Eddie Hung
|
61b4d7ae13
|
Use Cell::has_keep_attribute()
|
2019-08-21 15:41:46 -07:00 |
Eddie Hung
|
6fa9e03e4c
|
xilinx_srl to support FDRE and FDRE_1
|
2019-08-21 15:35:29 -07:00 |
Eddie Hung
|
3c8e8521a6
|
Fix polarity of EN_POL
|
2019-08-21 14:42:11 -07:00 |
Eddie Hung
|
a980f0d4be
|
Add CLKPOL == 0
|
2019-08-21 14:35:40 -07:00 |
Eddie Hung
|
1c7d721558
|
Reject if not minlen from inside pattern matcher
|
2019-08-21 14:26:24 -07:00 |
Eddie Hung
|
cab2bd083e
|
Get wire via SigBit
|
2019-08-21 13:47:47 -07:00 |
Eddie Hung
|
52fea5b658
|
Respect \keep on cells or wires
|
2019-08-21 13:42:03 -07:00 |
Eddie Hung
|
5ce0c31d0e
|
Add init support
|
2019-08-21 13:05:10 -07:00 |
Eddie Hung
|
df53fe12e7
|
Fix spacing
|
2019-08-21 12:54:11 -07:00 |
Eddie Hung
|
0250712486
|
Initial progress on xilinx_srl
|
2019-08-21 12:50:49 -07:00 |
Miodrag Milanovic
|
948b6f91a1
|
Fix test_pmgen deps
|
2019-08-21 17:00:24 +02:00 |
Eddie Hung
|
4cc74346f1
|
Fix compile error
|
2019-08-20 20:27:05 -07:00 |
Eddie Hung
|
9b9d759451
|
Fix copy-paste typo
|
2019-08-20 20:18:51 -07:00 |
Eddie Hung
|
b7a48e3e0f
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-08-20 20:18:17 -07:00 |
Clifford Wolf
|
d0117d7d12
|
Merge branch 'master' into clifford/pmgen
|
2019-08-20 11:39:23 +02:00 |
Clifford Wolf
|
1e3dd0a2da
|
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
|
2019-08-19 13:04:06 +02:00 |
Miodrag Milanovic
|
dbe3cb9708
|
Ignore all generated headers for pmgen pass
|
2019-08-18 10:49:17 +02:00 |
Clifford Wolf
|
f3405fb048
|
Refactor pmgen rollback mechanism
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-17 13:54:18 +02:00 |
Clifford Wolf
|
318ae0351c
|
Improvements in "test_pmgen -generate"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-17 13:53:55 +02:00 |
Clifford Wolf
|
f95853c822
|
Add pmgen "fallthrough" statement
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-17 11:29:37 +02:00 |
Eddie Hung
|
cd5a372cd1
|
Add help() call
|
2019-08-16 13:00:12 -07:00 |
Clifford Wolf
|
64bd414e54
|
Minor bugfix in "test_pmgen -generate"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 14:35:13 +02:00 |
Clifford Wolf
|
20910fd7c8
|
Add pmgen finish statement, return number of matches
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 14:16:35 +02:00 |
Clifford Wolf
|
f45dad8220
|
Redesign pmgen backtracking for recursive matching
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 13:47:50 +02:00 |
Clifford Wolf
|
c710df181c
|
Add pmgen "generate" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 13:26:36 +02:00 |
Clifford Wolf
|
4a57b7e1ab
|
Refactor demo_reduce into test_pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 11:47:51 +02:00 |
Clifford Wolf
|
016036f247
|
Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-15 23:02:37 +02:00 |
Clifford Wolf
|
969ab9027a
|
Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-15 22:48:13 +02:00 |
Clifford Wolf
|
eb80d3d43f
|
Change pmgen default rule to reject, switch peepopt behavior to accept
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-15 22:47:59 +02:00 |
Eddie Hung
|
c320abc3f4
|
xilinx_dsp to be sensitive to keep attribute
|
2019-08-15 12:34:11 -07:00 |
Eddie Hung
|
96ee7b9cf7
|
Simplify
|
2019-08-15 12:30:46 -07:00 |
Eddie Hung
|
27d5df9467
|
ffH -> ffFJKG
|
2019-08-15 12:19:34 -07:00 |
Clifford Wolf
|
03f98d9176
|
Add demo_reduce pass to demonstrace recursive pattern matching
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-15 18:36:39 +02:00 |
Clifford Wolf
|
73bf453929
|
Improvements in pmgen for recursive patterns
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-15 18:35:56 +02:00 |
Eddie Hung
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aad97168b0
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Fixes for reverting SigSpec helper functions
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2019-08-14 10:22:33 -07:00 |
Eddie Hung
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2f04beeeb5
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Perform C -> PCIN optimisation after pattern matcher
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2019-08-13 17:11:35 -07:00 |
Eddie Hung
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1b0e68db94
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Revert changes to RTLIL::SigSpec methods
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2019-08-13 17:09:28 -07:00 |
Eddie Hung
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0597a3ea23
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Rename to XilinxDspPass
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2019-08-13 10:23:07 -07:00 |
Eddie Hung
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12c692f6ed
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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
This reverts commit c851dc1310 , reversing
changes made to f54bf1631f .
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2019-08-12 12:06:45 -07:00 |
David Shah
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f9020ce2b3
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Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
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2019-08-10 17:14:48 +01:00 |
Eddie Hung
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ab1d63a565
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Check nusers of DSP output, not whole flop
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2019-08-09 17:35:13 -07:00 |
Eddie Hung
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3dd3ab98c2
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Improve ice40_dsp for non-fully-32-bit adders
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2019-08-09 17:23:12 -07:00 |
Eddie Hung
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dfc878deb4
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Another filter -> if
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2019-08-09 16:23:32 -07:00 |
Eddie Hung
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e83f231927
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Cleanup
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2019-08-09 15:47:40 -07:00 |
Eddie Hung
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0b5b56c1ec
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Pack partial-product adder DSP48E1 packing
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2019-08-09 15:19:33 -07:00 |
Eddie Hung
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a002eba14a
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Fix check
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2019-08-09 14:27:08 -07:00 |
Eddie Hung
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82cbfada1b
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Revert "Fix typo"
This reverts commit e3c39cc450 .
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2019-08-09 14:14:28 -07:00 |
Eddie Hung
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747690a6df
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Remove muxY and ffY for now
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2019-08-08 16:33:37 -07:00 |
Eddie Hung
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2c0be7aa5d
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Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
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2019-08-08 12:56:05 -07:00 |
Eddie Hung
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07e50b9c25
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Only pack registers if {A,B,P}REG = 0, do not pack $dffe
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2019-08-08 10:51:19 -07:00 |
Eddie Hung
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911129e3ef
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Disable $dffe
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2019-08-08 10:44:49 -07:00 |
Eddie Hung
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675c1d4218
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Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER
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2019-08-07 16:29:38 -07:00 |
Eddie Hung
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fb568ddb4e
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Fix compile error
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2019-08-07 14:31:55 -07:00 |
Eddie Hung
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d90b8b081a
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Do not SigSpec::extract() beyond bounds
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2019-08-07 13:58:26 -07:00 |
Eddie Hung
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cdf9c80134
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Do not pack registers if (* keep *)
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2019-08-07 12:57:10 -07:00 |
Eddie Hung
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c39b1a6fcf
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Add comment about supporting $dffe in ice40_dsp
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2019-08-01 15:13:18 -07:00 |
Eddie Hung
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ed7540a46f
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Pack P register properly
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2019-08-01 15:10:43 -07:00 |
Eddie Hung
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e19d33b003
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Cope with sign extension in mul2dsp
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2019-08-01 12:44:56 -07:00 |
Eddie Hung
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c54a39069d
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CO is sign extension only if signed multiplier
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2019-08-01 10:00:49 -07:00 |
Eddie Hung
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e3c39cc450
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Fix typo
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2019-08-01 10:00:01 -07:00 |
Eddie Hung
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e4a638c292
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Restore old CO behaviour
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2019-07-31 15:45:15 -07:00 |
Eddie Hung
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4c25d1a76f
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Pop the CO bit from O
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2019-07-26 10:27:30 -07:00 |
Eddie Hung
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c1a05f4557
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Allow adders/accumulators with 33 bits using CO output
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2019-07-26 10:15:36 -07:00 |
Eddie Hung
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79fd6edc5a
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Eliminate warnings by sizing O correctly
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2019-07-23 15:13:30 -07:00 |
Eddie Hung
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a37574ccbf
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Fix muxAB logic
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2019-07-23 14:52:14 -07:00 |
Eddie Hung
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0dd2a125f6
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Remove debug print
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2019-07-23 14:21:45 -07:00 |
Eddie Hung
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dc0c853abe
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Simplify and fix for MACs
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2019-07-23 14:20:34 -07:00 |
Eddie Hung
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4f11ff8ebd
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Fix typo
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2019-07-23 13:58:56 -07:00 |
Eddie Hung
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33c984a044
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Fix spacing
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2019-07-22 16:37:13 -07:00 |
Eddie Hung
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068617f094
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Pack hi and lo registers separately
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2019-07-22 16:12:57 -07:00 |
Eddie Hung
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4d71ab384d
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Rename according to vendor doc TN1295
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2019-07-22 15:08:26 -07:00 |
Eddie Hung
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304cefbbe2
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Pack Y register
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2019-07-22 15:05:16 -07:00 |
Eddie Hung
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5a14b6e1f6
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Pack adders not just accumulators
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2019-07-22 13:01:49 -07:00 |
Eddie Hung
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e0720a8018
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Restore old ffY behaviour
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2019-07-19 22:47:08 -07:00 |
Eddie Hung
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f9d08a5e5e
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Cleanup
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2019-07-19 20:25:28 -07:00 |
Eddie Hung
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9ad11ea2cc
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Fine tune ice40_dsp.pmg, add support for packing subsets of registers
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2019-07-19 10:57:32 -07:00 |
Eddie Hung
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8f0e796be1
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Add support for ice40 signed multipliers
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2019-07-19 10:38:13 -07:00 |
Eddie Hung
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09411dd996
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ice40_dsp to accept $__MUL16X16 too
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2019-07-18 15:38:28 -07:00 |
Eddie Hung
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802470746c
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Check if RHS is empty first
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2019-07-18 15:22:00 -07:00 |
Eddie Hung
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90ac147eb2
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Do not autoremove ffP aor muxP
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2019-07-18 15:02:41 -07:00 |
Eddie Hung
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08fe63c61e
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Improve pattern matcher to match subsets of $dffe? cells
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2019-07-18 14:08:18 -07:00 |
Eddie Hung
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79d63479ea
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Improve A/B reg packing
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2019-07-18 13:30:35 -07:00 |
Eddie Hung
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e075f0dda0
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Do not autoremove A/B registers since they might have other consumers
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2019-07-18 13:22:22 -07:00 |
Eddie Hung
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0727b2c902
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Fix xilinx_dsp index cast
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2019-07-18 13:18:04 -07:00 |
Eddie Hung
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c76607b9bc
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Wrong wildcard symbol
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2019-07-18 08:14:58 -07:00 |
Eddie Hung
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91629ee4b3
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Pattern matcher to check pool of bits, not exactly
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2019-07-17 12:45:25 -07:00 |
Eddie Hung
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3f677fb0db
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Signed extension
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2019-07-16 15:54:07 -07:00 |
Eddie Hung
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9616dbd125
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Add support {A,B,P}REG packing
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2019-07-16 14:06:32 -07:00 |
Eddie Hung
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5f00d335d4
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Oops forgot these files
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2019-07-15 15:03:15 -07:00 |
Eddie Hung
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dd59375a66
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Add xilinx_dsp for register packing
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2019-07-15 14:46:31 -07:00 |
Clifford Wolf
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cb285e4b87
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Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-28 17:17:56 +02:00 |
Clifford Wolf
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b37c31e2cb
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Bugfix in peepopt_shiftmul.pmg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 15:34:19 +02:00 |
Clifford Wolf
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2b29aa5c86
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Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 08:35:45 +02:00 |
Clifford Wolf
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e8c5afcb84
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Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 08:25:30 +02:00 |
Clifford Wolf
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b515fd2d25
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Add peepopt_muldiv, fixes #930
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 11:25:15 +02:00 |
Clifford Wolf
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4306bebe58
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pmgen progress
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 10:51:51 +02:00 |
Clifford Wolf
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bb4f3642de
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Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 08:04:22 +02:00 |
Clifford Wolf
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58238da133
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Progress in shiftmul peepopt pattern
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 07:59:39 +02:00 |
Clifford Wolf
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ea547bcaa3
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Add "peepopt" skeleton
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 13:38:56 +02:00 |
Clifford Wolf
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9f792c599d
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Add pmgen support for multiple patterns in one matcher
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 13:02:05 +02:00 |
Clifford Wolf
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32881a989c
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Support multiple pmg files (right now just concatenated together)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 12:09:02 +02:00 |
Eddie Hung
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408161ea3a
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Misspelling
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2019-04-25 16:46:13 -07:00 |
Eddie Hung
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0deaccbaae
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Fix a few typos
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2019-04-08 16:46:33 -07:00 |
Eddie Hung
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d03780c3f4
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Fix spelling in pmgen/README.md
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2019-03-05 17:55:29 -08:00 |
Larry Doolittle
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57f8bb471f
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Try again for passes/pmgen/ice40_dsp_pm.h rule
Tested on both in-tree and out-of-tree builds
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2019-03-01 20:20:53 -08:00 |
Larry Doolittle
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e2fc18f27b
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Reduce amount of trailing whitespace in code base
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2019-02-28 14:58:11 -08:00 |
Clifford Wolf
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68a6937173
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Fix pmgen for in-tree builds
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-28 14:56:05 -08:00 |
Clifford Wolf
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64d91219b4
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Fix pmgen for out-of-tree build
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-28 14:00:58 -08:00 |
Clifford Wolf
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893194689d
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Fix typo in passes/pmgen/README.md
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-21 18:50:02 +01:00 |
Clifford Wolf
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2fe1c830eb
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Bugfix in ice40_dsp
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-21 13:28:46 +01:00 |
Clifford Wolf
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218e9051bb
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Add "synth_ice40 -dsp"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-20 16:42:27 +01:00 |
Clifford Wolf
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dca65d83a0
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Detect and reject cases that do not map well to iCE40 DSPs (yet)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-20 11:18:19 +01:00 |
Clifford Wolf
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5a853ed46c
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Add actual DSP inference to ice40_dsp pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-17 15:35:48 +01:00 |
Clifford Wolf
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8ddec5d882
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Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |
Clifford Wolf
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5216735210
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Progress in pmgen, add pmgen README
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |
Clifford Wolf
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55ac030382
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Fix pmgen "reject" statement
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |
Clifford Wolf
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d45379936b
|
Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |
Clifford Wolf
|
1f8e76f993
|
Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |
Clifford Wolf
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b9545aa0e1
|
Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-01-15 11:23:25 +01:00 |
Clifford Wolf
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ad69c668ce
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Add mockup .pmg (pattern matcher generator) file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-01-15 11:23:25 +01:00 |