Eddie Hung
|
429c9852ce
|
Add HOLD/RST support for SB_MAC16
|
2019-09-19 14:02:55 -07:00 |
Eddie Hung
|
2766465a2b
|
Add support for SB_MAC16 CD and H registers
|
2019-09-19 12:14:33 -07:00 |
Eddie Hung
|
c8310a6e76
|
Refactor ice40_dsp.pmg
|
2019-09-19 12:00:48 -07:00 |
Eddie Hung
|
29d446d758
|
Cleanup
|
2019-09-19 10:39:00 -07:00 |
Eddie Hung
|
f7dbfef792
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-09-18 12:40:21 -07:00 |
Eddie Hung
|
b66c99ece0
|
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
|
2019-09-18 12:40:08 -07:00 |
Eddie Hung
|
44bf4ac35c
|
Add doc on pattern detector for overflow
|
2019-09-18 12:35:24 -07:00 |
Eddie Hung
|
347cbf59bd
|
Check overflow condition is power of 2 without using int32
|
2019-09-18 12:16:03 -07:00 |
Eddie Hung
|
1f18736d20
|
Add support for overflow using pattern detector
|
2019-09-18 09:39:59 -07:00 |
Eddie Hung
|
0932e23dff
|
Separate dffrstmux from dffcemux, fix typos
|
2019-09-18 09:34:42 -07:00 |
Eddie Hung
|
14d72c39c3
|
Revert "Make one check $shift(x)? only; change testcase to be 8b"
This reverts commit e2c2d784c8 .
|
2019-09-13 16:33:18 -07:00 |
Eddie Hung
|
3a39073302
|
Set more ports explicitly
|
2019-09-12 17:10:43 -07:00 |
Eddie Hung
|
f3081c20e7
|
Add support for A1 and B1 registers
|
2019-09-11 17:16:46 -07:00 |
Eddie Hung
|
4369fc17d0
|
Raise a RuntimeError instead of AssertionError
|
2019-09-11 17:06:37 -07:00 |
Eddie Hung
|
6fa6bf483c
|
Rename {A,B} -> {A2,B2}
|
2019-09-11 16:21:24 -07:00 |
Eddie Hung
|
3a49aa6b4a
|
Tidy up
|
2019-09-11 14:20:49 -07:00 |
Eddie Hung
|
817ac7c5e0
|
Fix UB
|
2019-09-11 14:18:02 -07:00 |
Eddie Hung
|
63431fe42a
|
Fix UB
|
2019-09-11 14:17:45 -07:00 |
Eddie Hung
|
690b1a064d
|
Add PCOUT -> PCIN non-shifted cascading
|
2019-09-11 13:48:45 -07:00 |
Eddie Hung
|
c0f26c2da8
|
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
|
2019-09-11 13:37:11 -07:00 |
Eddie Hung
|
bdb5e0f29c
|
Cope with presence of reset muxes too
|
2019-09-11 13:36:37 -07:00 |
Eddie Hung
|
4937917cd8
|
Cleanup
|
2019-09-11 13:22:52 -07:00 |
Eddie Hung
|
e9eb855d38
|
Make unextend a udata
|
2019-09-11 13:06:49 -07:00 |
Eddie Hung
|
bbef0d2ac8
|
Only display log message if did_something
|
2019-09-11 12:29:26 -07:00 |
Eddie Hung
|
d232e6a6cd
|
Input registers to add DSP as new siguser to block upstream packing
|
2019-09-11 11:46:21 -07:00 |
Eddie Hung
|
e5bdb521fa
|
More cleanup
|
2019-09-11 10:55:45 -07:00 |
Eddie Hung
|
0d709d2bb5
|
Add support for A/B/C/D/AD reset
|
2019-09-11 10:15:19 -07:00 |
Eddie Hung
|
ded805ae5d
|
Add support for RSTM
|
2019-09-11 07:34:14 -07:00 |
Eddie Hung
|
fc7008671f
|
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
|
2019-09-11 00:57:25 -07:00 |
Eddie Hung
|
edf90afd20
|
Rename dffmuxext -> dffmux, also remove constants in dff+mux
|
2019-09-11 00:56:38 -07:00 |
Eddie Hung
|
6b23c7c227
|
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
|
2019-09-11 00:07:33 -07:00 |
Eddie Hung
|
feb3fa65a3
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-09-11 00:01:31 -07:00 |
Eddie Hung
|
b08797da6b
|
Only pack out registers if \init is zero or x; then remove \init from PREG
|
2019-09-10 21:33:14 -07:00 |
Eddie Hung
|
37a34eeb04
|
Fix RSTP
|
2019-09-10 20:56:13 -07:00 |
Eddie Hung
|
af147d1430
|
Add support for RSTP
|
2019-09-10 20:51:48 -07:00 |
Eddie Hung
|
c6df55a9e7
|
enpol -> cepol
|
2019-09-10 18:59:03 -07:00 |
Eddie Hung
|
86700c2bea
|
d?ffmux -> d?ffcemux
|
2019-09-10 18:52:54 -07:00 |
Eddie Hung
|
8b8a68b38a
|
Refactor MREG and PREG to out_dffe subpattern
|
2019-09-10 18:27:05 -07:00 |
Eddie Hung
|
e64e650f9c
|
Update help text
|
2019-09-10 16:35:10 -07:00 |
Eddie Hung
|
d30b2a6d7e
|
Update xilinx_dsp help text
|
2019-09-10 16:33:13 -07:00 |
Eddie Hung
|
cba63fe72b
|
Oops
|
2019-09-09 22:06:23 -07:00 |
Eddie Hung
|
02cf9933b9
|
Support subtraction as well
|
2019-09-09 21:39:42 -07:00 |
Eddie Hung
|
31e60353ac
|
Support TWO24
|
2019-09-09 21:11:41 -07:00 |
Eddie Hung
|
0bb6fd8448
|
Refactor
|
2019-09-09 20:58:54 -07:00 |
Eddie Hung
|
5a6552e56b
|
Add initial USE_SIMD=FOUR12 support
|
2019-09-09 20:57:20 -07:00 |
Eddie Hung
|
2c04430445
|
Only trim sigM if USE_MULT; only look for ffM then too
|
2019-09-09 20:57:03 -07:00 |
Eddie Hung
|
be0eaf3a9a
|
Fix misspelling
|
2019-09-09 16:46:33 -07:00 |
Eddie Hung
|
6348f9512c
|
Rename
|
2019-09-09 16:45:38 -07:00 |
Eddie Hung
|
1df9c5d277
|
Oops
|
2019-09-09 16:07:40 -07:00 |
Eddie Hung
|
5f8f0e1383
|
Tidy up
|
2019-09-09 15:59:10 -07:00 |
Eddie Hung
|
04bc287271
|
Refactor using subpattern in_dffe
|
2019-09-09 15:51:14 -07:00 |
Eddie Hung
|
e2c2d784c8
|
Make one check $shift(x)? only; change testcase to be 8b
|
2019-09-06 22:48:23 -07:00 |
Eddie Hung
|
74a5c802f7
|
Pack CREG
|
2019-09-06 21:01:36 -07:00 |
Eddie Hung
|
6a9205280f
|
Use unextend lambda
|
2019-09-06 18:40:11 -07:00 |
Eddie Hung
|
b69512a5b9
|
Fix ffP just like ffPmux
|
2019-09-06 15:51:21 -07:00 |
Eddie Hung
|
5344bfe637
|
Perform D replacement properly
|
2019-09-06 15:46:15 -07:00 |
Eddie Hung
|
74eac76699
|
Add support for DREG
|
2019-09-06 15:32:26 -07:00 |
Eddie Hung
|
ef56f8596f
|
Fine tune nusers when postAdd
|
2019-09-06 15:11:41 -07:00 |
Eddie Hung
|
0d1d8b4d24
|
Fix macc and mul tests
|
2019-09-06 14:57:36 -07:00 |
Eddie Hung
|
8246062acf
|
Fix enable polarity
|
2019-09-06 14:36:10 -07:00 |
Eddie Hung
|
2c32056990
|
Logging for ffAD
|
2019-09-06 14:10:12 -07:00 |
Eddie Hung
|
e926f2973e
|
Add support for pre-adder and AD register
|
2019-09-06 14:06:57 -07:00 |
Eddie Hung
|
da8fe83f7a
|
Tidy up ice40_dsp some more
|
2019-09-06 12:16:40 -07:00 |
Eddie Hung
|
776d769941
|
Use more index patterns
|
2019-09-06 12:07:35 -07:00 |
Eddie Hung
|
a945f6c7ef
|
Fix ffPmux to cope with offset
|
2019-09-06 11:58:56 -07:00 |
Eddie Hung
|
fbf1b74946
|
Simplify filter expressions
|
2019-09-06 11:39:20 -07:00 |
Eddie Hung
|
39a5d046ea
|
Fix nusers condition in ffP
|
2019-09-06 11:38:19 -07:00 |
Eddie Hung
|
cdc1e1f5c2
|
Check adder is <= 48 bits before packing
|
2019-09-06 10:35:06 -07:00 |
Eddie Hung
|
91f68c4de2
|
Check nusers for M and P enable muxes
|
2019-09-06 09:59:35 -07:00 |
Eddie Hung
|
4fe24b20f9
|
More nusers() checks for A and B enable muxes
|
2019-09-06 09:47:32 -07:00 |
Eddie Hung
|
dc10559f31
|
Cleanup
|
2019-09-05 21:39:52 -07:00 |
Eddie Hung
|
174edbcb96
|
Sensitive to CEB CEM CEP polarity
|
2019-09-05 21:38:35 -07:00 |
Eddie Hung
|
53ca536d67
|
ffAmuxAB -> ffAenpol
|
2019-09-05 21:28:28 -07:00 |
Eddie Hung
|
5a2fc6fcb5
|
Refactor ice40_dsp
|
2019-09-05 18:06:59 -07:00 |
Eddie Hung
|
888ae1d05e
|
Fix broken ice40_dsp
|
2019-09-05 17:58:19 -07:00 |
Eddie Hung
|
38e73a3788
|
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
|
2019-09-05 13:01:34 -07:00 |
Eddie Hung
|
a32b14a55f
|
Do not check signedness of post-adder (assume taken care of by DSP)
|
2019-09-05 12:38:47 -07:00 |
Eddie Hung
|
7bd55f379c
|
Use filter instead of index; support wide enable muxes
|
2019-09-05 11:55:14 -07:00 |
Eddie Hung
|
fe5a1324c9
|
Do not make ff[MP]mux semioptional, use sigmap
|
2019-09-05 11:46:38 -07:00 |
Eddie Hung
|
447a31e75d
|
Add support for CEP
|
2019-09-05 11:00:27 -07:00 |
Eddie Hung
|
05282afc25
|
Add support for CEB, remove check on nusers
|
2019-09-05 10:46:33 -07:00 |
Eddie Hung
|
0166e02e78
|
Cleanup
|
2019-09-05 10:07:56 -07:00 |
Eddie Hung
|
aa462da395
|
Support CEA
|
2019-09-05 10:07:26 -07:00 |
Eddie Hung
|
09c26c55bb
|
Get rid of sigBset too
|
2019-09-04 17:22:02 -07:00 |
Eddie Hung
|
91ef4457b0
|
Get rid of sigAset
|
2019-09-04 17:18:49 -07:00 |
Eddie Hung
|
42548d9790
|
Get rid of sigPused
|
2019-09-04 17:06:17 -07:00 |
Eddie Hung
|
93d798272d
|
Compute sigP properly
|
2019-09-04 16:59:57 -07:00 |
Eddie Hung
|
433b0c677c
|
Remove log_cell() calls
|
2019-09-04 13:42:44 -07:00 |
Eddie Hung
|
229e54568e
|
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
|
2019-09-04 12:37:48 -07:00 |
Eddie Hung
|
2b86055848
|
Add peepopt_dffmuxext
|
2019-09-04 12:35:15 -07:00 |
Eddie Hung
|
e67e4a5ed6
|
Support CEM
|
2019-09-04 10:52:51 -07:00 |
Eddie Hung
|
80aec0f006
|
st.ffP from if to assert
|
2019-09-03 16:37:59 -07:00 |
Eddie Hung
|
16316aa05d
|
Rename muxAB to postAddMux
|
2019-09-03 16:24:59 -07:00 |
Eddie Hung
|
cd002ad3fb
|
Use choices for addAB, now called postAdd
|
2019-09-03 16:10:16 -07:00 |
Eddie Hung
|
2d80866daf
|
Add support for load value into DSP48E1.P
|
2019-09-03 15:53:10 -07:00 |
Eddie Hung
|
682153de4b
|
Process post-adder first since C could be used for load-P
|
2019-09-03 14:57:59 -07:00 |
Eddie Hung
|
97d11708e0
|
Use feedback path for MACC
|
2019-09-03 14:37:32 -07:00 |
Eddie Hung
|
4aa505d1b2
|
Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc
ice40_dsp to allow signed multipliers
|
2019-09-01 10:11:33 -07:00 |
Eddie Hung
|
a09e69dd56
|
Fine tune xilinx_dsp pattern matcher
|
2019-08-30 16:18:58 -07:00 |
Eddie Hung
|
8f503fe3e6
|
autoremove ffM
|
2019-08-30 15:30:04 -07:00 |
Eddie Hung
|
e67f049e3b
|
Remove debug
|
2019-08-30 15:03:43 -07:00 |
Eddie Hung
|
15bab02a1b
|
ffM before addAB
|
2019-08-30 15:03:12 -07:00 |
Eddie Hung
|
c497114e94
|
Another oops
|
2019-08-30 15:02:53 -07:00 |
Eddie Hung
|
44a35015b3
|
Update commented out
|
2019-08-30 15:01:38 -07:00 |
Eddie Hung
|
390cf34d0a
|
Add support for ffM
|
2019-08-30 15:00:56 -07:00 |
Eddie Hung
|
2983a35dc0
|
Update comment
|
2019-08-30 15:00:40 -07:00 |
Eddie Hung
|
17b77fd411
|
Missing dep for test_pmgen
|
2019-08-30 14:01:07 -07:00 |
Eddie Hung
|
89359b6927
|
Missing dep for test_pmgen
|
2019-08-30 14:00:40 -07:00 |
Eddie Hung
|
723815b384
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-08-30 13:26:19 -07:00 |
Eddie Hung
|
c1459bc748
|
Do not restrict multiplier to unsigned
|
2019-08-30 12:22:14 -07:00 |
Eddie Hung
|
4e782f1509
|
New pmgen requires explicit accept
|
2019-08-30 11:02:10 -07:00 |
Eddie Hung
|
295c18bd6b
|
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
|
2019-08-30 09:50:20 -07:00 |
David Shah
|
6919c0f9b0
|
Merge branch 'master' into xc7dsp
|
2019-08-30 13:57:15 +01:00 |
Eddie Hung
|
4eb5847dbd
|
Cleanup
|
2019-08-28 18:10:33 -07:00 |
Eddie Hung
|
0af64df10c
|
Account for D port being a constant
|
2019-08-28 15:32:38 -07:00 |
Eddie Hung
|
52c4655de3
|
No need to replace Q of slice since $shiftx is autoremove-d
|
2019-08-28 11:06:11 -07:00 |
Eddie Hung
|
11e3eb1009
|
More cleanup
|
2019-08-28 10:19:35 -07:00 |
Eddie Hung
|
86b538bd02
|
More cleanup
|
2019-08-28 10:11:09 -07:00 |
Eddie Hung
|
c4d1bd988b
|
Do not use default_params dict, hardcode default values, cleanup
|
2019-08-28 10:06:40 -07:00 |
Eddie Hung
|
c3e9627afe
|
Always generate if no match
|
2019-08-28 09:54:56 -07:00 |
Eddie Hung
|
0ebe2c9831
|
Rename test_pmgen arg xilinx_srl.{fixed,variable}
|
2019-08-28 09:27:03 -07:00 |
Eddie Hung
|
9172d4a674
|
Missing close bracket
|
2019-08-26 21:02:52 -07:00 |
Eddie Hung
|
54422c5bb4
|
Remove leftover header
|
2019-08-26 17:51:13 -07:00 |
Eddie Hung
|
e95fb24574
|
Improve xilinx_srl.fixed generate, add .variable generate
|
2019-08-26 17:49:08 -07:00 |
Eddie Hung
|
45c34c87ee
|
Account for maxsubcnt overflowing
|
2019-08-26 17:48:54 -07:00 |
Eddie Hung
|
b32d6bf403
|
Add xilinx_srl_pm.variable to test_pmgen
|
2019-08-26 17:44:57 -07:00 |
Eddie Hung
|
e574edc3e9
|
Populate generate for xilinx_srl.fixed pattern
|
2019-08-26 14:21:17 -07:00 |
Eddie Hung
|
cf9e017127
|
Add xilinx_srl_fixed, fix typos
|
2019-08-26 14:20:06 -07:00 |
Eddie Hung
|
7911143827
|
Create new $__XILINX_SHREG_ cell for variable length too
|
2019-08-23 18:15:49 -07:00 |
Eddie Hung
|
a048fc93e8
|
Do not allow Q of last cell of variable length SRL to be (* keep *)
|
2019-08-23 18:15:24 -07:00 |
Eddie Hung
|
ee9f6e6243
|
Also add first.Q to chain_bits since variable length
|
2019-08-23 18:14:06 -07:00 |
Eddie Hung
|
70ce3d0670
|
Do not enforce !EN_POLARITY on $dffe
|
2019-08-23 18:11:28 -07:00 |
Eddie Hung
|
188b49378a
|
Create new cell for fixed length SRL
|
2019-08-23 17:25:30 -07:00 |
Eddie Hung
|
e081303ee8
|
Cleanup FDRE matching
|
2019-08-23 17:23:52 -07:00 |
Eddie Hung
|
54488cfb82
|
Oops don't need a finally block
|
2019-08-23 16:39:37 -07:00 |
Eddie Hung
|
83e2d87fb8
|
Keep track of bits in variable length chain, to check for taps
|
2019-08-23 16:21:10 -07:00 |
Eddie Hung
|
f2d4814284
|
Don't forget $dff has no EN
|
2019-08-23 16:14:57 -07:00 |
Eddie Hung
|
2217d926a9
|
Same for variable length
|
2019-08-23 16:13:16 -07:00 |
Eddie Hung
|
b1caf7be5e
|
Filter on en_port for fixed length
|
2019-08-23 16:09:46 -07:00 |
Eddie Hung
|
513af10d77
|
Check clock is consistent
|
2019-08-23 15:18:26 -07:00 |
Eddie Hung
|
c762618783
|
Fix last_cell.D
|
2019-08-23 15:08:49 -07:00 |
Eddie Hung
|
ca5de78e76
|
Revert "Add a unique argument to pmgen's nusers()"
This reverts commit 1d88887cfd .
|
2019-08-23 15:04:00 -07:00 |
Eddie Hung
|
e85e6e8d45
|
Revert "Fix polarity"
This reverts commit 9cd23cf0fe .
|
2019-08-23 15:03:42 -07:00 |
Eddie Hung
|
9cd23cf0fe
|
Fix polarity
|
2019-08-23 14:49:34 -07:00 |
Eddie Hung
|
c2757613b6
|
Check for non unique nusers/fanouts
|
2019-08-23 14:32:36 -07:00 |
Eddie Hung
|
1d88887cfd
|
Add a unique argument to pmgen's nusers()
|
2019-08-23 14:32:17 -07:00 |
Eddie Hung
|
8ecfd55d5a
|
Update doc
|
2019-08-23 14:16:41 -07:00 |
Eddie Hung
|
3d7f4aa0c8
|
Remove (* init *) entry when consumed into SRL
|
2019-08-23 13:56:01 -07:00 |
Eddie Hung
|
967a36c125
|
indo -> into
|
2019-08-23 13:16:50 -07:00 |
Eddie Hung
|
a1f78eab04
|
indo -> into
|
2019-08-23 13:15:41 -07:00 |
Eddie Hung
|
5939ffdc07
|
Forgot to slice
|
2019-08-23 13:06:59 -07:00 |
Eddie Hung
|
242b3083ea
|
Cope with possibility that D could connect to Q on same cell
|
2019-08-23 13:06:31 -07:00 |
Eddie Hung
|
18b64609c2
|
xilinx_srl to use 'slice' features of pmgen for word level
|
2019-08-23 12:22:06 -07:00 |
Eddie Hung
|
f4fd41d5d2
|
Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl
|
2019-08-23 11:35:06 -07:00 |
Clifford Wolf
|
55bf8f69e0
|
Fix port hanlding in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-23 16:26:54 +02:00 |
Clifford Wolf
|
adb81ba386
|
Add pmgen slices and choices
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-23 16:15:50 +02:00 |
Eddie Hung
|
6e8fda8bf0
|
Add doc
|
2019-08-22 11:52:24 -07:00 |
Eddie Hung
|
cabadb85e2
|
Add copyright
|
2019-08-22 11:25:19 -07:00 |
Eddie Hung
|
9f3ed1726e
|
pmgen to also iterate over all module ports
|
2019-08-22 11:15:16 -07:00 |
Eddie Hung
|
74bd190d3b
|
Remove output_bits
|
2019-08-22 11:14:59 -07:00 |
Eddie Hung
|
231ddbf95c
|
Forgot to set ud_variable.minlen
|
2019-08-22 11:02:17 -07:00 |
Eddie Hung
|
61639d5387
|
Do not run xilinx_srl_pm in fixed loop
|
2019-08-22 10:51:04 -07:00 |
Eddie Hung
|
d0b2973413
|
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
|
2019-08-22 10:32:06 -07:00 |
Eddie Hung
|
7d02d17b16
|
Reuse var
|
2019-08-21 19:18:40 -07:00 |
Eddie Hung
|
5c8344363f
|
Revert "Trim shiftx_width when upper bits are 1'bx"
This reverts commit 7e7965ca7b .
|
2019-08-21 19:18:27 -07:00 |
Eddie Hung
|
7e7965ca7b
|
Trim shiftx_width when upper bits are 1'bx
|
2019-08-21 18:43:17 -07:00 |
Eddie Hung
|
ed7be3e6b6
|
Add comment
|
2019-08-21 17:36:38 -07:00 |
Eddie Hung
|
15188033da
|
Add variable length support to xilinx_srl
|
2019-08-21 17:34:40 -07:00 |
Eddie Hung
|
6d76ae4c65
|
Rename pattern to fixed
|
2019-08-21 15:46:58 -07:00 |
Eddie Hung
|
b0a3b430bf
|
attribute -> attr
|
2019-08-21 15:44:07 -07:00 |
Eddie Hung
|
61b4d7ae13
|
Use Cell::has_keep_attribute()
|
2019-08-21 15:41:46 -07:00 |
Eddie Hung
|
6fa9e03e4c
|
xilinx_srl to support FDRE and FDRE_1
|
2019-08-21 15:35:29 -07:00 |
Eddie Hung
|
3c8e8521a6
|
Fix polarity of EN_POL
|
2019-08-21 14:42:11 -07:00 |
Eddie Hung
|
a980f0d4be
|
Add CLKPOL == 0
|
2019-08-21 14:35:40 -07:00 |
Eddie Hung
|
1c7d721558
|
Reject if not minlen from inside pattern matcher
|
2019-08-21 14:26:24 -07:00 |
Eddie Hung
|
cab2bd083e
|
Get wire via SigBit
|
2019-08-21 13:47:47 -07:00 |
Eddie Hung
|
52fea5b658
|
Respect \keep on cells or wires
|
2019-08-21 13:42:03 -07:00 |
Eddie Hung
|
5ce0c31d0e
|
Add init support
|
2019-08-21 13:05:10 -07:00 |
Eddie Hung
|
df53fe12e7
|
Fix spacing
|
2019-08-21 12:54:11 -07:00 |
Eddie Hung
|
0250712486
|
Initial progress on xilinx_srl
|
2019-08-21 12:50:49 -07:00 |
Miodrag Milanovic
|
948b6f91a1
|
Fix test_pmgen deps
|
2019-08-21 17:00:24 +02:00 |
Eddie Hung
|
4cc74346f1
|
Fix compile error
|
2019-08-20 20:27:05 -07:00 |
Eddie Hung
|
9b9d759451
|
Fix copy-paste typo
|
2019-08-20 20:18:51 -07:00 |
Eddie Hung
|
b7a48e3e0f
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-08-20 20:18:17 -07:00 |
Clifford Wolf
|
d0117d7d12
|
Merge branch 'master' into clifford/pmgen
|
2019-08-20 11:39:23 +02:00 |
Clifford Wolf
|
1e3dd0a2da
|
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
|
2019-08-19 13:04:06 +02:00 |
Miodrag Milanovic
|
dbe3cb9708
|
Ignore all generated headers for pmgen pass
|
2019-08-18 10:49:17 +02:00 |
Clifford Wolf
|
f3405fb048
|
Refactor pmgen rollback mechanism
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-17 13:54:18 +02:00 |
Clifford Wolf
|
318ae0351c
|
Improvements in "test_pmgen -generate"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-17 13:53:55 +02:00 |
Clifford Wolf
|
f95853c822
|
Add pmgen "fallthrough" statement
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-17 11:29:37 +02:00 |
Eddie Hung
|
cd5a372cd1
|
Add help() call
|
2019-08-16 13:00:12 -07:00 |
Clifford Wolf
|
64bd414e54
|
Minor bugfix in "test_pmgen -generate"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 14:35:13 +02:00 |
Clifford Wolf
|
20910fd7c8
|
Add pmgen finish statement, return number of matches
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 14:16:35 +02:00 |
Clifford Wolf
|
f45dad8220
|
Redesign pmgen backtracking for recursive matching
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 13:47:50 +02:00 |
Clifford Wolf
|
c710df181c
|
Add pmgen "generate" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 13:26:36 +02:00 |
Clifford Wolf
|
4a57b7e1ab
|
Refactor demo_reduce into test_pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 11:47:51 +02:00 |
Clifford Wolf
|
016036f247
|
Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-15 23:02:37 +02:00 |
Clifford Wolf
|
969ab9027a
|
Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-15 22:48:13 +02:00 |
Clifford Wolf
|
eb80d3d43f
|
Change pmgen default rule to reject, switch peepopt behavior to accept
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-15 22:47:59 +02:00 |
Eddie Hung
|
c320abc3f4
|
xilinx_dsp to be sensitive to keep attribute
|
2019-08-15 12:34:11 -07:00 |