Udi Finkelstein
73d426bc87
Modified errors into warnings
...
No longer false warnings for memories and assertions
2018-06-05 18:03:22 +03:00
Clifford Wolf
4372cf690d
Add (* gclk *) attribute support
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 13:25:42 +02:00
Clifford Wolf
a572b49538
Replace -ignore_redef with -[no]overwrite
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-03 15:25:59 +02:00
Udi Finkelstein
2b9c75f8e3
This PR should be the base for discussion, do not merge it yet!
...
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.
What it DOES'T do:
Detect registers connected to output ports of instances.
Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.
You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-11 23:09:34 +02:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
c80315cea4
Bugfix in hierarchy handling of blackbox module ports
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-05 13:28:45 +01:00
Clifford Wolf
8364f509e3
Fix error handling for nested always/initial
2017-12-02 18:52:05 +01:00
Clifford Wolf
bc80426d45
Remove some dead code
2017-10-10 12:00:48 +02:00
Clifford Wolf
caa78388cd
Allow $past, $stable, $rose, $fell in $global_clock blocks
2017-10-10 11:59:32 +02:00
Udi Finkelstein
eb40278a16
Turned a few member functions into const, esp. dumpAst(), dumpVlog().
2017-09-30 07:37:38 +03:00
Clifford Wolf
dbfd8460a9
Allow $size and $bits in verilog mode, actually check test case
2017-09-29 11:56:43 +02:00
Udi Finkelstein
e951ac0dfb
$size() now works correctly for all cases!
...
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
2017-09-26 20:34:24 +03:00
Udi Finkelstein
6ddc6a7af4
$size() seems to work now with or without the optional parameter.
...
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
2017-09-26 19:18:25 +03:00
Udi Finkelstein
7e391ba904
enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog
2017-09-26 09:19:56 +03:00
Udi Finkelstein
2dea42e903
Added $bits() for memories as well.
2017-09-26 09:11:25 +03:00
Udi Finkelstein
17f8b41605
$size() now works with memories as well!
2017-09-26 08:36:45 +03:00
Udi Finkelstein
64eb8f29ad
Add $size() function. At the moment it works only on expressions, not on memories.
2017-09-26 06:25:42 +03:00
Clifford Wolf
8f8baccfde
Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"
2017-06-07 12:30:24 +02:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
1e927a51d5
Preserve string parameters
2017-02-23 15:39:13 +01:00
Clifford Wolf
4fb8007171
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions
2017-02-14 15:10:59 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
78f65f89ff
Fix bug in AstNode::mem2reg_as_needed_pass2()
2017-01-15 13:52:50 +01:00
Clifford Wolf
2d32c6c4f6
Fixed handling of local memories in functions
2017-01-05 13:19:03 +01:00
Clifford Wolf
81a9ee2360
Added handling of local memories and error for local decls in unnamed blocks
2017-01-04 16:03:04 +01:00
Clifford Wolf
dfb461fe52
Added Verilog $rtoi and $itor support
2017-01-03 17:40:58 +01:00
Clifford Wolf
70d7a02cae
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
Clifford Wolf
a926a6afc2
Remember global declarations and defines accross read_verilog calls
2016-11-15 12:42:43 +01:00
Clifford Wolf
2874914bcb
Fixed anonymous genblock object names
2016-11-04 07:46:30 +01:00
Clifford Wolf
56e2bb88ae
Some fixes in handling of signed arrays
2016-11-01 23:17:43 +01:00
Clifford Wolf
aa72262330
Added avail params to ilang format, check module params in 'hierarchy -check'
2016-10-22 11:05:49 +02:00
Clifford Wolf
bdc316db50
Added $anyseq cell type
2016-10-14 15:24:03 +02:00
Clifford Wolf
53655d173b
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
Clifford Wolf
aaa99c35bd
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
Clifford Wolf
ab18e9df7c
Added assertpmux
2016-09-07 00:28:01 +02:00
Clifford Wolf
97583ab729
Avoid creation of bogus initial blocks for assert/assume in always @*
2016-09-06 17:34:42 +02:00
Clifford Wolf
aa25a4cec6
Added $anyconst support to yosys-smtbmc
2016-08-30 19:27:42 +02:00
Clifford Wolf
6f41e5277d
Removed $aconst cell type
2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
450f6f59b4
Fixed bug with memories that do not have a down-to-zero data width
2016-08-22 14:27:46 +02:00
Clifford Wolf
82a4a0230f
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
Clifford Wolf
dbdd8927e7
Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()
2016-08-21 13:18:09 +02:00
Clifford Wolf
fe9315b7a1
Fixed finish_addr handling in $readmemh/$readmemb
2016-08-20 13:47:46 +02:00
Clifford Wolf
f6629b9c29
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
2016-08-19 18:38:25 +02:00
Clifford Wolf
e9fe57c75e
Only allow posedge/negedge with 1 bit wide signals
2016-08-10 19:32:11 +02:00
Clifford Wolf
4056312987
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
Clifford Wolf
a7b0769623
Added "read_verilog -dump_rtlil"
2016-07-27 15:40:17 +02:00
Clifford Wolf
7fef5ff104
Using $initstate in "initial assume" and "initial assert"
2016-07-21 14:37:28 +02:00
Clifford Wolf
5c166e76e5
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Clifford Wolf
9a101dc1f7
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
Ruben Undheim
a8200a773f
A few modifications after pull request comments
...
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
2016-06-18 14:23:38 +02:00
Ruben Undheim
178ff3e7f6
Added support for SystemVerilog packages with localparam definitions
2016-06-18 10:53:55 +02:00
Clifford Wolf
766032c5f8
Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
2016-05-27 17:55:03 +02:00
Clifford Wolf
ee071586c5
Fixed access-after-delete bug in mem2reg code
2016-05-27 17:25:33 +02:00
Clifford Wolf
e9ceec26ff
fixed typos in error messages
2016-05-27 16:37:36 +02:00
Clifford Wolf
570014800a
Include <cmath> in yosys.h
2016-05-08 10:50:39 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
5a09fa4553
Fixed handling of parameters and const functions in casex/casez pattern
2016-04-21 15:31:54 +02:00
Clifford Wolf
5328a85149
Do not set "nosync" on task outputs, fixes #134
2016-03-24 12:16:47 +01:00
Clifford Wolf
4f0d4899ce
Added support for $stop system task
2016-03-21 16:19:51 +01:00
Clifford Wolf
e5d42ebb4d
Added $display %m support, fixed mem leak in $display, fixes #128
2016-03-19 11:51:13 +01:00
Clifford Wolf
ef4207d5ad
Fixed localparam signdness, fixes #127
2016-03-18 12:15:00 +01:00
Clifford Wolf
b6d08f39ba
Set "nosync" attribute on internal task/function wires
2016-03-18 10:53:29 +01:00
Clifford Wolf
bcc873b805
Fixed some visual studio warnings
2016-02-13 17:31:24 +01:00
Rick Altherr
34969d4140
genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree()
2016-01-31 09:20:16 -08:00
Clifford Wolf
c86fbae3d1
Fixed handling of re-declarations of wires in tasks and functions
2015-11-23 17:09:57 +01:00
Clifford Wolf
7ae3d1b5a9
More bugfixes in handling of parameters in tasks and functions
2015-11-12 13:02:36 +01:00
Clifford Wolf
34f2b84fb6
Fixed handling of parameters and localparams in functions
2015-11-11 10:54:35 +01:00
Clifford Wolf
207736b4ee
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
Clifford Wolf
e51dcc83d0
Fixed complexity of assigning to vectors in constant functions
2015-10-01 12:15:35 +02:00
Clifford Wolf
9caeadf797
Fixed detection of unconditional $readmem[hb]
2015-09-30 15:46:51 +02:00
Clifford Wolf
f9d7df0869
Bugfixes in $readmem[hb]
2015-09-25 13:49:48 +02:00
Clifford Wolf
b2544cfcf7
Fixed segfault in AstNode::asReal
2015-09-25 12:38:01 +02:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
1b8cb9940e
Fixed AstNode::mkconst_bits() segfault on zero-sized constant
2015-09-24 11:21:20 +02:00
Clifford Wolf
089c1e176f
Bugfix in handling of multi-dimensional memories
2015-09-23 07:56:17 +02:00
Clifford Wolf
559929e341
Warning for $display/$write outside initial block
2015-09-23 07:16:03 +02:00
Clifford Wolf
6176f4d081
Fixed multi-level prefix resolving
2015-09-22 20:52:02 +02:00
Andrew Zonenberg
c469f22144
Improvements to $display system task
2015-09-19 10:33:37 +02:00
Clifford Wolf
9db05d17fe
Added AST_INITIAL checks for $finish and $display
2015-09-18 09:50:57 +02:00
Andrew Zonenberg
7141f65533
Initial implementation of $display()
2015-09-18 09:36:46 +02:00
Andrew Zonenberg
e446e651cb
Initial implementation of $finish()
2015-09-18 09:30:25 +02:00
Clifford Wolf
eb38722e98
Fixed handling of memory read without address
2015-08-22 14:46:42 +02:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
...
Smaller this time
2015-08-14 23:27:05 +02:00
Larry Doolittle
022f570563
Keep gcc from complaining about uninitialized variables
2015-08-14 23:26:49 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
Clifford Wolf
8d6d5c30d9
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
Clifford Wolf
4513ff1b85
Fixed nested mem2reg
2015-07-29 16:37:08 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
13983e8318
Fixed handling of parameters with reversed range
2015-06-08 14:03:06 +02:00
Clifford Wolf
99b8746d27
Fixed signedness of genvar expressions
2015-05-29 20:08:00 +02:00
Clifford Wolf
422794c584
Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
2015-03-01 11:20:22 +01:00
Clifford Wolf
1f1deda888
Added non-std verilog assume() statement
2015-02-26 18:47:39 +01:00
Clifford Wolf
d5ce9a32ef
Added deep recursion warning to AST simplify
2015-02-20 10:33:20 +01:00
Clifford Wolf
dc1a0f06fc
Parser support for complex delay expressions
2015-02-20 10:21:36 +01:00
Clifford Wolf
c2ba4fb2fd
Convert floating point cell parameters to strings
2015-02-18 23:35:23 +01:00
Clifford Wolf
e9368a1d7e
Various fixes for memories with offsets
2015-02-14 14:21:15 +01:00
Clifford Wolf
7f1a1759d7
Added "read_verilog -nomeminit" and "nomeminit" attribute
2015-02-14 11:21:12 +01:00
Clifford Wolf
a8e9d37c14
Creating $meminit cells in verilog front-end
2015-02-14 10:49:30 +01:00
Clifford Wolf
cd919abdf1
Added AstNode::simplify() recursion counter
2015-02-13 12:33:12 +01:00
Clifford Wolf
234a45a3d5
Ignore explicit assignments to constants in HDL code
2015-02-08 00:58:03 +01:00
Clifford Wolf
c8305e3a6d
Fixed a bug with autowire bit size
...
(removed leftover from when we tried to auto-size the wires)
2015-02-08 00:48:23 +01:00
Clifford Wolf
2a9ad48eb6
Added ENABLE_NDEBUG makefile options
2015-01-24 12:16:46 +01:00
Clifford Wolf
df9d096a7d
Ignoring more system task and functions
2015-01-15 13:08:19 +01:00
Clifford Wolf
a588a4a5c9
Fixed handling of "input foo; reg [0:0] foo;"
2015-01-15 12:53:12 +01:00
Clifford Wolf
8e8e791fb5
Consolidate "Blocking assignment to memory.." msgs for the same line
2015-01-15 12:41:52 +01:00
Clifford Wolf
eefe78be09
Fixed memory->start_offset handling
2015-01-01 12:56:01 +01:00
Clifford Wolf
0bb6b24c11
Added global yosys_celltypes
2014-12-29 14:30:33 +01:00
Clifford Wolf
90bc71dd90
dict/pool changes in ast
2014-12-29 03:11:50 +01:00
Clifford Wolf
137f35373f
Changed more code to dict<> and pool<>
2014-12-28 19:24:24 +01:00
Clifford Wolf
12ca6538a4
Fixed mem2reg warning message
2014-12-27 03:26:30 +01:00
Clifford Wolf
a6c96b986b
Added Yosys::{dict,nodict,vector} container types
2014-12-26 10:53:21 +01:00
Clifford Wolf
edb3c9d0c4
Renamed extend() to extend_xx(), changed most users to extend_u0()
2014-12-24 09:51:17 +01:00
Clifford Wolf
fe829bdbdc
Added log_warning() API
2014-11-09 10:44:23 +01:00
Clifford Wolf
37aa2e02db
AST simplifier: optimize constant AST_CASE nodes before recursively descending
2014-10-29 08:29:51 +01:00
Clifford Wolf
c4a2b3c1e9
Improvements in $readmem[bh] implementation
2014-10-26 23:29:36 +01:00
Clifford Wolf
70b2efdb05
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
Clifford Wolf
26cbe4a4e5
Fixed constant "cond ? string1 : string2" with strings of different size
2014-10-25 18:23:53 +02:00
Clifford Wolf
750c615e7f
minor indenting corrections
2014-10-19 18:42:03 +02:00
Parviz Palangpour
de8adb8ec5
Builds on Mac 10.9.2 with LLVM 3.5.
2014-10-19 11:14:43 -05:00
Clifford Wolf
84ffe04075
Fixed various VS warnings
2014-10-18 15:20:38 +02:00
William Speirs
fda52f05f2
Wrapped math in int constructor
2014-10-17 11:28:14 +02:00
Clifford Wolf
6b05a9e807
Fixed handling of invalid array access in mem2reg code
2014-10-16 00:44:23 +02:00
Clifford Wolf
35fbc0b35f
Do not the 'z' modifier in format string (another win32 fix)
2014-10-11 11:42:08 +02:00
Clifford Wolf
4569a747f8
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
48b00dccea
Another $clog2 bugfix
2014-09-08 12:25:23 +02:00
Clifford Wolf
680eaaac41
Fixed $clog2 (off by one error)
2014-09-06 19:31:04 +02:00
Clifford Wolf
deff416ea7
Fixed assignment of out-of bounds array element
2014-09-06 17:58:27 +02:00
Ruben Undheim
79cbf9067c
Corrected spelling mistakes found by lintian
2014-09-06 08:47:06 +02:00
Clifford Wolf
8927aa6148
Removed $bu0 cell type
2014-09-04 02:07:52 +02:00
Clifford Wolf
98442e019d
Added emscripten (emcc) support to build system and some build fixes
2014-08-22 16:20:22 +02:00
Clifford Wolf
74af3a2b70
Archibald Rust and Clifford Wolf: ffi-based dpi_call()
2014-08-22 14:22:09 +02:00
Clifford Wolf
ad146c2582
Fixed small memory leak in ast simplify
2014-08-21 17:33:40 +02:00
Clifford Wolf
6c5cafcd8b
Added support for DPI function with different names in C and Verilog
2014-08-21 17:22:04 +02:00
Clifford Wolf
085c8e873d
Added AstNode::asInt()
2014-08-21 17:11:51 +02:00
Clifford Wolf
490d7a5bf2
Fixed memory leak in DPI function calls
2014-08-21 13:09:47 +02:00
Clifford Wolf
7bfc4ae120
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
Clifford Wolf
38addd4c67
Added support for global tasks and functions
2014-08-21 12:42:28 +02:00
Clifford Wolf
640d9fc551
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
Clifford Wolf
acb435b6cf
Added const folding of AST_CASE to AST simplifier
2014-08-18 00:02:30 +02:00
Clifford Wolf
64713647a9
Improved AST ProcessGenerator performance
2014-08-17 02:17:49 +02:00
Clifford Wolf
d491fd8c19
Use stackmap<> in AST ProcessGenerator
2014-08-17 00:57:24 +02:00
Clifford Wolf
83e2698e10
AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
2014-08-16 19:31:59 +02:00
Clifford Wolf
c7afbd9d8e
Fixed bug in "read_verilog -ignore_redef"
2014-08-15 01:53:22 +02:00
Clifford Wolf
978a933b6a
Added RTLIL::SigSpec::to_sigbit_map()
2014-08-14 23:14:47 +02:00
Clifford Wolf
c83b990458
Changed the AST genWidthRTLIL subst interface to use a std::map
2014-08-14 23:02:07 +02:00
Clifford Wolf
85e3cc12ac
Fixed handling of task outputs
2014-08-14 22:26:10 +02:00
Clifford Wolf
1bf7a18fec
Added module->ports
2014-08-14 16:22:52 +02:00
Clifford Wolf
d259abbda2
Added AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 15:52:54 +02:00
Clifford Wolf
91dd87e60b
Improved scope resolution of local regs in Verilog+AST frontend
2014-08-05 12:15:53 +02:00
Clifford Wolf
0129d41efa
Fixed AST handling of variables declared inside a functions main block
2014-08-05 08:35:51 +02:00
Clifford Wolf
768eb846c4
More bugfixes related to new RTLIL::IdString
2014-08-02 18:14:21 +02:00
Clifford Wolf
b9bd22b8c8
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Clifford Wolf
14412e6c95
Preparations for RTLIL::IdString redesign: cleanup of existing code
2014-08-02 00:45:25 +02:00
Clifford Wolf
bd74ed7da4
Replaced sha1 implementation
2014-08-01 19:01:10 +02:00
Clifford Wolf
cdae8abe16
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
Clifford Wolf
e6d33513a5
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
Clifford Wolf
1cb25c05b3
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
Clifford Wolf
397b00252d
Added $shift and $shiftx cell types (needed for correct part select behavior)
2014-07-29 16:35:13 +02:00
Clifford Wolf
48822e79a3
Removed left over debug code
2014-07-28 19:38:30 +02:00
Clifford Wolf
ec58965967
Fixed part selects of parameters
2014-07-28 19:24:28 +02:00
Clifford Wolf
a03297a7df
Set results of out-of-bounds static bit/part select to undef
2014-07-28 16:09:50 +02:00
Clifford Wolf
55521c085a
Fixed RTLIL code generator for part select of parameter
2014-07-28 15:31:19 +02:00
Clifford Wolf
0598bc8708
Fixed width detection for part selects
2014-07-28 15:19:34 +02:00
Clifford Wolf
27a872d1e7
Added support for "upto" wires to Verilog front- and back-end
2014-07-28 14:25:03 +02:00
Clifford Wolf
3c45277ee0
Added wire->upto flag for signals such as "wire [0:7] x;"
2014-07-28 12:12:13 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
ee65dea738
Fixed signdness detection of expressions with bit- and part-selects
2014-07-28 10:10:08 +02:00
Clifford Wolf
c4bdba78cb
Added proper Design->addModule interface
2014-07-27 21:12:09 +02:00
Clifford Wolf
10e5791c5e
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
Clifford Wolf
f9946232ad
Refactoring: Renamed RTLIL::Module::wires to wires_
2014-07-27 01:49:51 +02:00
Clifford Wolf
946ddff9ce
Changed a lot of code to the new RTLIL::Wire constructors
2014-07-26 20:12:50 +02:00
Clifford Wolf
f8fdc47d33
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302
Changed users of cell->connections_ to the new API (sed command)
...
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b
Renamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 11:58:03 +02:00
Clifford Wolf
2bec47a404
Use only module->addCell() and module->remove() to create and delete cells
2014-07-25 17:56:19 +02:00
Clifford Wolf
309d64d46a
Fixed two memory leaks in ast simplify
2014-07-25 13:24:10 +02:00
Clifford Wolf
6aa792c864
Replaced more old SigChunk programming patterns
2014-07-24 23:10:58 +02:00
Clifford Wolf
20a7965f61
Various small fixes (from gcc compiler warnings)
2014-07-23 20:45:27 +02:00
Clifford Wolf
c094c53de8
Removed RTLIL::SigSpec::optimize()
2014-07-23 20:32:28 +02:00
Clifford Wolf
115dd959d9
SigSpec refactoring: More cleanups of old SigSpec use pattern
2014-07-22 23:50:21 +02:00
Clifford Wolf
28b3fd05fa
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
2014-07-22 20:58:44 +02:00
Clifford Wolf
7bffde6abd
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
2014-07-22 20:39:38 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
9b183539af
Implemented dynamic bit-/part-select for memory writes
2014-07-17 16:49:23 +02:00
Clifford Wolf
5867f6bcdc
Added support for bit/part select to mem2reg rewriter
2014-07-17 13:49:32 +02:00
Clifford Wolf
6d69d4aaa8
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
Clifford Wolf
543551b80a
changes in verilog frontend for new $mem/$memwr WR_EN interface
2014-07-16 12:49:50 +02:00
Clifford Wolf
55a1b8dbac
Fixed processing of initial values for block-local variables
2014-07-11 13:05:53 +02:00
Clifford Wolf
076182c34e
Fixed handling of mixed real/int ternary expressions
2014-06-25 10:05:36 +02:00
Clifford Wolf
4fc43d1932
More found_real-related fixes to AstNode::detectSignWidthWorker
2014-06-24 15:08:48 +02:00
Clifford Wolf
65b2e9c064
fixed signdness detection for expressions with reals
2014-06-21 21:41:13 +02:00
Clifford Wolf
80e4594695
Added AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 21:39:25 +02:00
Clifford Wolf
798ff88855
Improved handling of relational op of real values
2014-06-17 12:47:51 +02:00
Clifford Wolf
6c17d4f242
Improved ternary support for real values
2014-06-16 15:12:24 +02:00
Clifford Wolf
82bbd2f077
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
2014-06-16 15:05:37 +02:00
Clifford Wolf
5bfe865cec
Added found_real feature to AstNode::detectSignWidth
2014-06-16 15:00:57 +02:00
Clifford Wolf
4d1df128fa
Improved AstNode::realAsConst for large numbers
2014-06-15 09:27:09 +02:00
Clifford Wolf
48dc6ab98d
Improved AstNode::asReal for large integers
2014-06-15 08:38:31 +02:00
Clifford Wolf
149fe83a8d
improved (fixed) conversion of real values to bit vectors
2014-06-14 21:00:51 +02:00
Clifford Wolf
d5765b5e14
Fixed relational operators for const real expressions
2014-06-14 19:33:58 +02:00
Clifford Wolf
f3b4a9dd24
Added support for math functions
2014-06-14 13:36:23 +02:00
Clifford Wolf
9bd7d5c468
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
Clifford Wolf
fc7b6d172a
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
Clifford Wolf
442a8e2875
Implemented basic real arithmetic
2014-06-14 08:51:22 +02:00
Clifford Wolf
9dd16fa41c
Added real->int convertion in ast genrtlil
2014-06-14 07:44:19 +02:00
Clifford Wolf
7ef0da32cd
Added Verilog lexer and parser support for real values
2014-06-13 11:29:23 +02:00
Clifford Wolf
e275e8eef9
Add support for cell arrays
2014-06-07 11:48:50 +02:00
Clifford Wolf
0b1ce63a19
Added support for repeat stmt in const functions
2014-06-07 10:47:53 +02:00
Clifford Wolf
7c8a7b2131
further improved const function support
2014-06-07 00:02:05 +02:00
Clifford Wolf
76da2fe172
improved const function support
2014-06-06 22:55:02 +02:00
Clifford Wolf
5c10d2ee36
fix functions with no block (but single statement, loop, etc.)
2014-06-06 21:29:23 +02:00
Clifford Wolf
ab54ce17c8
improved ast simplify of const functions
2014-06-06 17:40:45 +02:00
Clifford Wolf
b5cd7a0179
added while and repeat support to verilog parser
2014-06-06 17:40:04 +02:00
Clifford Wolf
09805ee9ec
Include id2ast pointers when dumping AST
2014-03-05 19:56:31 +01:00
Clifford Wolf
d6a01fe412
Fixed merging of compatible wire decls in AST frontend
2014-03-05 19:55:58 +01:00
Clifford Wolf
de7bd12004
Bugfix in recursive AST simplification
2014-03-05 19:45:33 +01:00
Clifford Wolf
ae5032af84
Fixed bit-extending in $mux argument (use $bu0 instead of $pos)
2014-02-26 21:32:19 +01:00
Clifford Wolf
6bc94b7eb2
Don't blow up constants unneccessarily in Verilog frontend
2014-02-24 12:41:25 +01:00
Clifford Wolf
f8c9143b2b
Fixed bug in generation of undefs for $memwr MUXes
2014-02-22 17:08:00 +01:00
Clifford Wolf
4bd25edcd4
Cleanups in handling of read_verilog -defer and -icells
2014-02-20 19:12:32 +01:00
Clifford Wolf
02e6f2c5be
Added Verilog support for "`default_nettype none"
2014-02-17 14:28:52 +01:00
Clifford Wolf
7ac524e8e8
Improved support for constant functions
2014-02-16 13:16:38 +01:00
Clifford Wolf
5e39e6ece2
Correctly convert constants to RTLIL (fixed undef handling)
2014-02-15 15:42:10 +01:00
Clifford Wolf
45d2b6ffce
Be more conservative with new const-function code
2014-02-14 20:45:30 +01:00
Clifford Wolf
e8af3def7f
Added support for FOR loops in function calls in parameters
2014-02-14 20:33:22 +01:00
Clifford Wolf
534c1a5dd0
Created basic support for function calls in parameter values
2014-02-14 19:56:44 +01:00
Clifford Wolf
cd9e8741a7
Implemented read_verilog -defer
2014-02-13 13:59:13 +01:00
Clifford Wolf
f4f230d7cc
Fixed gcc compiler warnings with release build
2014-02-06 22:49:14 +01:00
Clifford Wolf
d267bcde4e
Fixed bug in sequential sat proofs and improved handling of asserts
2014-02-04 12:46:16 +01:00
Clifford Wolf
a6750b3753
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
2014-02-03 13:01:45 +01:00
Clifford Wolf
d06258f74f
Added constant size expression support of sized constants
2014-02-01 13:50:23 +01:00
Clifford Wolf
4df7e03ec9
Bugfix in name resolution with generate blocks
2014-01-30 15:01:28 +01:00
Clifford Wolf
375c4dddc1
Added read_verilog -icells option
2014-01-29 00:59:28 +01:00
Clifford Wolf
88fbdd4916
Fixed algorithmic complexity of AST simplification of long expressions
2014-01-20 20:25:20 +01:00
Clifford Wolf
1e67099b77
Added $assert cell
2014-01-19 14:03:40 +01:00
Clifford Wolf
9a1eb45c75
Added Verilog parser support for asserts
2014-01-19 04:18:22 +01:00
Clifford Wolf
a3d94bf888
Fixed typo in frontends/ast/simplify.cc
2014-01-12 21:04:42 +01:00
Clifford Wolf
fb2bf934dc
Added correct handling of $memwr priority
2014-01-03 00:22:17 +01:00
Clifford Wolf
364f277afb
Fixed a stupid access after delete bug
2013-12-29 20:18:22 +01:00
Clifford Wolf
369bf81a70
Added support for non-const === and !== (for miter circuits)
2013-12-27 14:20:15 +01:00
Clifford Wolf
ecc30255ba
Added proper === and !== support in constant expressions
2013-12-27 13:50:08 +01:00
Clifford Wolf
891e4b5b0d
Keep strings as strings in const ternary and concat
2013-12-05 13:26:17 +01:00
Clifford Wolf
e935bb6eda
Added const folding support for $signed and $unsigned
2013-12-05 13:09:41 +01:00
Clifford Wolf
5c39948ead
Added AstNode::mkconst_str API
2013-12-05 12:53:49 +01:00
Clifford Wolf
853538d78b
Fixed generate-for (and disabled double warning for auto-wire)
2013-12-04 21:33:00 +01:00
Clifford Wolf
3c220e0b32
Added support for $clog2 system function
2013-12-04 21:19:54 +01:00
Clifford Wolf
4a4a3fc337
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
Clifford Wolf
f4b46ed31e
Replaced signed_parameters API with CONST_FLAG_SIGNED
2013-12-04 14:24:44 +01:00
Clifford Wolf
93a70959f3
Replaced RTLIL::Const::str with generic decoder method
2013-12-04 14:14:05 +01:00
Clifford Wolf
507c63d112
Added support for local regs in named blocks
2013-12-04 09:10:16 +01:00
Clifford Wolf
10aa08dca1
Fixed temp net name generation in rtlil process generator for abbreviated name matching
2013-11-28 21:47:08 +01:00
Clifford Wolf
0e52f3fa01
Added "src" attribute to processes
2013-11-28 17:37:50 +01:00
Clifford Wolf
8dafecd34d
Added module->avail_parameters (for advanced techmap features)
2013-11-24 20:29:07 +01:00
Clifford Wolf
7d9a90396d
Added verilog frontend -ignore_redef option
2013-11-24 19:57:42 +01:00
Clifford Wolf
019b301541
Early wire/reg/parameter width calculation in ast/simplify
2013-11-24 19:40:23 +01:00
Clifford Wolf
f71e27dbf1
Remove auto_wire framework (smarter than the verilog standard)
2013-11-24 17:29:11 +01:00
Clifford Wolf
609caa23b5
Implemented correct handling of signed module parameters
2013-11-24 17:17:21 +01:00
Clifford Wolf
295e352ba6
Renamed "placeholder" to "blackbox"
2013-11-22 15:01:12 +01:00
Clifford Wolf
95c94a02fc
Fixed async proc detection in mem2reg
2013-11-21 21:26:56 +01:00
Clifford Wolf
09471846c5
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
Clifford Wolf
65ad556f3d
Another name resolution bugfix for generate blocks
2013-11-20 13:57:40 +01:00
Clifford Wolf
c4c299eb5a
Do not allow memory bit select on the left side of an assignment
2013-11-20 12:18:46 +01:00
Clifford Wolf
ac2be2d892
Fixed name resolution of local tasks and functions in generate block
2013-11-20 11:05:58 +01:00
Clifford Wolf
19dba2561e
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
Clifford Wolf
4f2edcf2f9
Fixed two bugs in mem2reg functionality in AST frontend
2013-11-18 19:55:12 +01:00
Clifford Wolf
79910a5547
Added dumping of attributes in AST frontend
2013-11-18 19:54:36 +01:00
Clifford Wolf
2a25e3bca3
Fixed parsing of default cases when not last case
2013-11-18 16:10:50 +01:00
Clifford Wolf
de03184150
Fixed mem2reg for reg usage outside always block
2013-11-18 12:35:41 +01:00
Clifford Wolf
e5b974fa2a
Cleanups and bugfixes in response to new internal cell checker
2013-11-11 00:39:45 +01:00
Clifford Wolf
378cc509cd
Call internal checker more often
2013-11-10 23:24:21 +01:00
Clifford Wolf
259cc1391e
More undef-propagation related fixes
2013-11-08 11:40:36 +01:00
Clifford Wolf
9f49d538e1
Fixed handling of different signedness in power operands
2013-11-08 11:06:11 +01:00
Clifford Wolf
4abc8e695a
Implemented const folding of ternary op with undef select
2013-11-08 04:44:09 +01:00
Clifford Wolf
fc6dc0d7b8
Fixed handling of power operator
2013-11-07 22:20:00 +01:00
Clifford Wolf
d7cb62ac96
Fixed more extend vs. extend_u0 issues
2013-11-07 19:20:20 +01:00
Clifford Wolf
02f4f89fdb
Disabled const folding of ternary op when select is undef
2013-11-07 18:18:16 +01:00
Clifford Wolf
947bd9b96b
Renamed extend_un0() to extend_u0() and use it in genrtlil
2013-11-07 18:17:10 +01:00
Clifford Wolf
ed4bcd52e5
Fixed sign handling in constants
2013-11-07 14:53:10 +01:00
Clifford Wolf
83a8b8b5ca
Fixed const folding in corner cases with parameters
2013-11-07 14:08:53 +01:00
Clifford Wolf
b52bf379b9
Fixed width detection for replicate operator
2013-11-07 12:43:04 +01:00
Clifford Wolf
536621a98b
Fixed at_zero evaluation of dynamic ranges
2013-11-07 11:25:19 +01:00
Clifford Wolf
f050c40519
Various fixes for correct parameter support
2013-11-07 10:02:11 +01:00
Clifford Wolf
160adccca2
Fixed the fix for propagation of width hints for $signed() and $unsigned()
2013-11-07 03:01:28 +01:00
Clifford Wolf
7fe13faefa
Fixed propagation of width hints for $signed() and $unsigned()
2013-11-06 22:41:21 +01:00
Clifford Wolf
baeca48a24
Additional fixes for undef propagation in concat and replicate ops
2013-11-06 21:16:54 +01:00
Clifford Wolf
6fcbc79b5c
Improved width extension with regard to undef propagation
2013-11-06 21:05:11 +01:00
Clifford Wolf
f2786df146
Another fix for early width and sign detection in ast simplifier
2013-11-04 21:29:36 +01:00
Clifford Wolf
d38c67f53d
Fixed const folding of ternary operator
2013-11-04 16:46:14 +01:00
Clifford Wolf
8d226da694
Use proper bit width ans sign extension for const folding
2013-11-04 15:37:09 +01:00
Clifford Wolf
1325514d33
Fixes for early width and sign detection in ast simplifier
2013-11-04 08:28:13 +01:00
Clifford Wolf
472117d532
further improved early width and sign detection in ast simplifier
2013-11-04 06:04:42 +01:00
Clifford Wolf
d2b083f5cb
Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT
2013-11-03 18:56:45 +01:00
Clifford Wolf
ada80545fa
Behavior should be identical now to rev. 0b4a64ac6a
(next: testing before constfold fixes)
2013-11-02 21:13:01 +01:00
Clifford Wolf
943329c1dc
Various ast changes for early expression width detection (prep for constfold fixes)
2013-11-02 13:00:17 +01:00
Clifford Wolf
23cf23418c
Fixed handling of boolean attributes (frontends)
2013-10-24 11:20:13 +02:00
Johann Glaser
6c4cbc03c2
Added support for notif0/notif1 primitives
2013-08-20 11:23:59 +02:00
Clifford Wolf
0003743432
Fixed width and sign detection for ** operator
2013-08-19 20:58:01 +02:00
Clifford Wolf
8656b1c08f
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
Clifford Wolf
4214561890
Improved ast dumping (ast/verilog frontend)
2013-08-19 19:49:14 +02:00
Clifford Wolf
759852914d
Added support for "2**n" shifter encoding
2013-08-12 14:47:50 +02:00
Clifford Wolf
c8763301b4
Added $div and $mod technology mapping
2013-08-09 17:09:24 +02:00
Clifford Wolf
0f38008ed3
Added "design" command (-reset, -save, -load)
2013-07-27 14:27:51 +02:00
Clifford Wolf
3650fd7fbe
More fixes in ternary op sign handling
2013-07-12 13:13:04 +02:00
Clifford Wolf
ded769c98c
Fixed sign handling in ternary operator
2013-07-12 01:15:37 +02:00
Clifford Wolf
b380c8c790
Another vloghammer related bugfix
2013-07-11 19:24:59 +02:00
Clifford Wolf
ed62fcdbe2
Fixed sign propagation in bit-wise operators
2013-07-09 23:53:55 +02:00
Clifford Wolf
5dab327b30
More fixes in ast expression sign/width handling
2013-07-09 23:41:43 +02:00
Clifford Wolf
00a6c1d9a5
Major redesign of expr width/sign detecion (verilog/ast frontend)
2013-07-09 14:31:57 +02:00
Clifford Wolf
e8da3ea7b6
Fixed another bug found using vloghammer
2013-07-07 16:49:30 +02:00
Clifford Wolf
eff68560a2
Fixed AST_CONSTANT node generation
2013-07-07 15:40:26 +02:00
Clifford Wolf
56432a920f
Added defparam support to Verilog/AST frontend
2013-07-04 14:12:33 +02:00
Clifford Wolf
0c6ffc4c65
More fixes for bugs found using xsthammer
2013-06-13 11:18:45 +02:00
Clifford Wolf
a5c30183b5
Sign-extension related fixes in SatGen and AST frontend
2013-06-10 17:10:06 +02:00
Clifford Wolf
59dd02baa2
Fixes and improvements in AST const folding
2013-06-10 13:56:03 +02:00
Clifford Wolf
db98a18edb
Enabled AST/Verilog front-end optimizations per default
2013-06-10 13:19:04 +02:00
Clifford Wolf
ed0e2f7a6f
Added log_assert() api
2013-05-24 14:38:36 +02:00
Clifford Wolf
c5ee2b306a
Merge branch 'bugfix'
2013-05-16 16:44:45 +02:00
Clifford Wolf
6cc8e848b6
Fixed synthesis of functions in latched blocks
2013-05-16 16:44:06 +02:00
Clifford Wolf
8f2d90de4f
Fixed handling of positional module parameters
2013-04-26 14:40:25 +02:00
Clifford Wolf
453a29c9f6
Only use sha1 checksums for names of parametric modules when the verbose form is to long
2013-04-26 13:13:58 +02:00
Clifford Wolf
e0c408cb4a
Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
2013-04-13 21:19:10 +02:00
Clifford Wolf
f1a2fd966f
Now only use value from "initial" when no matching "always" block is found
2013-03-31 11:51:12 +02:00
Clifford Wolf
161565be10
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
2013-03-31 11:19:11 +02:00
Clifford Wolf
7bfc7b61a8
Implemented proper handling of stub placeholder modules
2013-03-28 09:20:10 +01:00
Clifford Wolf
7a99349de4
Improvements and bugfixes for generate blocks with local signals
2013-03-26 11:31:34 +01:00
Clifford Wolf
6a382f2aba
Fixed handling of unconditional generate blocks
2013-03-26 09:44:54 +01:00
Clifford Wolf
227520f94d
Added nosync attribute and some async reset related fixes
2013-03-25 17:13:14 +01:00
Clifford Wolf
df9753d398
Added mem2reg option to verilog frontend
2013-03-24 11:13:32 +01:00
Clifford Wolf
3a5244e913
Another fix in mem2reg ast simplify logic
2013-03-24 10:42:08 +01:00
Clifford Wolf
bb3357c027
Improved mem2reg handling in ast simplifier
2013-03-24 09:27:01 +01:00
Clifford Wolf
e45d1c8865
Tiny fixes to verilog parser
2013-03-23 18:54:31 +01:00
Clifford Wolf
a321a5c412
Moved stand-alone libs to libs/ directory and added libs/subcircuit
2013-02-27 09:32:19 +01:00
Clifford Wolf
4f0c2862a0
Added support for verilog genblock[index].member syntax
2013-02-26 13:18:22 +01:00
Clifford Wolf
7764d0ba1d
initial import
2013-01-05 11:13:26 +01:00