Commit Graph

797 Commits

Author SHA1 Message Date
tangxifan f102e84497 [Tool] Add bitstream setting file to openfpga library 2021-02-01 17:43:46 -07:00
tangxifan 4b77a3a574 [Tool] Now activity file is not a manadatory input of openfpga tools 2021-01-29 11:33:40 -07:00
tangxifan d9fda31a9f [Tool] Add --version to openfpga shell option and a command to openfpga shell 2021-01-27 16:03:46 -07:00
tangxifan fd0e73a9bb [Tool] Enhance return code for openfpga shell 2021-01-24 14:48:27 -07:00
tangxifan 8cac3291cb [Tool] Add batch mode to openfpga shell execution 2021-01-24 14:33:58 -07:00
ganeshgore d502410b40
Merge pull request #179 from lnis-uofu/unused_gpout_patch
Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
2021-01-23 18:27:54 -07:00
tangxifan 4cc8b08a6c [Tool] Add openfpga version display 2021-01-23 16:38:00 -07:00
tangxifan d2defebee9 [Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches 2021-01-22 16:42:13 -07:00
tangxifan 3f80a26172 [Tool] Bug fix for combinational benchmarks in pre-config testbench generation 2021-01-19 18:22:50 -07:00
tangxifan 75b99b78e9 [Tool] Now testbench generator consider pin constraints in generating clock sources for benchmarks 2021-01-19 17:38:51 -07:00
tangxifan da200658c1 [Tool] Now autocheck top testbench consider pin constraints to generate operating clock sources for benchmarks 2021-01-19 17:29:59 -07:00
tangxifan 0670c2de59 [Tool] Deploy pin constraints to preconfig Verilog module generation 2021-01-19 16:56:30 -07:00
tangxifan 8c311b8282 [Tool] Bug fix in repacker for considering design constraints 2021-01-17 12:26:14 -07:00
tangxifan 2efe513122 [Tool] Now repack consider design constraints; test pending 2021-01-16 21:57:17 -07:00
tangxifan bb8e7e25c2 [Tool] Start deploying design constraints in repack engine 2021-01-16 21:27:12 -07:00
tangxifan fa67517349 [Tool] Add repack design constraints to openfpga command 'repack' 2021-01-16 18:49:34 -07:00
tangxifan ad7a54db1b [Tool] Add repack dc library to compilation 2021-01-16 17:20:59 -07:00
tangxifan 87b2c1f3b8 [Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation 2021-01-15 12:01:53 -07:00
tangxifan 852f5bb72e [Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers 2021-01-14 15:38:24 -07:00
tangxifan 9cc9e45b4b [Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated 2021-01-13 15:13:19 -07:00
tangxifan c0da6b900a [Tool] Bug fix in creating multi-bit clock port connections 2021-01-12 18:38:00 -07:00
tangxifan 65b2fe3ab7 [Tool] Bug fix in the global tile connection by considering all the subtiles 2021-01-10 11:52:38 -07:00
tangxifan 9a441fa5cc [Tool] Upgrade openfpga to support extended global tile port definition 2021-01-09 18:47:12 -07:00
tangxifan cde26597ed [Tool] Bug fix in scan chain builder calling 2021-01-04 18:45:47 -07:00
tangxifan 804b721a19 [Tool] Bug fix in the configuration chain connection builder 2021-01-04 17:41:29 -07:00
tangxifan bfd305b5a5 [Tool] Patch the bug in finding data output ports for CCFF 2021-01-04 17:22:30 -07:00
tangxifan cc91a0aebd [Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder 2021-01-04 17:14:26 -07:00
tangxifan d11a3d9fef [Tool] Avoid outputting signal initialization codes because they are bulky 2020-12-06 14:29:16 -07:00
tangxifan cb2bd2e31c [Tool] Remove register ports for mini local encoders (1-bit data out) 2020-12-06 14:21:54 -07:00
tangxifan 6bdfcb0147 [Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming 2020-12-05 12:44:09 -07:00
tangxifan 6f18688f0e [Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module 2020-12-05 10:53:01 -07:00
tangxifan 0da92ad888 [Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules 2020-12-04 22:16:51 -07:00
tangxifan 5be9e9b736 [Tool] Adapted tools to support I/O in center grid 2020-12-04 18:50:13 -07:00
tangxifan 73aaa261d8 [Tool] Relax the IO restriction in pb_pin post-routing packing fix-up 2020-12-04 17:55:25 -07:00
tangxifan 4aa6264b1c [Tool] Rework simulation time period to be sync with actual stimuli 2020-12-02 22:58:13 -07:00
tangxifan b661c39b04 [Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches 2020-12-02 19:36:36 -07:00
tangxifan 3a708cff21 [Tool] Bug fix to enable nature fracturable LUT design 2020-11-25 23:01:18 -07:00
tangxifan c82f01b3ab [Tool] Use conditional operator in signal initialization to eliminate all the warning messages 2020-11-23 15:50:23 -07:00
tangxifan e644545f21 [Doc] Remove signal initialization for select ports of MUXes and Pass-gates; Use urandom to generate just-fit random vectors 2020-11-23 15:02:06 -07:00
tangxifan 3b2a4c5387 [Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists 2020-11-22 20:25:03 -07:00
tangxifan 57a24570f5 [Tool] Move icarus and signal initialization options to testbench generator 2020-11-22 16:01:31 -07:00
tangxifan 3f91b8433e [Tool] Change the i/o numbering to the clockwise sequence 2020-11-13 15:00:25 -07:00
tangxifan 088198c861 [Tool] enhance error checking in fabric key parser 2020-11-13 10:56:00 -07:00
tangxifan 372fb261fd [Tool] Extend the support on global tile port for I/O tiles 2020-11-11 15:09:40 -07:00
tangxifan e627b6dd5d [Tool] Enhance port attribute checks in tile annotation data structure 2020-11-11 13:41:05 -07:00
tangxifan 9cbc374b33 [Tool] Add check codes for tile annotation 2020-11-11 12:03:13 -07:00
tangxifan 81e56d45d6 [Tool] Update FPGA-SDC to use the new data structure for global ports 2020-11-10 21:17:17 -07:00
tangxifan c61ec5a8b8 [Tool] Bug fix for defining global ports from tiles 2020-11-10 20:31:14 -07:00
tangxifan dcb50e4f19 [Tool] Use use standard data structure to store global port information 2020-11-10 19:07:28 -07:00
tangxifan cbb1545ee3 [Tool] Add connection builder for tile global ports to top-level module 2020-11-10 16:59:00 -07:00
tangxifan 5fe9c27600 [Tool] Remove redundant assertation 2020-11-09 09:42:39 -07:00
tangxifan ba0120bd76 [Tool] Remove the limitation on requiring Qb ports for CCFF 2020-11-06 11:10:04 -07:00
tangxifan 9b0617ffe6 [Tool] Bug fix for mappable I/O support 2020-11-04 20:45:51 -07:00
tangxifan 37c10f0cb5 [Tool] Add mappable I/O support and enhance I/O support 2020-11-04 20:21:49 -07:00
tangxifan 4a2874b2bc [Tool] Refactor the codes for walking through io blocks 2020-11-03 13:21:50 -07:00
tangxifan 1e47203c7c [Tool] Auto-generated gate Verilog netlist should not contain any signal initalization 2020-11-02 18:35:26 -07:00
tangxifan e4d974c5c8 [Tool] Split io location mapping builder from fabric builder 2020-11-02 18:27:34 -07:00
tangxifan 1fd899ecee [Tool] Relex logic block checking codes to skip zero-capacity nodes 2020-11-02 16:57:19 -07:00
tangxifan 6b25cf720d [Tool] Comment on the memory efficiency on fabric bitstream address storage 2020-10-30 22:09:48 -06:00
tangxifan b78f8bec16 [Tool] Bug fixed for multi-region configuration frame 2020-10-30 21:19:20 -06:00
tangxifan 5bcd559851 [Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification 2020-10-30 17:29:04 -06:00
tangxifan 0d77916041 [Tool] Support multi-region frame-based configuration protocol 2020-10-30 10:43:11 -06:00
tangxifan 8ef6ae32fb [Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol 2020-10-29 17:35:55 -06:00
tangxifan 987eccf586 [Tool] Bug fix in multi-region memory bank; Basic test passed 2020-10-29 16:26:45 -06:00
tangxifan 448e88645a [Tool] Support multiple memory banks in top-level module 2020-10-29 12:42:03 -06:00
tangxifan bd49ea95d4 [Tool] Add function to comput configuration bits by region 2020-10-28 12:37:09 -06:00
tangxifan 446f982410 [Tool] Add warning when number of regions defined in fabric key is different than architecture 2020-10-28 11:43:05 -06:00
tangxifan 1ef0898f41 [Tool] Now users can specify a different fabric netlist when generating Verilog testbench 2020-10-12 12:31:51 -06:00
tangxifan 721bcce373 [Tool] Change analysis SDC file name to track netlist name 2020-10-10 17:43:35 -06:00
tangxifan e0d7bcfa11 [Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols 2020-09-29 12:49:32 -06:00
tangxifan e988e35f81 [Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches 2020-09-29 12:22:10 -06:00
tangxifan 180d72f3e5 [Tool] Add regions to fabric bitstream 2020-09-28 21:04:08 -06:00
tangxifan e179a58b15 [OpenFPGA Tool] Bug fix for long runtime 2020-09-28 20:42:18 -06:00
tangxifan 47f3c79927 [OpenFPGA Tool] Bug fix in module manager due to configurable regions 2020-09-28 19:08:19 -06:00
tangxifan f93d46a870 [OpenFPGA Tool] Add multiple configuration chain support in top module builder 2020-09-28 19:03:19 -06:00
tangxifan 552dddffd0 [OpenFPGA Tool] Support configurable regions in module manager 2020-09-28 18:13:07 -06:00
tangxifan 052b8b71c7 [OpenFPGA Tool] Bug fix in the XML parser for fabric regions 2020-09-27 20:54:58 -06:00
tangxifan 154f23b108 [OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches 2020-09-26 11:54:06 -06:00
tangxifan 1b4e449179 [OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol 2020-09-25 21:05:20 -06:00
tangxifan 6bea712db0 [OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name 2020-09-25 14:54:51 -06:00
tangxifan 8468f25b23 [OpenFPGA Tool] Bug fix in the smart fast configuration strategy 2020-09-24 16:31:55 -06:00
tangxifan 46b12611a9 [OpenFPGA Tool] Bug fix for smart fast configuration 2020-09-23 22:04:07 -06:00
tangxifan 154c9045f6 [OpoenFPGA Tool] Bug fix for smart fast configuration 2020-09-23 21:38:42 -06:00
tangxifan c2c37d7555 [OpenFPGA Tool] Add more print-out for smart fast configuration 2020-09-23 21:34:23 -06:00
tangxifan a3abf81afe [OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration 2020-09-23 21:25:06 -06:00
tangxifan 064678fe32 [OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol 2020-09-23 20:27:52 -06:00
tangxifan ad881ea4dc [OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank 2020-09-23 18:59:25 -06:00
tangxifan 9adeb550dc [OpenFPGA Tool] Bug fix in fabric builder 2020-09-23 18:28:00 -06:00
tangxifan 6480b06a2d [OpenFPGA tool] Remove out-of-data test blif, architecture and scripts 2020-09-23 11:01:53 -06:00
tangxifan 26f1a5d9ec [OpenFPGA Tool] Bug fix for repacking no local routing architecture 2020-09-21 22:22:03 -06:00
tangxifan c6ac02d210 [FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation 2020-09-20 15:21:33 -06:00
tangxifan 544c44fe46 [FPGA-SPICE] Add VDD and VSS port to module definition 2020-09-20 14:58:15 -06:00
tangxifan 460fef5807 [FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions 2020-09-20 12:58:55 -06:00
tangxifan 222bc86cbf [FPGA-SPICE] Add auxiliary SPICE netlist writer 2020-09-20 12:53:28 -06:00
tangxifan 06c0073a3e [FPGA-SPICE] Add SPICE writer for fpga top module 2020-09-20 12:43:48 -06:00
tangxifan 1dfb3e06cc [FPGA-SPICE] add SPICE writer for logic blocks 2020-09-20 12:38:24 -06:00
tangxifan 5e78e91fdf [FPGA-SPICE] Add SPICE writer for routing blocks 2020-09-20 12:27:48 -06:00
tangxifan 0f25b52907 [FPGA-Verilog] code format fix 2020-09-20 12:18:22 -06:00
tangxifan 2fae311c8e [FPGA-SPICE] Add SPICE writer for memories 2020-09-20 12:14:34 -06:00
tangxifan f284f6f8d0 [OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs 2020-09-20 12:03:10 -06:00
tangxifan 6801d260e9 [FPGA-SPICE] Add SPICE writer for LUT 2020-09-20 11:58:11 -06:00
tangxifan 0f9fce92b2 [FPGA-SPICE] Add SPICE writer for routing multiplexers 2020-09-20 11:49:02 -06:00
tangxifan c7e3d97d1b [FPGA-SPICE] Add supply voltage generator 2020-09-20 11:19:06 -06:00
tangxifan 15df9b3893 [FPGA-SPICE] Add SPICE subcircuit writer 2020-09-19 23:01:44 -06:00
tangxifan 82e137cbe4 [FPGA-SPICE] Add wire module SPICE writer 2020-09-19 19:31:16 -06:00
tangxifan 1b2762386c [FPGA-SPICE] Bug fix for essential gate netlist writing 2020-09-19 16:52:30 -06:00
tangxifan 26a0a769ea [FPGA-SPICE] Split essential gate SPICE netlists into separated files 2020-09-19 16:45:26 -06:00
tangxifan e102e30d19 [FPGA-SPICE] Add support for AND/OR logic gate 2020-09-19 16:20:21 -06:00
tangxifan 482d90018f [FPGA-SPICE] Create generic PMOS/NMOS instanciation function 2020-09-19 15:33:28 -06:00
tangxifan 3262ceb276 [FPGA-SPICE] Bug fix for pass gate transistor sizing 2020-09-19 15:24:40 -06:00
tangxifan aa078f079c [FPGA-SPICE] Restructured SPICE netlist writers for atom circuits to avoid large cpp files 2020-09-19 15:20:19 -06:00
tangxifan f5dadca884 [FPGA-SPICE] Optimize the print-out of SPICE ports 2020-09-19 15:07:48 -06:00
tangxifan 51d423e4db [FPGA-SPICE] Add pass-gate SPICE netlist writer 2020-09-19 14:59:00 -06:00
tangxifan 9cfb2f52ef [OpenFPGA code] bug fix for fully equivalent outputs of pb_type 2020-09-16 19:26:46 -06:00
tangxifan fc6bfdc7a2 [OpenFPGA Code] Patch syntax compatibility for older gcc 2020-09-14 18:55:21 -06:00
tangxifan 04070fd4ca [Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker 2020-09-02 22:16:10 -06:00
tangxifan 3eea12ceae added a new XML syntax: initial offset for physical mode pin mapping 2020-08-19 14:43:44 -06:00
tangxifan f631245b2b bug fix and enriched debugging info print out 2020-08-19 13:41:04 -06:00
tangxifan 79b6ff3cb0 relax checking for device annotation as we support multi-port during physical mode pin mapping 2020-08-19 12:44:51 -06:00
tangxifan 2712c354a9 now physical pb_port binding support multiple ports 2020-08-18 12:38:56 -06:00
tangxifan 5d83abb2cf bug fix in read architecture bitstream and regression tests 2020-07-27 19:37:05 -06:00
tangxifan 9a7364c6e6 bug fix in fabric bitstream XML syntax 2020-07-27 19:22:36 -06:00
tangxifan 35af0dd676 streamline fabric bitstream file format 2020-07-27 16:34:43 -06:00
tangxifan 8dd26094b8 add root node to fabric bitstream XML file format 2020-07-27 15:31:08 -06:00
tangxifan 6592db3dfe bug fix in calling the wrong function of write_fabric_bitstream 2020-07-27 14:32:58 -06:00
tangxifan d68e77f322 Split the writer of build_fabric_bitstream to a separated command so that users will output multiple files in different formats 2020-07-27 14:16:33 -06:00
tangxifan e09eddab43 add width syntex to the fabric bitstream file format 2020-07-27 13:54:23 -06:00
tangxifan 80e982fb39 minor file format fix in fabric bitstream XML 2020-07-26 21:35:48 -06:00
tangxifan b3ad04fd1e minor file format fix in fabric bitstream XML 2020-07-26 21:33:47 -06:00
tangxifan 861e346830 minor bug fix in fabric bitstream XML writer 2020-07-26 21:31:08 -06:00
tangxifan 5fb7d9fbdb bug fix in fabric bitstream file format writer 2020-07-26 21:28:45 -06:00
tangxifan 92d2d2d849 add fabric bitstream XML writer 2020-07-26 21:00:57 -06:00
tangxifan a3d22c56e3 bug fix in FPGA-SPICE 2020-07-24 19:51:32 -06:00
tangxifan fd3e947c6d update FPGA_SPICE to support max width for transistors and multi-bin 2020-07-24 17:52:31 -06:00
tangxifan 73e2b857a3 add buffer support to FPGA-SPICE 2020-07-24 15:54:18 -06:00
tangxifan 2603836111 split logical tile netlists to keep good Verilog hierarchy 2020-07-24 12:53:21 -06:00
tangxifan be5966475e formulate file name, module name and instance name to be consistent 2020-07-24 12:23:27 -06:00
tangxifan 22159531c5 bug fix in power gating support of FPGA-Verilog 2020-07-22 20:21:38 -06:00
tangxifan a4a38f8156 support multi-bit power gate ports in FPGA-SPICE 2020-07-22 20:04:39 -06:00
tangxifan f573fa3ee0 move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
2020-07-22 18:47:12 -06:00
tangxifan 97cca72590 add spice support on power gated inverters 2020-07-22 18:21:11 -06:00
tangxifan b5fd6aa859 add inverter subckt writer to FPGA-SPICE 2020-07-17 13:01:08 -06:00
tangxifan eb070694b5 fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture 2020-07-15 17:52:41 -06:00
tangxifan 66a50742fc use configuration chain in the k4k4 test case to speed up CI 2020-07-15 11:56:11 -06:00
tangxifan 3f14fe62c7 add fast configuration support for configuration chain protocol 2020-07-15 11:44:23 -06:00
tangxifan 1b55dfb441 hotfix on treating the dangling ports in pb_graph for analysis SDC generator 2020-07-09 23:28:42 -06:00
tangxifan 62fd0947f5 using a unified string to replace multi net names to save memory of bitstream database 2020-07-08 16:28:20 -06:00
tangxifan 66e5e141a1 improve fabric key loader to reduce runtime 2020-07-07 10:19:34 -06:00
tangxifan 824b56f14c fabric key can now accept instance name only; decoders are no longer part of the key 2020-07-06 16:42:33 -06:00
tangxifan 462fc0d04e add spice transistor wrapper writer 2020-07-05 14:50:29 -06:00
tangxifan b38ee0e8be add spice writer functions 2020-07-05 13:58:05 -06:00
tangxifan 81171a8f97 start transplanting FPGA-SPICE 2020-07-05 12:10:12 -06:00
tangxifan 1ad6e8292a move constants from verilog domain to common so that FPGA-SPICE can share 2020-07-05 11:39:46 -06:00
tangxifan 7c2a0a6ad2 streamline fabric verilog options 2020-07-05 11:28:14 -06:00
tangxifan 83e26adf90 add module usage types for future FPGA-SPICE development 2020-07-04 22:33:54 -06:00
tangxifan 4f8260a7ba remove obselete codes and update regression tests 2020-07-04 17:31:34 -06:00
tangxifan 033c92c365 precisely reserve memory for child blocks in bitstream manager 2020-07-03 22:47:21 -06:00
tangxifan 46f038c829 bug fix in grid config block allocation 2020-07-03 20:46:04 -06:00
tangxifan f040fc78a9 now reserve blocks in bitstream manager can accurately capture the size 2020-07-03 20:06:12 -06:00
tangxifan 8067a13346 bug fix for memory bank due to encoding bl/wl addresses in fabric bitstream 2020-07-03 15:56:20 -06:00
tangxifan 2a9377b3f4 use encoded address in storage of fabric bitstream to save memory 2020-07-03 15:12:29 -06:00
tangxifan 1f38e17111 bug fix for naming conflicts in mux local encoder and architecture decoders 2020-07-03 14:12:13 -06:00
tangxifan 70d9678578 reserve child block in bistream manager 2020-07-03 14:04:10 -06:00
tangxifan 2783fda344 use index range instead of vector for block bitstream 2020-07-03 11:42:38 -06:00
tangxifan 6ea857ae6c use fast method to inquire number of bits and blocks in bitstream databases 2020-07-03 10:55:25 -06:00
tangxifan 7ca1a5bdc1 Fabric bitstream now allocates vectors in conditions for memory efficiency 2020-07-03 10:17:03 -06:00
tangxifan 8a45e48a1c minor fix 2020-07-02 22:27:48 -06:00
tangxifan 246b4d5ac6 reserve block bits to save memory 2020-07-02 21:52:32 -06:00
tangxifan dee4be96af reserve all the input/output net storage in bitstream manager 2020-07-02 19:17:34 -06:00
tangxifan f97e3bfba6 add timer to openfpga shell 2020-07-02 18:02:33 -06:00
tangxifan 81c9fcb7c0 bug fix when optimizing the fabric bitstream data structure 2020-07-02 16:41:32 -06:00
tangxifan adee87569d enable fast bitstream building by creating a frame view of fabric 2020-07-02 16:25:36 -06:00
tangxifan 9608cefa86 remove id vector in fabric bitstream database and replace with more memory efficient implementation 2020-07-02 16:08:50 -06:00
tangxifan 9f19c36a89 use char in fabric bitstream to save memory footprint 2020-07-02 15:56:50 -06:00
tangxifan 405824081b reserve configuration blocks and bits in bitstream manager builder to be memory efficient 2020-07-02 15:28:52 -06:00
tangxifan b85af57971 optimizing fabric bitsteream memory footprint 2020-07-02 12:39:18 -06:00
tangxifan ac22ba28e4 add config protocol type information to simulation ini file 2020-07-02 12:26:59 -06:00
tangxifan 81ecfa3197 add comments to clarify how to select CB ports when connecting to SBs at the top level 2020-07-01 14:44:40 -06:00
tangxifan 0a3c746fb1 now split CB module bus ports into lower/upper parts 2020-07-01 14:37:13 -06:00
tangxifan cb2baed257 bug fix in simulation ini GPIO width 2020-07-01 13:39:12 -06:00
tangxifan b74dde919d add additional information in the simulation ini file for UVM 2020-07-01 13:07:39 -06:00
tangxifan e688ca1388 update fabric bitstream writer to support various configuration protocols 2020-07-01 11:54:28 -06:00
tangxifan 1015880d0e use easy-to-access net look up in switch block module builder 2020-06-30 18:15:41 -06:00
tangxifan 05187f8aa4 use typedef to short the module pin information 2020-06-30 18:07:22 -06:00
tangxifan 2e7684b746 adapt bus ports in connection block module builder 2020-06-30 17:50:53 -06:00
tangxifan 2ef083c49d adapt SB module builder to use bus ports 2020-06-30 16:02:40 -06:00
tangxifan f023652ac4 keep optimizing memory footprint of module manager by using net terminal storage 2020-06-30 14:18:05 -06:00
tangxifan f49cabeeda optimize memory efficiency for module net id storage 2020-06-30 11:33:06 -06:00
tangxifan 23bcad0678 use more robust net builder in inter tile connections 2020-06-30 10:49:17 -06:00
tangxifan 025d4a3599 use efficient net builder in top module connection builder 2020-06-29 23:28:26 -06:00
tangxifan e7d5736269 add profile time to top module builder for better spot on runtime/memory overhead sources 2020-06-29 23:17:03 -06:00
tangxifan 57e6c84252 add reserve net sources and sinks to module manager 2020-06-29 22:49:11 -06:00
tangxifan 66746f69da optimizing memory efficiency by reserving nets in module manager 2020-06-29 21:27:43 -06:00
tangxifan e9937954f2 optimizing the constant writing in Verilog for single bits 2020-06-29 12:29:25 -06:00
tangxifan 9d32a5b81f add alias name support for fabric key 2020-06-27 14:59:53 -06:00
tangxifan ebf5636e7b add verbose output to edge sorting for GSBs 2020-06-26 17:10:51 -06:00
tangxifan aded675633 rename files in fpga bitstream library to be consistent with conventions 2020-06-21 13:06:39 -06:00
tangxifan d526f08782 deploy bitstream reader in openfpga shell 2020-06-20 18:48:19 -06:00
tangxifan 675a59ecb8 Move fpga_bitstream to the libopenfpga library and add XML reader 2020-06-20 18:25:17 -06:00
tangxifan 5d79a3f69f critical bug fixed when annotating the routing results.
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
tangxifan 4f7e8020a8 minor fix on the format of arch bitstream writer 2020-06-17 00:08:28 -06:00
tangxifan b91c30191a add input and output net echo in arch bitstream database 2020-06-17 00:04:55 -06:00
tangxifan 19c0b57df6 ignore invalid nets when decoding bitstream 2020-06-16 22:26:36 -06:00
tangxifan 9d0e002532 echo path in architecture bitstream database 2020-06-16 21:29:45 -06:00
ganeshgore 559564c333 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2020-06-12 17:31:14 -06:00
tangxifan a5055e9d26 add support about loading external fabric key 2020-06-12 13:03:11 -06:00
tangxifan 9dbf536306 add shuffled configurable children support for top module 2020-06-12 11:16:53 -06:00
tangxifan cf9c3b0f44 add write fabric to test cases 2020-06-12 10:50:23 -06:00
tangxifan 3499b4d3e7 add fabric key writer for top-level module 2020-06-12 10:41:34 -06:00
tangxifan 278acee216 bug fix for 'build_fabric' command 2020-06-11 23:59:24 -06:00
tangxifan 9167b288b6 add options for fabric key 2020-06-11 21:50:46 -06:00
tangxifan 8a4ec85c39 add configurable children-related methods to module manager 2020-06-11 21:44:25 -06:00
tangxifan 58807bfcb3 remove simulation settings from openfpga arch data structure 2020-06-11 19:31:16 -06:00
tangxifan 96b58dfdbb use new simulation setting command in openfpga shell 2020-06-11 19:31:15 -06:00
tangxifan 4a2f6dfae2 add read/write simulation setting commands to openfpga shell 2020-06-11 19:31:15 -06:00
tangxifan 3c10af7f2b bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm 2020-06-11 19:31:14 -06:00
tangxifan 8267dad8ef add decoder support for Z signals 2020-06-11 19:31:14 -06:00
tangxifan 5368485bd6 keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level 2020-06-11 19:31:14 -06:00
tangxifan c85ccceac7 try bug fixing in memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan 0bee70bee6 finish memory bank configuration protocol support. 2020-06-11 19:31:13 -06:00
tangxifan e14c39e14c update Verilog full testbench generation to support memory bank configuration protocol 2020-06-11 19:31:13 -06:00
tangxifan 51e1559352 add fabric bitstream support for memory bank configuration protocol 2020-06-11 19:31:13 -06:00
tangxifan 0e16ee1030 add configuration bus nets for memory bank decoders at top module 2020-06-11 19:31:13 -06:00
tangxifan fa8dfc1fbd add configuration protocol ports to top module for memory bank organization 2020-06-11 19:31:13 -06:00
tangxifan ad7422359d deploy compact constant values in Verilog codes 2020-06-11 19:31:13 -06:00
tangxifan 8ec8ac4118 bug fixed in flatten memory organization. Passed verification 2020-06-11 19:31:12 -06:00
tangxifan b9aac3cbdf updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol 2020-06-11 19:31:12 -06:00
tangxifan fbe05963e0 add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol) 2020-06-11 19:31:12 -06:00
tangxifan d2d443a988 start developing memory bank and standalone configuration protocol 2020-06-11 19:31:12 -06:00
tangxifan 9e176b8d38 add fast configuration stats to log 2020-06-11 19:31:12 -06:00
tangxifan 8b3e79766c add fast configuration option to fpga_verilog to speed up full testbench simulation 2020-06-11 19:31:12 -06:00
tangxifan b5e5182f52 frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops 2020-06-11 19:31:11 -06:00
tangxifan 31c9a011dd keep bug fixing for arch decoders 2020-06-11 19:31:11 -06:00
tangxifan bdc9efb38f bug fix in top-level testbench for frame-based decoders 2020-06-11 19:31:11 -06:00
tangxifan 986956e474 bug fix for arch decoder Verilog codes. Now Modelsim compiles ok. 2020-06-11 19:31:11 -06:00
tangxifan 6a72c66eb8 bug fixed for frame-based configuration memory in top-level full testbench 2020-06-11 19:31:11 -06:00
tangxifan 8aa665b3b2 bug fix in the Verilog codes for frame decoders 2020-06-11 19:31:10 -06:00
tangxifan 8298bbff78 bug fixed in the fabric bitstream for frame-based configurable memories. 2020-06-11 19:31:10 -06:00
tangxifan bf9f62f0f7 keep bug fixing for frame-based configuration protocol. 2020-06-11 19:31:10 -06:00
tangxifan 65df309419 bug fixing for frame-based configuration protocol and rename some naming function to be generic 2020-06-11 19:31:10 -06:00
tangxifan ece651ade2 bug fixed in the configuration chian errrors 2020-06-11 19:31:10 -06:00
tangxifan cff5b5cfc1 break the configuration testbench. This commit is to spot which modification leads to the problem 2020-06-11 19:31:10 -06:00
tangxifan 85921dcc05 add fabric bitstream builder for frame-based configuration protocol 2020-06-11 19:31:10 -06:00
tangxifan 4a0e1cd908 add fabric bitstream data structure and deploy it to Verilog testbench generation 2020-06-11 19:31:10 -06:00
tangxifan 8c14cced84 start improve fabric bitstream database to support frame-based configuration protocol 2020-06-11 19:31:09 -06:00
tangxifan 5c5a044c68 add architecture decoder (for frame-based config memory) to Verilog writer 2020-06-11 19:31:09 -06:00
tangxifan c696e3d20f refine frame-based memory addition to compact the area 2020-06-11 19:31:09 -06:00
tangxifan ed2325ec9e add frame decoder build-up to top-level module 2020-06-11 19:31:09 -06:00
tangxifan 290dd1a8a6 add frame decoder builder to all the module graph builder except the top-level 2020-06-11 19:31:09 -06:00
tangxifan 8864920460 add frame-based memory module builder 2020-06-11 19:31:09 -06:00