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1710 Commits

Author SHA1 Message Date
Eddie Hung 29db96fa1f Revert "Vivado does not like zero width port connections" 
This reverts commit 895e2befa7.
 2019-09-23 19:52:54 -07:00
Eddie Hung 895e2befa7 Vivado does not like zero width port connections 2019-09-23 19:04:07 -07:00
Eddie Hung 67c2db3486 Remove (* techmap_autopurge *) from abc_unmap.v since no effect 2019-09-23 18:56:18 -07:00
Eddie Hung 23d90e0439 Add a xilinx_finalise pass 2019-09-23 18:56:02 -07:00
Eddie Hung 4401e5f142 Grammar 2019-09-20 14:24:31 -07:00
Eddie Hung ab46d9017b Fix signedness bug 2019-09-20 10:11:36 -07:00
Eddie Hung 289cf688b7 Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 2019-09-20 09:02:29 -07:00
Eddie Hung 829e4f5d2c Revert "Move mul2dsp before wreduce" 
This reverts commit e4f4f6a9d5.
 2019-09-20 08:56:16 -07:00
Eddie Hung e4f4f6a9d5 Move mul2dsp before wreduce 2019-09-20 08:41:40 -07:00
Eddie Hung 691686f92c Tidy up, fix undriven 2019-09-19 20:04:52 -07:00
Eddie Hung 1602516a8b $__ABC_REG to have WIDTH parameter 2019-09-19 19:37:45 -07:00
Eddie Hung e09f80479e Fix DSP48E1 timing by breaking P path if MREG or PREG 2019-09-19 18:59:28 -07:00
Eddie Hung 362a803779 Revert "Different approach to timing" 
This reverts commit 41256f48a5.
 2019-09-19 18:33:38 -07:00
Eddie Hung 41256f48a5 Different approach to timing 2019-09-19 18:33:29 -07:00
Eddie Hung 5ca25b0c59 Suppress $anyseq warnings 2019-09-19 16:27:14 -07:00
Eddie Hung 595fb611a5 Use (* techmap_autopurge *) to suppress techmap warnings 2019-09-19 15:58:01 -07:00
Eddie Hung c15a35db84 D is 25 bits not 24 bits wide 2019-09-19 15:55:49 -07:00
Eddie Hung b88f0f6450 Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp 2019-09-19 15:47:41 -07:00
Eddie Hung 95db2489bd synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 2019-09-19 14:58:06 -07:00
Eddie Hung 3b9b0fcd06 Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2 2019-09-19 14:57:38 -07:00
Marcin Kościelnicki 13fa873f11 Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00
Eddie Hung fd3b033903 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-18 12:23:22 -07:00
Eddie Hung 25e0f0c376 Fix copy-paste 2019-09-18 12:19:16 -07:00
Eddie Hung b77cf6ba48 Mis-spell 2019-09-18 11:12:46 -07:00
Eddie Hung e992dbf2c5 Add pattern detection support for DSP48E1 model, check against vendor 2019-09-18 10:45:04 -07:00
Eddie Hung 3ec28ec53a
Merge pull request #1379 from mmicko/sim_models 
Added simulation models for Efinix and Anlogic
 2019-09-18 10:04:27 -07:00
Miodrag Milanovic 3e9449cb0b make note that it is for latch mode 2019-09-18 17:48:16 +02:00
Miodrag Milanovic b0ca6de472 better lut handling 2019-09-18 17:45:19 +02:00
Miodrag Milanovic 8badd4d812 better handling of lut and begin/end add 2019-09-18 17:45:07 +02:00
Marcin Kościelnicki 09ac36da60 xilinx: Make blackbox library family-dependent. 
Fixes #1246.
 2019-09-15 13:37:24 +02:00
Miodrag Milanovic 3487b95224 Added simulation models for Efinix and Anlogic 2019-09-15 09:37:16 +02:00
Eddie Hung 681be20ca2 Add `undef DSP48E1_INST 2019-09-13 17:07:18 -07:00
Eddie Hung 61877e1370 Fix D -> P{,COUT} delay 2019-09-13 13:32:55 -07:00
Eddie Hung d0b202c58d Add no MULT no DPORT config 2019-09-13 12:05:14 -07:00
Eddie Hung 247a63f55d Add support for MULT and DPORT 2019-09-13 11:45:55 -07:00
Eddie Hung e235dd0785 Refine diagram 2019-09-13 09:34:40 -07:00
Eddie Hung 734034a872 Add an ASCII drawing 2019-09-12 18:13:46 -07:00
Eddie Hung c52863f147 Finish explanation 2019-09-12 18:01:49 -07:00
Eddie Hung aaeaab4ac0 Rename to techmap_guard 2019-09-12 17:45:02 -07:00
Eddie Hung 6bb8e6a726 Initial DSP48E1 box support 2019-09-12 17:11:01 -07:00
Eddie Hung 3a39073302 Set more ports explicitly 2019-09-12 17:10:43 -07:00
Eddie Hung 0ebbecf833 Missing space 2019-09-11 13:06:59 -07:00
Eddie Hung feb3fa65a3 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-11 00:01:31 -07:00
Eddie Hung 5c1271c51c Move "(skip if -nodsp)" message to label 2019-09-10 15:26:56 -07:00
Eddie Hung f2d030a70f Be sensitive to signedness 2019-09-10 15:14:55 -07:00
Eddie Hung 76eedee089 Really get rid of 'opt_expr -fine' by being explicit 2019-09-10 14:26:12 -07:00
Eddie Hung c460d10e60 Remove wreduce call 2019-09-10 14:17:35 -07:00
Eddie Hung f3a55d3f06 Add comment for why opt_expr is necessary 2019-09-10 14:11:56 -07:00
Eddie Hung 8514e7c32e Revert "Remove "opt_expr -fine" call" 
This reverts commit bfda921d03.
 2019-09-10 14:09:21 -07:00
Eddie Hung d3fb308181 Rename label to map_dsp 2019-09-10 13:18:10 -07:00
Eddie Hung bfda921d03 Remove "opt_expr -fine" call 2019-09-10 13:17:47 -07:00
Eddie Hung a7e6032287 Set USE_MULT and USE_SIMD 2019-09-09 20:56:29 -07:00
Marcin Kościelnicki fda94311ee synth_xilinx: Support init values on Spartan 6 flip-flops properly. 2019-09-07 16:30:43 +02:00
Pepijn de Vos 2fb20f184a Revert "add MUX support" 
It turns out that they make everything worse and they don't PnR.

This reverts commit 3eff2271d0.
 2019-09-06 11:28:17 +02:00
Pepijn de Vos 96efa63f16 fix BRAM width and init 2019-09-06 10:55:04 +02:00
Pepijn de Vos 1b9f7f49b5 add more DFF to sim lib 2019-09-06 09:01:07 +02:00
Eddie Hung e742478e1d Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-05 13:01:27 -07:00
Pepijn de Vos 5168b6ffa4 WIP aditional DFF primitives 2019-09-05 19:12:47 +02:00
Pepijn de Vos 47374a495d support bram initialisation 2019-09-05 17:25:51 +02:00
Pepijn de Vos 7a43be5e43 use singleton ground and vcc nets, apparently this makes pnr happier 2019-09-05 16:38:47 +02:00
Pepijn de Vos 3eff2271d0 add MUX support 2019-09-05 13:36:41 +02:00
Eddie Hung aa1491add3 Resolve TODO with pin assignments for SRL* 2019-09-04 15:47:36 -07:00
Eddie Hung 3732d421c5 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-04 12:37:42 -07:00
Pepijn de Vos ae93c034ad set undriven pads to zero 2019-09-04 16:29:40 +02:00
Pepijn de Vos a6d81a8d14 Merge remote-tracking branch 'diego/gowin' 2019-09-04 11:20:05 +02:00
Pepijn de Vos ec56438cf2 gowin: add splitnets to appease the PnR 2019-09-04 10:33:47 +02:00
Diego H 5aa8d7ceeb Updating gowin 2019-09-02 17:43:27 -05:00
Eddie Hung 3459d28349 Add comments 2019-09-02 12:22:15 -07:00
Eddie Hung 696f854801 Rename box 2019-09-02 12:15:11 -07:00
Eddie Hung 2fa3857963 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-09-02 12:13:44 -07:00
Miodrag Milanovic a3c16a0565 Fix TRELLIS_FF simulation model 2019-08-31 11:12:06 +02:00
David Shah 90b44113d8 ecp5_gsr: Fix typo 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-31 09:58:46 +01:00
Eddie Hung f33abd4eab Remove trailing space 2019-08-30 16:44:11 -07:00
Eddie Hung 723815b384 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-30 13:26:19 -07:00
Eddie Hung f0fef90e9d Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-30 10:30:46 -07:00
Eddie Hung 295c18bd6b Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-30 09:50:20 -07:00
Eddie Hung 6e475484b2 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-30 09:37:32 -07:00
David Shah 6919c0f9b0 Merge branch 'master' into xc7dsp 2019-08-30 13:57:15 +01:00
David Shah 91b46ed816 ecp5: Add simulation equivalence check for Diamond FF implementations 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-30 13:27:36 +01:00
whitequark d9c621f9d1 ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives. 2019-08-30 10:05:09 +00:00
whitequark 1e6b60d563 ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives. 2019-08-30 09:56:19 +00:00
whitequark 6fa8ce93e6 ecp5: add missing FD primitives. 2019-08-30 09:54:48 +00:00
whitequark 7e2825a2a4 ecp5: fix CEMUX on IFS/OFS primitives. 2019-08-30 09:42:33 +00:00
Eddie Hung 25b1670a84 Rename boxes too 2019-08-29 07:03:32 -07:00
Eddie Hung c4e5310823 Use a dummy box file if none specified 2019-08-28 20:58:55 -07:00
Eddie Hung e8e3830868 Comment out SB_MAC16 arrival time for now, need to handle all its modes 2019-08-28 19:09:29 -07:00
Eddie Hung 309684af16 Add arrival for SB_MAC16.O 2019-08-28 19:07:28 -07:00
Eddie Hung efa4ee5c0e Add arrival times for U 2019-08-28 19:03:29 -07:00
Eddie Hung 4bda902f1b LX -> LP 2019-08-28 19:02:54 -07:00
Eddie Hung 0f4e9f6bc5 Round not floor 2019-08-28 18:57:34 -07:00
Eddie Hung 927f1e3754 Add LP timings 2019-08-28 18:56:25 -07:00
Eddie Hung e3709e5ee6 LX -> LP 2019-08-28 18:51:14 -07:00
Eddie Hung a4f641f230 Do not overwrite LUT param 2019-08-28 18:46:53 -07:00
Eddie Hung c0b99ed0e8 Do not overwrite LUT param 2019-08-28 18:45:09 -07:00
Eddie Hung 070f3ac561 Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival 2019-08-28 17:29:25 -07:00
Eddie Hung d46d38e4d5 Trailing comma 2019-08-28 17:25:54 -07:00
Eddie Hung f5b4bc847c Adapt to $__ICE40_CARRY_WRAPPER 2019-08-28 17:25:05 -07:00
Eddie Hung e569f13870 Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with" 
This reverts commit 2aedee1f0e.
 2019-08-28 17:22:44 -07:00
Eddie Hung 2421cb3fed Add arrival times for HX devices 2019-08-28 17:21:37 -07:00
Eddie Hung e4f89e01b5 Specify ice40 family to cells_sim.v using define 2019-08-28 17:21:12 -07:00
Eddie Hung 345a572449 Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival 2019-08-28 17:19:02 -07:00
Eddie Hung 2aedee1f0e Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with 
CARRY_WRAPPER in the same way since I0 and I3 could be used
 2019-08-28 17:07:36 -07:00
Eddie Hung 077e9d4ada Update box size and timings 2019-08-28 17:07:24 -07:00
Eddie Hung 129df7184a Update to new $__ICE40_CARRY_WRAPPER 2019-08-28 17:07:07 -07:00
Eddie Hung 1b08f861b6 Merge branch 'eddie/xilinx_srl' into xaig_arrival 2019-08-28 15:31:48 -07:00
Eddie Hung 8d820a9884 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-28 15:19:10 -07:00
Eddie Hung 9314a0a42e Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor 2019-08-28 10:51:39 -07:00
Eddie Hung ba5d81c7f1 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-28 09:21:03 -07:00
David Shah 13424352cc
Merge pull request #1332 from YosysHQ/dave/ecp5gsr 
ecp5: Add GSR and SGSR support
 2019-08-28 12:44:02 +01:00
Marcin Kościelnicki d361f5ab79 xilinx: Add SRLC16E primitive. 
Fixes #1331.
 2019-08-27 20:27:12 +02:00
David Shah fc001b4731 ecp5: Add GSR support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 13:07:06 +01:00
Eddie Hung 1ba09c4ab7 Merge branch 'master' into eddie/xilinx_srl 2019-08-26 13:56:31 -07:00
Eddie Hung a098205479 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-26 13:25:17 -07:00
Eddie Hung d7051b90de Add undocumented feature 2019-08-23 16:41:32 -07:00
Eddie Hung 455da57272 Fix spacing 2019-08-23 13:21:21 -07:00
Eddie Hung 85d39653ac Remove unused model 2019-08-23 13:20:29 -07:00
Eddie Hung 08139aa53a xilinx_srl now copes with word-level flops $dff{,e} 2019-08-23 12:22:46 -07:00
Eddie Hung 78b7d8f531 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-23 11:32:44 -07:00
Eddie Hung e658d472c8 Put attributes above port 2019-08-23 11:31:20 -07:00
Eddie Hung d672b1ddec Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-23 11:26:55 -07:00
Eddie Hung 20f4d191b5 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-23 11:24:19 -07:00
Eddie Hung 509c353fe9 Forgot one 2019-08-23 11:23:50 -07:00
Eddie Hung 0d0ad15898 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-23 11:23:31 -07:00
Eddie Hung a270af00cc Put abc_* attributes above port 2019-08-23 11:21:44 -07:00
Eddie Hung 6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Eddie Hung 7188972645 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-22 10:32:54 -07:00
Clifford Wolf 151db528e4 Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:09:37 +02:00
Clifford Wolf 2c8c8b3c74
Merge pull request #1289 from mmicko/anlogic_fixes 
Anlogic fixes and optimization
 2019-08-22 18:09:10 +02:00
Clifford Wolf 4c449caf9b Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:06:36 +02:00
Clifford Wolf 4d37710e82
Merge pull request #1281 from mmicko/efinix 
Initial support for Efinix Trion series FPGAs
 2019-08-22 18:06:02 +02:00
Eddie Hung 15188033da Add variable length support to xilinx_srl 2019-08-21 17:34:40 -07:00
Eddie Hung edec73fec1 abc9 to perform new 'map_ffs' before 'map_luts' 2019-08-21 15:37:55 -07:00
Eddie Hung 5ce0c31d0e Add init support 2019-08-21 13:05:10 -07:00
Eddie Hung c7af71ecde Use semicolon 2019-08-21 11:47:17 -07:00
Eddie Hung 5d0f6cbd54 techmap before read 2019-08-21 11:47:06 -07:00
Eddie Hung 8f69be9cc7 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-21 11:39:14 -07:00
Eddie Hung 584c680691 Add abc_arrival to SRL* 2019-08-21 11:27:42 -07:00
Eddie Hung 076af2e617 Missing newline 2019-08-20 20:37:52 -07:00
Eddie Hung b7a48e3e0f Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-20 20:18:17 -07:00
Eddie Hung 64d62710de Oops 2019-08-20 20:07:38 -07:00
Eddie Hung c26c556384 xilinx to use abc_map.v with -max_iter 1 2019-08-20 19:47:11 -07:00
Eddie Hung 6b1b03d9f7 ecp5: remove DPR16X4 from abc_unmap.v 2019-08-20 19:20:17 -07:00
Eddie Hung d46dc9c5b4 ecp5 to use -max_iter 1 2019-08-20 19:18:36 -07:00
Eddie Hung 55acf3120f ecp5 to use abc_map.v and _unmap.v 2019-08-20 18:59:03 -07:00
Eddie Hung 343039496b Add reference to FD* timing 2019-08-20 18:22:58 -07:00
Eddie Hung f1a206ba03 Revert "Remove sequential extension" 
This reverts commit 091bf4a18b.
 2019-08-20 18:17:14 -07:00
Eddie Hung 091bf4a18b Remove sequential extension 2019-08-20 18:16:37 -07:00
Eddie Hung bbab608691 Remove SRL* delays from cells_sim.v 2019-08-20 18:14:40 -07:00
Eddie Hung aa2d3af631 LUTMUX -> LUTMUX6 2019-08-20 18:08:07 -07:00
Eddie Hung 30a379b5b6 Cleanup techmap in map_luts 2019-08-20 17:59:31 -07:00
Eddie Hung 3b52d6e29c Move `techmap abc_map.v` into map_luts 2019-08-20 17:55:12 -07:00
Eddie Hung 54284aaa98 Remove delays from abc_map.v 2019-08-20 17:52:27 -07:00
Eddie Hung 96f00e9147 Typo 2019-08-20 17:51:50 -07:00
Eddie Hung 8f666ebac1 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-20 17:36:14 -07:00
Eddie Hung e273ed5275 Wrap SRL{16,32} too 2019-08-20 15:09:38 -07:00
Eddie Hung 808f07630f Wrap LUTRAMs in order to capture comb/seq behaviour 2019-08-20 14:49:11 -07:00
Eddie Hung 0079e9b4a6 Add LUTRAM delays 2019-08-20 13:53:38 -07:00
Eddie Hung 8d0cffaf20 Remove mapping rules 2019-08-20 13:11:39 -07:00
Eddie Hung 33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx 
[WIP] synth xilinx renaming, as per #1184
 2019-08-20 12:55:26 -07:00
Eddie Hung 5eda5fc7eb Remove -icells 2019-08-20 12:41:11 -07:00
Eddie Hung be9e4f1b67 Use abc_{map,unmap,model}.v 2019-08-20 12:39:11 -07:00
Eddie Hung c4d4c6db3f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-20 12:00:12 -07:00
Eddie Hung 14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor 
Refactor abc9 to use port attributes, not module attributes
 2019-08-20 11:59:31 -07:00
Eddie Hung d9fe4cccbf Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx 2019-08-20 11:57:52 -07:00
Eddie Hung 526e081342 Add arrival times for SRL outputs 2019-08-19 15:15:43 -07:00
Eddie Hung b71212ddea Add BRAM arrival times 2019-08-19 12:46:35 -07:00
Eddie Hung 2f86366087 Add reference to source of Tclktoq timing 2019-08-19 12:39:22 -07:00
Eddie Hung d02ef8c73f Add 'abc_arrival' attribute for flop outputs 2019-08-19 11:32:18 -07:00
Eddie Hung f25837f8e8 Update box timings 2019-08-19 11:31:40 -07:00
Eddie Hung ba2261e21a Move from cell attr to module attr 2019-08-19 11:18:33 -07:00
Eddie Hung 2f4e0a5388 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-19 10:07:27 -07:00
Eddie Hung d81a090d89 Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro 2019-08-19 09:56:17 -07:00
Eddie Hung e301440a0b Use attributes instead of params 2019-08-19 09:51:49 -07:00
Miodrag Milanovic 4a32e29445 Merge remote-tracking branch 'upstream/master' into anlogic_fixes 2019-08-18 11:47:46 +02:00
whitequark 101235400c
Merge branch 'master' into eddie/pr1266_again 2019-08-18 08:04:10 +00:00
Eddie Hung 24c934f1af Merge branch 'eddie/abc9_refactor' into xaig_dff 2019-08-16 16:51:22 -07:00
Eddie Hung 1c57b1e7ea Update abc_* attr in ecp5 and ice40 2019-08-16 15:56:57 -07:00
Eddie Hung 562c9e3624 Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules 2019-08-16 15:40:53 -07:00
Eddie Hung 41191f1ea4
Merge pull request #1250 from bwidawsk/master 
techlibs/intel: Clean up Makefile
 2019-08-16 14:07:09 -07:00
Eddie Hung 261daffd9d Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-15 12:19:47 -07:00
Eddie Hung e35dfc5ab5 Only swap ports if $mul and not $__mul 2019-08-13 16:52:15 -07:00
Marcin Kościelnicki 3c75a72feb move attributes to wires 2019-08-13 19:36:59 +00:00
Eddie Hung ed4b2834ef Add assign PCOUT = P to DSP48E1 2019-08-13 12:19:26 -07:00
Marcin Kościelnicki 49765ec19e minor review fixes 2019-08-13 18:05:49 +00:00
Eddie Hung 2a1b98d478 Add DSP_A_MAXWIDTH_PARTIAL, refactor 2019-08-13 10:21:24 -07:00
David Shah edff79a25a xilinx: Rework labels for faster Verilator testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-13 10:29:42 +01:00
Marcin Kościelnicki c6d5b97b98 review fixes 2019-08-13 00:35:54 +00:00
Marcin Kościelnicki f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Eddie Hung 8a2480526f Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER 2019-08-12 12:19:25 -07:00
Eddie Hung 12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
Eddie Hung f890cfb63b Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-12 11:32:10 -07:00
Miodrag Milanovic 5f561bdcb1 Proper arith for Anlogic and use standard pass 2019-08-12 20:21:36 +02:00
Miodrag Milanovic 2897fe4d09 Fix formating 2019-08-11 17:05:24 +02:00
Miodrag Milanovic ead2b52b5a one bit enable signal 2019-08-11 13:59:39 +02:00
Miodrag Milanovic aa0c37722a fix mixing signals on FF mapping 2019-08-11 11:40:15 +02:00
Miodrag Milanovic 853c755a0c Replaced custom step with setundef 2019-08-11 11:01:46 +02:00
Miodrag Milanovic e609537e38 Fixed data width 2019-08-11 10:46:48 +02:00
Miodrag Milanovic 8c8100e0df Adding new pass to fix carry chain 2019-08-11 10:17:49 +02:00
Miodrag Milanovic b3a91d6508 cleanup 2019-08-11 08:37:56 +02:00
David Shah f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Clifford Wolf f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Clifford Wolf a469d1a64a
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc 
Add a few comments to document $alu and $lcu
 2019-08-10 09:46:46 +02:00
Eddie Hung 6d254f2de8 Add wreduce to synth_ice40 -dsp as well 2019-08-09 17:05:56 -07:00
Eddie Hung 0b5b56c1ec Pack partial-product adder DSP48E1 packing 2019-08-09 15:19:33 -07:00
Eddie Hung 041defc5a6 Reformat so it shows up/looks nice when "help $alu" and "help $alu+" 2019-08-09 12:33:39 -07:00
Eddie Hung acfb672d34 A bit more on where $lcu comes from 2019-08-09 09:50:47 -07:00
Eddie Hung 5aef998957 Add more comments 2019-08-09 09:48:17 -07:00
Miodrag Milanovic d51b135e33 Fix CO 2019-08-09 12:37:10 +02:00
Miodrag Milanovic 7a860c5623 Merge remote-tracking branch 'upstream/master' into efinix 2019-08-09 09:46:37 +02:00
Eddie Hung 1f722b3500 Remove signed from ports in +/xilinx/dsp_map.v 2019-08-08 16:33:20 -07:00
Eddie Hung 2c0be7aa5d Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing 2019-08-08 12:56:05 -07:00
Eddie Hung 162eab6b74 Combine techmap calls 2019-08-08 10:55:48 -07:00
Eddie Hung 7160243874 Move xilinx_dsp to before alumacc 2019-08-08 10:45:56 -07:00
Eddie Hung 57b2e4b9c1 INMODE is 5 bits 2019-08-08 10:44:35 -07:00
Eddie Hung 13cc106cf7 Fix copy-pasta typo 2019-08-08 10:44:26 -07:00
Eddie Hung dae7c59358 Add a few comments to document $alu and $lcu 2019-08-08 10:05:28 -07:00
David Shah 0492b8b541 ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 15:18:59 +01:00
David Shah cb84ed2326 ecp5: Bring up to date with mul2dsp changes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 15:14:09 +01:00
David Shah 83b2e02723 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-08 11:40:09 +01:00
David Shah b8cd4ad64a DSP48E1 sim model: add SIMD tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:39:35 +01:00
David Shah 57aeb4cc01 DSP48E1 model: test CE inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:32:43 +01:00
David Shah d60b3c0dc8 DSP48E1 sim model: fix seq tests and add preadder tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:18:37 +01:00
David Shah e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:52:04 +01:00
David Shah f6605c7dc0 DSP48E1 sim model: Comb, no pre-adder, mode working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:26:44 +01:00
David Shah f0f352e971 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:05:11 +01:00
David Shah ccfb4ff2a9 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 09:31:34 +01:00
Eddie Hung 9776084eda Allow whitebox modules to be overwritten 2019-08-07 16:40:24 -07:00
Eddie Hung 675c1d4218 Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER 2019-08-07 16:29:38 -07:00
Eddie Hung cc331cf70d Add test 2019-08-07 16:29:38 -07:00
Eddie Hung ea8ac8fd74 Remove ice40_unlut 2019-08-07 16:29:38 -07:00
Eddie Hung 6b314c8371 Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER 2019-08-07 16:29:38 -07:00
Eddie Hung a206aed977 Run "opt_expr -fine" instead of "wreduce" due to #1213 2019-08-07 13:59:07 -07:00
Eddie Hung e3d898dccb Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-07 13:44:08 -07:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung 7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
Eddie Hung e6d5147214 Merge remote-tracking branch 'origin/master' into eddie/cleanup 2019-08-07 11:11:50 -07:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
David Shah 5545cd3c10
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes 
ecp5: Make cells_sim.v consistent with nextpnr
 2019-08-07 15:35:29 +01:00
David Shah a36fd8582e ecp5: Make cells_sim.v consistent with nextpnr 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:19:31 +01:00
David Shah fe95807f16 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 13:09:12 +01:00
Clifford Wolf 4c49ddf36a
Merge pull request #1249 from mmicko/anlogic_fix 
anlogic : Fix alu mapping
 2019-08-07 12:30:52 +02:00
Eddie Hung e5be9ff871 Fix spacing 2019-08-06 16:47:55 -07:00
Eddie Hung c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Eddie Hung 3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
David Shah c43b0c4b49 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 18:47:18 +01:00
David Shah 7a563d0b92 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 13:23:42 +01:00
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
Ben Widawsky 7de098ad45 techlibs/intel: Clean up Makefile 
Use GNU make's foreach iterator and remove nonexistent files. Gmake is
already a requirement of the build system.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-08-05 11:22:11 -07:00
Miodrag Milanovic 8a3329871b clock for ram trough gbuf 2019-08-04 12:17:55 +02:00
Miodrag Milanovic cf96f41c6d Added bram support 2019-08-04 11:46:36 +02:00
Miodrag Milanovic 837cb0a1b9 anlogic : Fix alu mapping 2019-08-03 14:47:33 +02:00
Miodrag Milanovic 6e210f26fa Custom step to add global clock buffers 2019-08-03 14:40:23 +02:00
Miodrag Milanovic ab98f604fd Initial EFINIX support 2019-08-03 13:10:44 +02:00
Clifford Wolf f4ae6afc22
Merge pull request #1239 from mmicko/mingw_fix 
Fix formatting for msys2 mingw build
 2019-08-02 16:37:57 +02:00
Eddie Hung 105aaeaf59 Trim Y_WIDTH 2019-08-01 14:33:16 -07:00
Eddie Hung 65de9aaaa9 Add DSP_SIGNEDONLY back 2019-08-01 14:29:00 -07:00
Eddie Hung 915f4e34bf DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH 2019-08-01 13:20:34 -07:00
Eddie Hung fc0b5d5ab6 Change $__softmul back to $mul 2019-08-01 12:45:14 -07:00
Eddie Hung 332b86491d Revert "Do not do sign extension in techmap; let packer do it" 
This reverts commit 595a8f032f.
 2019-08-01 12:17:14 -07:00
Eddie Hung ed303b07b7 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-01 12:02:16 -07:00
Eddie Hung 7e86c8bcfb Fix B_WIDTH > DSP_B_MAXWIDTH case 2019-08-01 10:01:43 -07:00
Miodrag Milanovic 28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Eddie Hung d2c33863d0 Do not compute sign bit if result is zero 2019-07-31 16:04:19 -07:00
Eddie Hung 60c4887d15 For signed multipliers, compute sign bit separately... 2019-07-31 15:45:41 -07:00
Eddie Hung 66806085db RST -> RSTBRST for RAMB8BWER 2019-07-29 16:05:44 -07:00
Eddie Hung 2f71c2c219 Fix spacing 2019-07-26 15:30:51 -07:00
Clifford Wolf eb663c7579 Merge branch 'ZirconiumX-synth_intel_m9k' 2019-07-25 17:23:48 +02:00
Clifford Wolf 5c933e5110
Merge pull request #1218 from ZirconiumX/synth_intel_iopads 
intel: Make -noiopads the default
 2019-07-25 17:19:54 +02:00
Eddie Hung 5248a902ef
Merge pull request #1224 from YosysHQ/xilinx_fix_ff 
xilinx: Fix missing cell name underscore in cells_map.v
 2019-07-25 06:44:17 -07:00
David Shah ab607e896e xilinx: Fix missing cell name underscore in cells_map.v 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-25 08:19:07 +01:00
Eddie Hung c39ccc65e9 Add copyright header, comment on cascade 2019-07-24 10:49:09 -07:00
Dan Ravensloft 49528ed3bd intel: Make -noiopads the default 2019-07-24 10:38:15 +01:00
Eddie Hung 151c5c96c0 Typo for Y_WIDTH 2019-07-23 15:05:20 -07:00
Dan Ravensloft 67b4ce06e0 intel: Map M9K BRAM only on families that have it 
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
 2019-07-23 18:11:11 +01:00
Eddie Hung cb505c50d3 Remove debug 2019-07-22 16:14:15 -07:00
Eddie Hung 4d71ab384d Rename according to vendor doc TN1295 2019-07-22 15:08:26 -07:00
Eddie Hung 5e70b8a22b opt and wreduce necessary for -dsp 2019-07-22 13:48:33 -07:00
Eddie Hung 3a7aeb028d Use minimum sized width wires 2019-07-22 13:01:26 -07:00
Eddie Hung 47fd042b9f Indirection via $__soft_mul 2019-07-19 20:20:33 -07:00
Eddie Hung 595a8f032f Do not do sign extension in techmap; let packer do it 2019-07-19 15:50:13 -07:00
Eddie Hung bba72f03dd Do not $mul -> $__mul if A and B are less than maxwidth 2019-07-19 11:54:26 -07:00
Eddie Hung 3dc3c749d5 Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold 2019-07-19 11:41:00 -07:00
Eddie Hung 1d14cec7fd Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too 2019-07-19 11:39:24 -07:00
Eddie Hung 7bdb3996e2 Merge branch 'xc7dsp' into ice40dsp 2019-07-19 10:28:38 -07:00
Eddie Hung ca94c2d3c4 Fix typo in B 2019-07-19 10:27:44 -07:00
Eddie Hung d439a830c6 Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp 2019-07-19 09:40:47 -07:00
David Shah 80884d6f7b ice40: Fix test_dsp_model.sh 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:57 +01:00
David Shah 79f14c7514 ice40/cells_sim.v: Fix sign of J and K partial products 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:41 +01:00
Eddie Hung 2168568f43 Use sign_headroom instead 2019-07-19 09:16:13 -07:00
David Shah 3c84271543 ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:13:34 +01:00
Eddie Hung 171cd2ff73 Add tests for all combinations of A and B signedness for comb mul 2019-07-19 08:52:49 -07:00
Eddie Hung f7753720fe Don't copy ref if exists already 2019-07-19 08:45:35 -07:00
Eddie Hung bddd641290 Fix SB_MAC sim model -- do not sign extend internal products? 2019-07-18 21:03:54 -07:00
Eddie Hung 601fac97e4 Add params 2019-07-18 21:02:49 -07:00
Eddie Hung a777be3091 Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 20:37:39 -07:00
Eddie Hung 0157043b97 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-07-18 20:36:48 -07:00
Eddie Hung 15c2a79ab9 Do not define `DSP_SIGNEDONLY macro if no exists 2019-07-18 16:04:58 -07:00
Eddie Hung 42e40dbd0a Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 15:45:25 -07:00
Eddie Hung 266c1ae122 synth_ice40 to decompose into 16x16 2019-07-18 15:38:09 -07:00
Eddie Hung 2339b7fc37 mul2dsp to create cells that can be interchanged with $mul 2019-07-18 15:37:35 -07:00