mirror of https://github.com/YosysHQ/yosys.git
Do not define `DSP_SIGNEDONLY macro if no exists
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@ -8,9 +8,6 @@ $error("Macro DSP_A_MAXWIDTH must be defined");
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`ifndef DSP_B_MAXWIDTH
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$error("Macro DSP_B_MAXWIDTH must be defined");
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`endif
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`ifndef DSP_SIGNEDONLY
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`define DSP_SIGNEDONLY 0
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`endif
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`ifndef DSP_NAME
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$error("Macro DSP_NAME must be defined");
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@ -33,7 +30,8 @@ module \$mul (A, B, Y);
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generate
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if (A_SIGNED != B_SIGNED)
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wire _TECHMAP_FAIL_ = 1;
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else if (`DSP_SIGNEDONLY && !A_SIGNED) begin
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`ifdef DSP_SIGNEDONLY
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else if (!A_SIGNED) begin
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wire [1:0] dummy;
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\$mul #(
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.A_SIGNED(1),
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@ -47,6 +45,7 @@ module \$mul (A, B, Y);
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.Y({dummy, Y})
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);
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end
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`endif
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// NB: A_SIGNED == B_SIGNED == 0 from here
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else if (A_WIDTH >= B_WIDTH)
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\$__mul_gen #(
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