mirror of https://github.com/YosysHQ/yosys.git
clock for ram trough gbuf
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@ -38,6 +38,12 @@ static void handle_gbufs(Module *module)
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for (auto bit : sigmap(cell->getPort("\\CLK")))
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clk_bits.insert(bit);
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}
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if (cell->type == "\\EFX_RAM_5K") {
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for (auto bit : sigmap(cell->getPort("\\RCLK")))
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clk_bits.insert(bit);
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for (auto bit : sigmap(cell->getPort("\\WCLK")))
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clk_bits.insert(bit);
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}
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}
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for (auto wire : vector<Wire*>(module->wires()))
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