mirror of https://github.com/YosysHQ/yosys.git
Fix B_WIDTH > DSP_B_MAXWIDTH case
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@ -67,22 +67,6 @@ module \$mul (A, B, Y);
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.B(A),
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.Y(Y)
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);
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else if (A_SIGNED && (A_WIDTH > `DSP_A_MAXWIDTH || B_WIDTH > `DSP_B_MAXWIDTH)) begin
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wire _;
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.Y({_,Y[Y_WIDTH-2:0]})
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);
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// For non-zero results, recompute sign bit
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assign Y[Y_WIDTH-1] = (|Y[Y_WIDTH-2:0]) & (A[A_WIDTH-1] ^ B[B_WIDTH-1]);
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end
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else
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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@ -171,14 +155,15 @@ module \$__mul (A, B, Y);
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assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1];
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end
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localparam last_A_WIDTH = A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom);
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)),
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.A_WIDTH(last_A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(last_Y_WIDTH)
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) mul_slice_last (
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.A(A[A_WIDTH-1 : (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]),
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.A(A[A_WIDTH-1 -: last_A_WIDTH]),
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.B(B),
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.Y(last_partial)
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);
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@ -232,20 +217,17 @@ module \$__mul (A, B, Y);
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end
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localparam last_B_WIDTH = B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom);
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if (A_SIGNED && B_SIGNED && last_B_WIDTH == 1)
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assign last_partial = 0;
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else
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(last_B_WIDTH),
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.Y_WIDTH(last_Y_WIDTH)
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) mul_last (
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.A(A),
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.B(B[B_WIDTH-1 -: last_B_WIDTH]),
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.Y(last_partial)
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);
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(last_B_WIDTH),
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.Y_WIDTH(last_Y_WIDTH)
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) mul_last (
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.A(A),
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.B(B[B_WIDTH-1 -: last_B_WIDTH]),
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.Y(last_partial)
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);
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assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
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assign Y = partial_sum[n-1];
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end
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