riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Do not $mul -> $__mul if A and B are less than maxwidth

This commit is contained in:
Eddie Hung 2019-07-19 11:54:26 -07:00
parent 3dc3c749d5
commit bba72f03dd
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
techlibs/common/mul2dsp.v
View File

@ -28,7 +28,9 @@ module \$mul (A, B, Y);
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1)
if (A_SIGNED != B_SIGNED)
wire _TECHMAP_FAIL_ = 1;
else if (A_WIDTH <= `DSP_A_MAXWIDTH && B_WIDTH <= `DSP_B_MAXWIDTH)
wire _TECHMAP_FAIL_ = 1;
// NB: A_SIGNED == B_SIGNED == 0 from here
else if (A_WIDTH >= B_WIDTH)