mirror of https://github.com/YosysHQ/yosys.git
Indirection via $__soft_mul
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@ -28,9 +28,7 @@ module \$mul (A, B, Y);
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output [Y_WIDTH-1:0] Y;
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generate
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if (A_SIGNED != B_SIGNED)
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wire _TECHMAP_FAIL_ = 1;
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else if (A_WIDTH <= `DSP_A_MAXWIDTH && B_WIDTH <= `DSP_B_MAXWIDTH)
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if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1)
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wire _TECHMAP_FAIL_ = 1;
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// NB: A_SIGNED == B_SIGNED == 0 from here
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else if (A_WIDTH >= B_WIDTH)
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@ -212,7 +210,7 @@ module \$__mul (A, B, Y);
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endmodule
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(* techmap_celltype = "$__mul" *)
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module _90_internal_mul_to_external (A, B, Y);
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module $__soft_mul (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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@ -223,9 +221,11 @@ module _90_internal_mul_to_external (A, B, Y);
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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// Indirection necessary since mapping
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// back to $mul will cause recursion
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generate
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if (A_SIGNED && !B_SIGNED)
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\$mul #(
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\$__soft__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(1),
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.A_WIDTH(A_WIDTH),
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@ -233,23 +233,23 @@ module _90_internal_mul_to_external (A, B, Y);
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B({1'b0, B}),
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.B({1'b0,B}),
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.Y(Y)
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);
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else if (!A_SIGNED && B_SIGNED)
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\$mul #(
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\$__soft_mul #(
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.A_SIGNED(1),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH+1),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A({1'b0, A}),
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.A({1'b0,A}),
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.B(B),
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.Y(Y)
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);
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else
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\$mul #(
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\$__soft_mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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@ -268,6 +268,7 @@ struct SynthIce40Pass : public ScriptPass
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if (help_mode || dsp) {
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run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
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run("ice40_dsp", "(if -dsp)");
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run("chtype -set $mul t:$__soft_mul");
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}
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run("alumacc");
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run("opt");
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