tangxifan
|
b07111497c
|
[core] enable options in xml writers
|
2023-10-06 18:20:17 -07:00 |
|
tangxifan
|
ae63c9d441
|
[core] code format
|
2023-10-06 17:28:25 -07:00 |
|
tangxifan
|
1e8bf1cece
|
[core] deploy options
|
2023-10-06 17:28:02 -07:00 |
|
tangxifan
|
f30663f708
|
[core] code format
|
2023-10-06 14:08:09 -07:00 |
|
tangxifan
|
108bbad8d4
|
[core] syntax
|
2023-10-06 14:07:44 -07:00 |
|
tangxifan
|
80856f1b70
|
[core] adding new options and rewrite options for bitfile writer
|
2023-10-06 13:54:29 -07:00 |
|
tangxifan
|
a15db83267
|
[core] code format
|
2023-09-26 11:41:11 -07:00 |
|
tangxifan
|
ea91182216
|
[core] check option conflicts
|
2023-09-26 11:40:42 -07:00 |
|
tangxifan
|
c4bce834e4
|
[core] code format
|
2023-09-25 22:34:39 -07:00 |
|
tangxifan
|
5aa206e616
|
[core] fixed some bugs
|
2023-09-25 22:27:24 -07:00 |
|
tangxifan
|
1624dc9764
|
[core] code format
|
2023-09-25 21:13:50 -07:00 |
|
tangxifan
|
76f446caec
|
[core] fixed a bug
|
2023-09-25 21:13:11 -07:00 |
|
tangxifan
|
dbd466cdec
|
[core] now support tile port merge
|
2023-09-25 18:16:24 -07:00 |
|
tangxifan
|
3adf81046a
|
[core] code format
|
2023-09-25 17:22:26 -07:00 |
|
tangxifan
|
5e269e8bc4
|
[core] support port merging at grid modules
|
2023-09-25 17:21:58 -07:00 |
|
tangxifan
|
edb0e687f1
|
[core] code format
|
2023-09-23 12:15:53 -07:00 |
|
tangxifan
|
11de8965a8
|
[core] fixed some bugs
|
2023-09-23 12:15:31 -07:00 |
|
tangxifan
|
860cfd53c6
|
[core] fixed critical bugs in renaming modules
|
2023-09-23 11:51:31 -07:00 |
|
tangxifan
|
ca3617a029
|
[core] code format
|
2023-09-20 20:37:27 -07:00 |
|
tangxifan
|
1ef38b6a64
|
[core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming
|
2023-09-20 20:34:21 -07:00 |
|
tangxifan
|
c105b56bf0
|
[core] code format
|
2023-09-18 23:31:27 -07:00 |
|
tangxifan
|
43fd08a3fe
|
[core] fixed a bug
|
2023-09-18 23:31:09 -07:00 |
|
tangxifan
|
4d11f73471
|
[core] fixed a bug
|
2023-09-18 20:43:15 -07:00 |
|
tangxifan
|
a1e609c901
|
[core] fixed some bugs
|
2023-09-18 16:39:07 -07:00 |
|
tangxifan
|
1daabb990e
|
[core] code format
|
2023-09-18 15:35:13 -07:00 |
|
tangxifan
|
110301a2e4
|
[core] now tile port naming can follow index
|
2023-09-18 15:34:40 -07:00 |
|
tangxifan
|
e46e58527a
|
[core] code format
|
2023-09-17 23:16:38 -07:00 |
|
tangxifan
|
eeb1bd6662
|
[core] fixed some bugs
|
2023-09-17 23:16:15 -07:00 |
|
tangxifan
|
c6175aa514
|
[core] code format
|
2023-09-17 22:37:48 -07:00 |
|
tangxifan
|
ef97127c63
|
[core] fixed some bugs in testbenches when renaming top modules
|
2023-09-17 22:34:00 -07:00 |
|
tangxifan
|
c14277a674
|
[core] fixing bugs
|
2023-09-17 17:57:57 -07:00 |
|
tangxifan
|
d5152dc16d
|
[core] fixed a bug on the hierarchy writer
|
2023-09-17 17:42:25 -07:00 |
|
tangxifan
|
4ccb4737be
|
[core] code format
|
2023-09-17 17:33:10 -07:00 |
|
tangxifan
|
f79da76656
|
[core] supporting renaming on all the verilog modules
|
2023-09-17 17:29:11 -07:00 |
|
tangxifan
|
72a3c05747
|
[core] code format
|
2023-09-17 13:29:30 -07:00 |
|
tangxifan
|
ccd4c1861b
|
[core] developing new command to write module naming rules
|
2023-09-16 19:37:06 -07:00 |
|
tangxifan
|
32df673d72
|
[core] code format
|
2023-09-16 18:35:33 -07:00 |
|
tangxifan
|
200ecad74a
|
[core] fixed bugs in bitgen
|
2023-09-16 18:34:55 -07:00 |
|
tangxifan
|
058bb1ef51
|
[core] code format
|
2023-09-16 18:24:38 -07:00 |
|
tangxifan
|
6fc2924438
|
[core] syntax
|
2023-09-16 18:16:30 -07:00 |
|
tangxifan
|
d61d88f12e
|
[core] fixed some bugs in verilog writer due to renaming
|
2023-09-16 18:13:22 -07:00 |
|
tangxifan
|
37573abc22
|
[core] code format
|
2023-09-15 23:32:40 -07:00 |
|
tangxifan
|
c85c64eb5a
|
[core] syntax
|
2023-09-15 23:30:34 -07:00 |
|
tangxifan
|
bc407e5d69
|
[core] code complete for rename modules
|
2023-09-15 23:22:31 -07:00 |
|
tangxifan
|
2a45b49890
|
[core] developing renaming commands. options and functions
|
2023-09-15 19:15:18 -07:00 |
|
tangxifan
|
af67b02cca
|
[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
|
2023-09-15 13:51:14 -07:00 |
|
tangxifan
|
eaadff3448
|
[core] fixed some bugs
|
2023-09-06 22:49:56 -07:00 |
|
tangxifan
|
bcb82d43af
|
[core] code format
|
2023-09-06 22:40:59 -07:00 |
|
tangxifan
|
2fee56548b
|
[core] fixed some bugs
|
2023-09-06 22:39:59 -07:00 |
|
tangxifan
|
f544953085
|
[core] code format
|
2023-09-06 22:29:30 -07:00 |
|
tangxifan
|
f8b2eec988
|
[core] now default net type wire will not appear. timescale does not show in fabric netlists
|
2023-09-06 22:27:51 -07:00 |
|
tangxifan
|
539bcba851
|
[core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types
|
2023-09-06 17:23:41 -07:00 |
|
tangxifan
|
dfe5447e2a
|
[core] format
|
2023-08-25 15:21:24 -07:00 |
|
tangxifan
|
b8c66b06a0
|
[core] syntax
|
2023-08-25 15:17:52 -07:00 |
|
tangxifan
|
717906ea17
|
[core] code format
|
2023-08-25 15:13:39 -07:00 |
|
tangxifan
|
89b392a51f
|
[core] adapt changes in is_sb_exist()
|
2023-08-25 15:13:00 -07:00 |
|
tangxifan
|
55e5f738ce
|
[core] code format
|
2023-08-25 11:58:15 -07:00 |
|
tangxifan
|
92f92658c9
|
[core] remove useless errors
|
2023-08-25 11:53:49 -07:00 |
|
tangxifan
|
a6d43beaca
|
[core] now tile verilog writer supports relative paths
|
2023-08-21 22:25:52 -07:00 |
|
tangxifan
|
66cc375996
|
[core] remove debugging messages
|
2023-08-18 22:08:47 -07:00 |
|
tangxifan
|
19d4d9a16d
|
[core] code format
|
2023-08-18 21:05:26 -07:00 |
|
tangxifan
|
fc523bed32
|
[core] fixed some bugs in spotting the correct pin index of given subtiles
|
2023-08-18 21:04:37 -07:00 |
|
tangxifan
|
3d8f76269a
|
[core] fixed a bug when io is in the center of 3x3 fabric
|
2023-08-18 12:42:15 -07:00 |
|
tangxifan
|
e9fd22790d
|
[core] fixed a bug where pass thru cb blocks are not connected in tiles
|
2023-08-17 15:26:32 -07:00 |
|
tangxifan
|
399f087c50
|
[core] code format
|
2023-08-17 13:54:31 -07:00 |
|
tangxifan
|
414f7379c6
|
[core] fixed some bugs in debugging messages
|
2023-08-17 13:52:21 -07:00 |
chungshien
|
aabbd330b3
|
Address follow up from PR 1259 (1)
|
2023-08-11 08:06:57 -07:00 |
|
chungshien
|
6c0df8da20
|
Address follow up from PR 1259
|
2023-08-11 07:59:53 -07:00 |
|
tangxifan
|
788e3c17a9
|
[core] format
|
2023-08-08 23:02:20 -07:00 |
|
tangxifan
|
1c8c4fedbb
|
[core] fix memory leak
|
2023-08-08 23:01:52 -07:00 |
|
tangxifan
|
ff6fa1e90c
|
[core] fix memory leak
|
2023-08-08 22:41:43 -07:00 |
|
tangxifan
|
94d80a9b7c
|
[core] code format
|
2023-08-08 16:28:56 -07:00 |
|
tangxifan
|
867da98d3f
|
[core] update to use latest api from vpr upstream
|
2023-08-08 16:28:19 -07:00 |
|
tangxifan
|
bb945b2816
|
Merge branch 'master' into openfpga-issue-1256
|
2023-08-07 13:49:19 -07:00 |
|
tangxifan
|
4d37421735
|
[core] fixed a bug on loading subkey to support fabric keys
|
2023-08-07 10:40:22 -07:00 |
|
tangxifan
|
18acb39fad
|
[core] fixed a bug where heterogeneous fabric may fail
|
2023-08-06 22:12:32 -07:00 |
|
tangxifan
|
26c8b5146c
|
[core] fixed a bug where release build will fail
|
2023-08-06 21:44:15 -07:00 |
|
tangxifan
|
c5b1918e47
|
[core] fixed a critical bug which causes reg test failures when group_config_block is off
|
2023-08-06 13:11:17 -07:00 |
|
tangxifan
|
beee2369c9
|
[core] fixed a bug
|
2023-08-05 22:06:17 -07:00 |
|
tangxifan
|
a1f8b3c441
|
[core] fixed a bug on bitstream generator on supporting group_config_block
|
2023-08-05 21:58:03 -07:00 |
|
tangxifan
|
68f07d6fc9
|
[core] code format
|
2023-08-05 20:53:58 -07:00 |
|
tangxifan
|
2aab94cd6c
|
[core] syntax
|
2023-08-05 14:11:57 -07:00 |
|
tangxifan
|
22816a7ed4
|
[core] syntax
|
2023-08-05 14:04:57 -07:00 |
|
tangxifan
|
f4d7ad2bd1
|
[core] trying to fix the bug on instance naming so that bitstream generation can work
|
2023-08-05 13:38:51 -07:00 |
|
tangxifan
|
9a23dc7bff
|
[core] fixed some bugs which causes architecture bitstream generation failed when supporting group_config_block
|
2023-08-04 21:20:21 -07:00 |
|
tangxifan
|
7d8d686f74
|
[core] add status codes to build grid modules
|
2023-08-04 16:52:43 -07:00 |
|
tangxifan
|
bb9cf6dbcb
|
[core] fixed a critical bug which causes undriven nets on config bus in group config block
|
2023-08-04 16:45:15 -07:00 |
|
tangxifan
|
64c0839e30
|
[core] now verilog writer supports memory group modules
|
2023-08-04 16:11:33 -07:00 |
|
tangxifan
|
a0f81a5bf2
|
[core] now verilog generator can output feedthrough memory module to files
|
2023-08-04 13:34:38 -07:00 |
|
tangxifan
|
5bc8925c3a
|
[core] fixed multiple bugs on fabric generator on supporting group_config_block
|
2023-08-04 12:36:59 -07:00 |
|
tangxifan
|
3c2518ac70
|
[core] adding debugging message when verbose is enabled
|
2023-08-04 11:20:05 -07:00 |
|
tangxifan
|
99bda2e5b0
|
[core] debugging
|
2023-08-03 22:50:14 -07:00 |
|
tangxifan
|
2aeeb0cacf
|
[core] fixed a bug which causes reg tests failed
|
2023-08-03 22:13:27 -07:00 |
|
tangxifan
|
d3895c3dc0
|
[core] code format
|
2023-08-03 17:34:25 -07:00 |
|
tangxifan
|
f4cbc95053
|
[core] syntax
|
2023-08-03 17:33:57 -07:00 |
|
tangxifan
|
5618f1d567
|
[core] now bitgen uses config child types
|
2023-08-03 16:06:19 -07:00 |
|
tangxifan
|
3331540ed6
|
[core] using config child type in bitstream generation
|
2023-08-03 14:24:22 -07:00 |
|
tangxifan
|
2facde2097
|
[core] reworked fabric generator to use config child type
|
2023-08-03 12:57:50 -07:00 |
|
tangxifan
|
5895a1d96b
|
[core] reworking fabric generator based on latest changes on configurable children
|
2023-08-02 22:50:19 -07:00 |
|
tangxifan
|
27cae41123
|
[core] rework physical and logical types of configurable child
|
2023-08-02 20:37:27 -07:00 |
|
tangxifan
|
87f2822ef8
|
[core] working on logical and physical children
|
2023-08-02 19:46:27 -07:00 |
|
tangxifan
|
c05f12ac11
|
[core] sync up logical-to-physical configurable child mapping after physical memory build-up
|
2023-08-02 12:24:16 -07:00 |
|
tangxifan
|
470ab84489
|
[core] developing group config block support for routing module
|
2023-08-01 22:57:22 -07:00 |
|
tangxifan
|
53050b94ab
|
[core] developing memory group modules in grid modules
|
2023-08-01 17:50:03 -07:00 |
|
chungshien
|
eed96b395e
|
Misc - update comment + remove code that not being used
|
2023-08-01 07:33:17 -07:00 |
|
tangxifan
|
23643f3fb1
|
[core] developing the physical memory block builder
|
2023-07-31 22:57:26 -07:00 |
|
tangxifan
|
2d2b8f67aa
|
[core] adding new option '--group_config_block' to command 'build_fabric'
|
2023-07-31 17:32:48 -07:00 |
chungshien
|
c1b5ca0941
|
Merge branch 'master' into openfpga-issue-1256
|
2023-07-31 01:18:10 -07:00 |
|
cschai
|
aae037bf77
|
Address comment
|
2023-07-30 02:18:48 -07:00 |
|
cschai
|
838cf0d818
|
Address comment
|
2023-07-30 01:14:11 -07:00 |
|
cschai
|
56d76741d5
|
Address comment
|
2023-07-30 00:39:16 -07:00 |
|
cschai
|
63459218e5
|
Address comment
|
2023-07-30 00:24:40 -07:00 |
|
tangxifan
|
beaa687a20
|
[core] fixed bugs on supporting heterogeneous blocks in tile modules
|
2023-07-27 20:29:18 -07:00 |
|
tangxifan
|
c2066cc63c
|
[core] fixed a bug where pb/cb/sb instance name is not assigned correctly in bitstream manager under tile modules
|
2023-07-27 13:33:23 -07:00 |
|
tangxifan
|
156cb800aa
|
[core] fixed a critical bug which causes wrong connections in tile modules
|
2023-07-27 12:22:16 -07:00 |
|
tangxifan
|
dd486f5ccb
|
[core] fixed a bug on checking if cb is in a tile
|
2023-07-27 11:14:05 -07:00 |
|
tangxifan
|
cfec6c88f1
|
[core] fixed a bug in cb instance naming
|
2023-07-27 10:59:46 -07:00 |
|
tangxifan
|
be0715a81c
|
[core] fixed a bug on cb instance name. Spot some bug in port naming for tile modules
|
2023-07-27 10:42:56 -07:00 |
|
tangxifan
|
97219fd825
|
[core] add more verbose to help debug failed test cases
|
2023-07-26 23:26:11 -07:00 |
|
tangxifan
|
19ed9ea669
|
Merge branch 'master' into openfpga-issue-1256
|
2023-07-26 10:32:30 -07:00 |
|
tangxifan
|
f5e8f175fb
|
[core] fixed a bug which causes flow failures when group_tile is not enabled
|
2023-07-25 21:27:58 -07:00 |
|
tangxifan
|
83428a209e
|
[core] fixed a bug on io indexing which causes tile-based test cases failed in dv
|
2023-07-25 16:03:50 -07:00 |
|
tangxifan
|
de6956530f
|
[core] disable pnr sdc for tile-based fabric
|
2023-07-25 15:38:41 -07:00 |
|
tangxifan
|
6ecbbb3a94
|
[core] fixed a bug in fabric bitgen due to tile modules
|
2023-07-25 14:49:12 -07:00 |
|
tangxifan
|
95a32628ab
|
[core] fixed the bug in arch bitgen due to the tile modules
|
2023-07-25 14:15:15 -07:00 |
|
tangxifan
|
64698443c9
|
[core] fixed a bug on io location map for tile modules
|
2023-07-24 22:11:57 -07:00 |
|
tangxifan
|
2105abdbca
|
[core] fixed a bug
|
2023-07-24 21:26:29 -07:00 |
|
tangxifan
|
e7d714b94d
|
[core] fixed a bug on the tile module port addition: some grid output was not pulled out
|
2023-07-24 21:21:25 -07:00 |
|
tangxifan
|
b8d080b08e
|
[core] fixed a bug where undriven cb ports are not connected to tile
|
2023-07-24 20:40:25 -07:00 |
|
tangxifan
|
3745897ff6
|
[core] fixed a few bugs
|
2023-07-24 16:10:29 -07:00 |
|
tangxifan
|
48b0ba8b78
|
[core] format
|
2023-07-24 15:00:26 -07:00 |
|
tangxifan
|
4294914987
|
[core] fixed compiler warnings
|
2023-07-24 14:59:43 -07:00 |
|
tangxifan
|
812473ef04
|
[core] fixed the bug on io location map for tiled top module
|
2023-07-24 14:50:39 -07:00 |
|
tangxifan
|
da36b735c6
|
[core] syntax
|
2023-07-24 12:13:45 -07:00 |
|
tangxifan
|
f031148959
|
[core] syntax
|
2023-07-23 22:39:36 -07:00 |
|
tangxifan
|
f551188d0f
|
[core] developed tile directs to support tile modules
|
2023-07-23 21:45:45 -07:00 |
|
tangxifan
|
14666f3ae5
|
[core] sync
|
2023-07-23 20:45:59 -07:00 |
|
tangxifan
|
0b3b7b5472
|
[core] hotfix
|
2023-07-23 13:39:06 -07:00 |
|
tangxifan
|
1ee7448070
|
[core] supporting tile annotation (for global port) in tile modules
|
2023-07-23 13:38:16 -07:00 |
|
tangxifan
|
399259ea1d
|
[core] adding prog clock arch support for tile modules
|
2023-07-23 13:11:13 -07:00 |
|
tangxifan
|
0f3f4b0d81
|
[core] now tile module use unique port name (for heterogeneous blocks)
|
2023-07-22 23:55:54 -07:00 |
|
tangxifan
|
003d9515ff
|
[core] developing tile-based top module builder
|
2023-07-22 17:13:30 -07:00 |
|
tangxifan
|
93c5a68592
|
[core] developing top-level nets for tiles
|
2023-07-21 23:21:53 -07:00 |
|
Chung Shien Chai
|
6c03819c5f
|
100% limited new flow for flatten bl/wl protocol
|
2023-07-21 03:14:26 -07:00 |
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tangxifan
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fcf308fcd6
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[core] developing inter-tile connections for top module
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2023-07-20 23:00:35 -07:00 |
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Chung Shien Chai
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39934f9d16
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Address issue 1256
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2023-07-20 22:34:18 -07:00 |
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tangxifan
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b70f7fb1b6
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[core] now option conflicts in command 'build_fabric' can error out
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2023-07-20 21:22:07 -07:00 |
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tangxifan
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6b92299e39
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[core] start working on the net build-up for tile instances under the top-level module
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2023-07-20 17:38:13 -07:00 |
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tangxifan
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88c5d122ca
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[core] syntax
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2023-07-20 17:12:10 -07:00 |
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tangxifan
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db179ec4bb
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[core] split tile instance builder and the classic fine-grained builder
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2023-07-20 17:07:07 -07:00 |