riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] remove debugging messages

This commit is contained in:
tangxifan 2023-08-18 22:08:47 -07:00
parent 15a8d8a76a
commit 66cc375996
2 changed files with 0 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp
View File

@ -402,7 +402,6 @@ static void add_top_module_io_children(
/* Now walk through the coordinates */
for (vtr::Point<size_t> coord : coords) {
VTR_LOG("Adding coord [%lu][%lu]\n", coord.x(), coord.y());
t_physical_tile_loc phy_tile_loc(coord.x(), coord.y(), layer);
t_physical_tile_type_ptr grid_type = grids.get_physical_type(phy_tile_loc);
/* Bypass EMPTY grid */

2
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1387,8 +1387,6 @@ static int build_top_module_global_net_for_given_tile_module(
generate_tile_module_port_name(grid_instance_name, grid_port_name);
ModulePortId tile_grid_port_id =
module_manager.find_module_port(tile_module, tile_grid_port_name);
VTR_LOG("Finding global port '%s' from grid '%s'\n",
tile_grid_port_name.c_str(), tile_module_name.c_str());
VTR_ASSERT(true == module_manager.valid_module_port_id(
tile_module, tile_grid_port_id));