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[core] fixed some bugs

This commit is contained in:
tangxifan 2023-09-18 16:39:07 -07:00
parent 1daabb990e
commit a1e609c901
6 changed files with 33 additions and 14 deletions
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6
openfpga/src/fpga_bitstream/build_device_bitstream.cpp
View File

@ -169,8 +169,10 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
/* Create the core block when the fpga_core is added */
size_t num_blocks_to_reserve = 0;
std::string core_block_name =
openfpga_ctx.module_name_map().name(generate_fpga_core_module_name());
std::string core_block_name = generate_fpga_core_module_name();
if (openfpga_ctx.module_name_map().name_exist(core_block_name)) {
core_block_name = openfpga_ctx.module_name_map().name(core_block_name);
}
const ModuleId& core_module =
openfpga_ctx.module_graph().find_module(core_block_name);
if (openfpga_ctx.module_graph().valid_module_id(core_module)) {

6
openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
View File

@ -795,8 +795,10 @@ FabricBitstream build_fabric_dependent_bitstream(
ConfigBlockId top_block = top_blocks[0];
/* Create the core block when the fpga_core is added */
std::string core_block_name =
module_name_map.name(generate_fpga_core_module_name());
std::string core_block_name = generate_fpga_core_module_name();
if (module_name_map.name_exist(core_block_name)) {
core_block_name = module_name_map.name(core_block_name);
}
const ModuleId& core_module = module_manager.find_module(core_block_name);
if (module_manager.valid_module_id(core_module)) {
/* Now we use the core_block as the top-level block for the remaining

7
openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp
View File

@ -486,8 +486,11 @@ int print_verilog_mock_fpga_wrapper(
/* Note that we always need the core module as it contains the original port
* names before possible renaming at top-level module. If there is no core
* module, it means that the current top module is the core module */
ModuleId core_module = module_manager.find_module(
module_name_map.name(generate_fpga_core_module_name()));
std::string core_module_name = generate_fpga_core_module_name();
if (module_name_map.name_exist(core_module_name)) {
core_module_name = module_name_map.name(core_module_name);
}
ModuleId core_module = module_manager.find_module(core_module_name);
if (!module_manager.valid_module_id(core_module)) {
core_module = top_module;
}

7
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -586,8 +586,11 @@ int print_verilog_preconfig_top_module(
/* Note that we always need the core module as it contains the original port
* names before possible renaming at top-level module. If there is no core
* module, it means that the current top module is the core module */
ModuleId core_module = module_manager.find_module(
module_name_map.name(generate_fpga_core_module_name()));
std::string core_module_name = generate_fpga_core_module_name();
if (module_name_map.name_exist(core_module_name)) {
core_module_name = module_name_map.name(core_module_name);
}
ModuleId core_module = module_manager.find_module(core_module_name);
if (!module_manager.valid_module_id(core_module)) {
core_module = top_module;
}

7
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -2491,8 +2491,11 @@ int print_verilog_full_testbench(
/* Note that we always need the core module as it contains the original port
* names before possible renaming at top-level module. If there is no core
* module, it means that the current top module is the core module */
ModuleId core_module = module_manager.find_module(
module_name_map.name(generate_fpga_core_module_name()));
std::string core_module_name = generate_fpga_core_module_name();
if (module_name_map.name_exist(core_module_name)) {
core_module_name = module_name_map.name(core_module_name);
}
ModuleId core_module = module_manager.find_module(core_module_name);
if (!module_manager.valid_module_id(core_module)) {
core_module = top_module;
}

14
openfpga/src/utils/fabric_global_port_info_utils.cpp
View File

@ -80,8 +80,11 @@ bool port_is_fabric_global_reset_port(
ModuleId top_module = module_manager.find_module(
module_name_map.name(generate_fpga_top_module_name()));
VTR_ASSERT(true == module_manager.valid_module_id(top_module));
ModuleId core_module = module_manager.find_module(
module_name_map.name(generate_fpga_core_module_name()));
std::string core_module_name = generate_fpga_core_module_name();
if (module_name_map.name_exist(core_module_name)) {
core_module_name = module_name_map.name(core_module_name);
}
ModuleId core_module = module_manager.find_module(core_module_name);
if (module_manager.valid_module_id(core_module)) {
top_module = core_module;
}
@ -120,8 +123,11 @@ FabricGlobalPortId find_fabric_global_port(
ModuleId top_module = module_manager.find_module(
module_name_map.name(generate_fpga_top_module_name()));
VTR_ASSERT(true == module_manager.valid_module_id(top_module));
ModuleId core_module = module_manager.find_module(
module_name_map.name(generate_fpga_core_module_name()));
std::string core_module_name = generate_fpga_core_module_name();
if (module_name_map.name_exist(core_module_name)) {
core_module_name = module_name_map.name(core_module_name);
}
ModuleId core_module = module_manager.find_module(core_module_name);
if (module_manager.valid_module_id(core_module)) {
top_module = core_module;
}