riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] syntax

This commit is contained in:
tangxifan 2023-09-15 23:30:34 -07:00
parent bc407e5d69
commit c85c64eb5a
5 changed files with 8 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga/src/base/openfpga_build_fabric_template.h
View File

@ -346,7 +346,7 @@ int add_fpga_core_to_fabric_template(T& openfpga_ctx, const Command& cmd,
* Rename modules in module graph with a set of given rules
*******************************************************************/
template <class T>
int rename_modules_template(const T& openfpga_ctx, const Command& cmd,
int rename_modules_template(T& openfpga_ctx, const Command& cmd,
const CommandContext& cmd_context) {
CommandOptionId opt_verbose = cmd.option("verbose");

2
openfpga/src/base/openfpga_setup_command_template.h
View File

@ -812,7 +812,7 @@ ShellCommandId add_rename_modules_command_template(
ShellCommandId shell_cmd_id = shell.add_command(
shell_cmd, "Rename modules with a set of given rules", hidden);
shell.set_command_class(shell_cmd_id, cmd_class_id);
shell.set_command_const_execute_function(shell_cmd_id,
shell.set_command_execute_function(shell_cmd_id,
rename_modules_template<T>);
/* Add command dependency to the Shell */

2
openfpga/src/fabric/build_device_module.cpp
View File

@ -162,7 +162,7 @@ int build_device_module_graph(
}
if (name_module_using_index) {
/* Update module name data */
status = update_module_map_name_with_indexing_names(module_name_map, device_rr_gsb, fabric_tile, verbose);
status = update_module_map_name_with_indexing_names(module_name_map, openfpga_ctx.device_rr_gsb(), fabric_tile, verbose);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}

3
openfpga/src/fabric/build_device_module.h
View File

@ -7,6 +7,7 @@
#include "fabric_key.h"
#include "fabric_tile.h"
#include "io_name_map.h"
#include "module_name_map.h"
#include "openfpga_context.h"
#include "tile_config.h"
#include "vpr_context.h"
@ -21,10 +22,12 @@ namespace openfpga {
int build_device_module_graph(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
MemoryBankShiftRegisterBanks& blwl_sr_banks, FabricTile& fabric_tile,
ModuleNameMap& module_name_map,
const OpenfpgaContext& openfpga_ctx, const DeviceContext& vpr_device_ctx,
const bool& frame_view, const bool& compress_routing,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const TileConfig& tile_config, const bool& group_config_block,
const bool& name_module_using_index,
const bool& generate_random_fabric_key, const bool& verbose);
} /* end namespace openfpga */

4
openfpga/src/fabric/rename_modules.cpp
View File

@ -64,7 +64,7 @@ int update_module_map_name_with_indexing_names(ModuleNameMap& module_name_map, c
FabricTileId fabric_tile_id = fabric_tile.unique_tiles()[itile];
vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(fabric_tile_id);
std::string name_using_coord = generate_tile_module_name(tile_coord);
std::string name_using_index = generate_tile_module_name_using_index(tile_coord, itile);
std::string name_using_index = generate_tile_module_name_using_index(itile);
status = module_name_map.set_tag_to_name_pair(name_using_coord, name_using_index);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_SUCCESS;
@ -79,7 +79,7 @@ int rename_fabric_modules(ModuleManager& module_manager, const ModuleNameMap& mo
size_t cnt = 0;
for (ModuleId curr_module : module_manager.modules()) {
std::string new_name = module_name_map.name(module_manager.module_name(curr_module));
if (new_name != module_manager.module_name()) {
if (new_name != module_manager.module_name(curr_module)) {
VTR_LOGV(verbose, "Rename module '%s' to its new name '%s'\n", module_manager.module_name(curr_module).c_str(), new_name.c_str());
module_manager.set_module_name(curr_module, new_name);
}