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[core] code format

This commit is contained in:
tangxifan 2023-09-17 22:37:48 -07:00
parent ef97127c63
commit c6175aa514
13 changed files with 90 additions and 97 deletions
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3
libs/libnamemanager/src/base/module_name_map.h
View File

@ -19,7 +19,8 @@ class ModuleNameMap {
public: /* Public accessors */
/** @brief Get customized name with a given tag */
std::string name(const std::string& tag) const;
/** @brief Check if a name does exist with a given tag. Return true if there is a tag-to-name mapping */
/** @brief Check if a name does exist with a given tag. Return true if there
* is a tag-to-name mapping */
bool name_exist(const std::string& tag) const;
/** @brief return a list of all the current keys */
std::vector<std::string> tags() const;

3
openfpga/src/base/openfpga_verilog_template.h
View File

@ -335,7 +335,8 @@ int write_preconfigured_testbench_template(const T& openfpga_ctx,
}
return fpga_verilog_preconfigured_testbench(
openfpga_ctx.module_graph(), openfpga_ctx.module_name_map(), g_vpr_ctx.atom(), pin_constraints, bus_group,
openfpga_ctx.module_graph(), openfpga_ctx.module_name_map(),
g_vpr_ctx.atom(), pin_constraints, bus_group,
openfpga_ctx.fabric_global_port_info(),
openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.simulation_setting(),
options);

11
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -319,10 +319,9 @@ int fpga_verilog_mock_fpga_wrapper(
*verification and formal verification purpose.
********************************************************************/
int fpga_verilog_preconfigured_testbench(
const ModuleManager &module_manager,
const ModuleNameMap &module_name_map,
const AtomContext &atom_ctx,
const PinConstraints &pin_constraints, const BusGroup &bus_group,
const ModuleManager &module_manager, const ModuleNameMap &module_name_map,
const AtomContext &atom_ctx, const PinConstraints &pin_constraints,
const BusGroup &bus_group,
const FabricGlobalPortInfo &fabric_global_port_info,
const VprNetlistAnnotation &netlist_annotation,
const SimulationSetting &simulation_setting,
@ -345,8 +344,8 @@ int fpga_verilog_preconfigured_testbench(
std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
print_verilog_random_top_testbench(
netlist_name, random_top_testbench_file_path, atom_ctx, netlist_annotation,
module_manager, module_name_map, fabric_global_port_info, pin_constraints, bus_group,
simulation_setting, options);
module_manager, module_name_map, fabric_global_port_info, pin_constraints,
bus_group, simulation_setting, options);
/* Generate a Verilog file including all the netlists that have been generated
*/

7
openfpga/src/fpga_verilog/verilog_api.h
View File

@ -84,10 +84,9 @@ int fpga_verilog_mock_fpga_wrapper(
const VerilogTestbenchOption& options);
int fpga_verilog_preconfigured_testbench(
const ModuleManager& module_manager,
const ModuleNameMap &module_name_map,
const AtomContext& atom_ctx,
const PinConstraints& pin_constraints, const BusGroup& bus_group,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
const AtomContext& atom_ctx, const PinConstraints& pin_constraints,
const BusGroup& bus_group,
const FabricGlobalPortInfo& fabric_global_port_info,
const VprNetlistAnnotation& netlist_annotation,
const SimulationSetting& simulation_setting,

44
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -52,8 +52,7 @@ constexpr const char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start";
*******************************************************************/
static void print_verilog_top_random_testbench_ports(
std::fstream& fp, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const std::string& circuit_name,
const ModuleNameMap& module_name_map, const std::string& circuit_name,
const std::vector<std::string>& clock_port_names, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const VerilogTestbenchOption& options) {
@ -83,10 +82,11 @@ static void print_verilog_top_random_testbench_ports(
fp << std::endl;
print_verilog_testbench_shared_ports(
fp, module_manager, module_name_map, FabricGlobalPortInfo(), PinConstraints(), atom_ctx,
netlist_annotation, clock_port_names, std::string(),
std::string(BENCHMARK_PORT_POSTFIX), std::string(FPGA_PORT_POSTFIX),
std::string(CHECKFLAG_PORT_POSTFIX), options.no_self_checking());
fp, module_manager, module_name_map, FabricGlobalPortInfo(),
PinConstraints(), atom_ctx, netlist_annotation, clock_port_names,
std::string(), std::string(BENCHMARK_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX), std::string(CHECKFLAG_PORT_POSTFIX),
options.no_self_checking());
/* Instantiate an integer to count the number of error
* and determine if the simulation succeed or failed
@ -169,8 +169,7 @@ static void print_verilog_random_testbench_fpga_instance(
static void print_verilog_random_testbench_reset_stimuli(
std::fstream& fp, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
const FabricGlobalPortInfo& global_ports,
const PinConstraints& pin_constraints,
const std::vector<std::string>& clock_port_names,
@ -202,18 +201,18 @@ static void print_verilog_random_testbench_reset_stimuli(
/* Bypass any constained net that are mapped to a global port of the FPGA
* fabric because their stimulus cannot be random
*/
if (false ==
port_is_fabric_global_reset_port(global_ports, module_manager, module_name_map,
pin_constraints.net_pin(block_name))) {
if (false == port_is_fabric_global_reset_port(
global_ports, module_manager, module_name_map,
pin_constraints.net_pin(block_name))) {
continue;
}
/* Generete stimuli for this net which is how reset signal works */
BasicPort reset_port(block_name, 1);
size_t initial_value = 1;
if (1 ==
global_ports.global_port_default_value(find_fabric_global_port(
global_ports, module_manager, module_name_map, pin_constraints.net_pin(block_name)))) {
if (1 == global_ports.global_port_default_value(find_fabric_global_port(
global_ports, module_manager, module_name_map,
pin_constraints.net_pin(block_name)))) {
initial_value = 0;
}
@ -273,8 +272,7 @@ static void print_verilog_random_testbench_reset_stimuli(
void print_verilog_random_top_testbench(
const std::string& circuit_name, const std::string& verilog_fname,
const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation,
const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
const FabricGlobalPortInfo& global_ports,
const PinConstraints& pin_constraints, const BusGroup& bus_group,
const SimulationSetting& simulation_parameters,
@ -306,9 +304,9 @@ void print_verilog_random_top_testbench(
find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
/* Start of testbench */
print_verilog_top_random_testbench_ports(fp, module_manager, module_name_map, circuit_name,
clock_port_names, atom_ctx,
netlist_annotation, options);
print_verilog_top_random_testbench_ports(
fp, module_manager, module_name_map, circuit_name, clock_port_names,
atom_ctx, netlist_annotation, options);
/* Call defined top-level module */
print_verilog_random_testbench_fpga_instance(
@ -334,12 +332,12 @@ void print_verilog_random_top_testbench(
* limitation should be removed!
*/
print_verilog_random_testbench_reset_stimuli(
fp, atom_ctx, netlist_annotation, module_manager, module_name_map, global_ports,
pin_constraints, clock_port_names, clock_ports[0]);
fp, atom_ctx, netlist_annotation, module_manager, module_name_map,
global_ports, pin_constraints, clock_port_names, clock_ports[0]);
print_verilog_testbench_random_stimuli(
fp, atom_ctx, netlist_annotation, module_manager, module_name_map, global_ports,
pin_constraints, clock_port_names, std::string(),
fp, atom_ctx, netlist_annotation, module_manager, module_name_map,
global_ports, pin_constraints, clock_port_names, std::string(),
std::string(CHECKFLAG_PORT_POSTFIX), clock_ports,
options.no_self_checking());

3
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
View File

@ -26,8 +26,7 @@ namespace openfpga {
void print_verilog_random_top_testbench(
const std::string& circuit_name, const std::string& verilog_fname,
const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation,
const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
const FabricGlobalPortInfo& global_ports,
const PinConstraints& pin_constraints, const BusGroup& bus_group,
const SimulationSetting& simulation_parameters,

15
openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp
View File

@ -44,7 +44,8 @@ static void print_verilog_mock_fpga_wrapper_connect_ios(
std::fstream& fp, const ModuleManager& module_manager,
const ModuleId& top_module, const AtomContext& atom_ctx,
const PlacementContext& place_ctx, const IoLocationMap& io_location_map,
const IoNameMap& io_name_map, const ModuleNameMap& module_name_map, const PinConstraints& pin_constraints,
const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
const PinConstraints& pin_constraints,
const FabricGlobalPortInfo& global_ports,
const VprNetlistAnnotation& netlist_annotation,
const std::string& net_name_postfix,
@ -189,8 +190,8 @@ static void print_verilog_mock_fpga_wrapper_connect_ios(
}
/* For global ports, use wires; otherwise, use registers*/
if (true == port_is_fabric_global_reset_port(
global_ports, module_manager,
module_name_map, pin_constraints.net_pin(block_name))) {
global_ports, module_manager, module_name_map,
pin_constraints.net_pin(block_name))) {
continue;
}
@ -516,8 +517,8 @@ int print_verilog_mock_fpga_wrapper(
/* Print local wires */
print_verilog_testbench_shared_input_ports(
fp, module_manager, module_name_map, global_ports, pin_constraints, atom_ctx,
netlist_annotation, benchmark_clock_port_names, true,
fp, module_manager, module_name_map, global_ports, pin_constraints,
atom_ctx, netlist_annotation, benchmark_clock_port_names, true,
std::string(APPINST_PORT_POSTFIX), false);
print_verilog_testbench_shared_benchmark_output_ports(
@ -543,8 +544,8 @@ int print_verilog_mock_fpga_wrapper(
/* Connect I/Os to benchmark I/Os or constant driver */
print_verilog_mock_fpga_wrapper_connect_ios(
fp, module_manager, core_module, atom_ctx, place_ctx, io_location_map,
require_io_naming ? io_name_map : IoNameMap(), module_name_map, pin_constraints,
global_ports, netlist_annotation, std::string(),
require_io_naming ? io_name_map : IoNameMap(), module_name_map,
pin_constraints, global_ports, netlist_annotation, std::string(),
std::string(APPINST_PORT_POSTFIX), std::string(APPINST_PORT_POSTFIX),
benchmark_clock_port_names, (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);

4
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -633,8 +633,8 @@ int print_verilog_preconfig_top_module(
*/
std::string inst_name = module_name_map.name(generate_fpga_top_module_name());
if (options.dut_module() == generate_fpga_core_module_name()) {
ModuleId parent_module =
module_manager.find_module(module_name_map.name(generate_fpga_top_module_name()));
ModuleId parent_module = module_manager.find_module(
module_name_map.name(generate_fpga_top_module_name()));
inst_name = module_manager.instance_name(parent_module, core_module, 0);
}

27
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -818,8 +818,7 @@ void print_verilog_testbench_clock_stimuli(
void print_verilog_testbench_random_stimuli(
std::fstream& fp, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
const FabricGlobalPortInfo& global_ports,
const PinConstraints& pin_constraints,
const std::vector<std::string>& clock_port_names,
@ -860,9 +859,9 @@ void print_verilog_testbench_random_stimuli(
/* Bypass any constained net that are mapped to a global port of the FPGA
* fabric because their stimulus cannot be random
*/
if (true ==
port_is_fabric_global_reset_port(global_ports, module_manager,
module_name_map, pin_constraints.net_pin(block_name))) {
if (true == port_is_fabric_global_reset_port(
global_ports, module_manager, module_name_map,
pin_constraints.net_pin(block_name))) {
continue;
}
@ -944,9 +943,9 @@ void print_verilog_testbench_random_stimuli(
/* Bypass any constained net that are mapped to a global port of the FPGA
* fabric because their stimulus cannot be random
*/
if (true ==
port_is_fabric_global_reset_port(global_ports, module_manager, module_name_map,
pin_constraints.net_pin(block_name))) {
if (true == port_is_fabric_global_reset_port(
global_ports, module_manager, module_name_map,
pin_constraints.net_pin(block_name))) {
continue;
}
@ -1009,9 +1008,9 @@ void print_verilog_testbench_shared_input_ports(
/* Each logical block assumes a single-width port */
BasicPort input_port(block_name + shared_input_port_postfix, 1);
/* For global ports, use wires; otherwise, use registers*/
if (false ==
port_is_fabric_global_reset_port(global_ports, module_manager,
module_name_map, pin_constraints.net_pin(block_name))) {
if (false == port_is_fabric_global_reset_port(
global_ports, module_manager, module_name_map,
pin_constraints.net_pin(block_name))) {
if (use_reg_port) {
fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";"
<< std::endl;
@ -1172,9 +1171,9 @@ void print_verilog_testbench_shared_ports(
const std::string& fpga_output_port_postfix,
const std::string& check_flag_port_postfix, const bool& no_self_checking) {
print_verilog_testbench_shared_input_ports(
fp, module_manager, module_name_map, global_ports, pin_constraints, atom_ctx,
netlist_annotation, clock_port_names, false, shared_input_port_postfix,
true);
fp, module_manager, module_name_map, global_ports, pin_constraints,
atom_ctx, netlist_annotation, clock_port_names, false,
shared_input_port_postfix, true);
print_verilog_testbench_shared_fpga_output_ports(
fp, atom_ctx, netlist_annotation, fpga_output_port_postfix);

5
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -13,8 +13,8 @@
#include "fabric_global_port_info.h"
#include "io_location_map.h"
#include "io_name_map.h"
#include "module_name_map.h"
#include "module_manager.h"
#include "module_name_map.h"
#include "pin_constraints.h"
#include "simulation_setting.h"
#include "vpr_context.h"
@ -85,8 +85,7 @@ void print_verilog_testbench_clock_stimuli(
void print_verilog_testbench_random_stimuli(
std::fstream& fp, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
const FabricGlobalPortInfo& global_ports,
const PinConstraints& pin_constraints,
const std::vector<std::string>& clock_port_names,

40
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -801,9 +801,8 @@ static void print_verilog_top_testbench_benchmark_clock_ports(
*******************************************************************/
static void print_verilog_top_testbench_ports(
std::fstream& fp, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const ModuleId& top_module, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const ModuleNameMap& module_name_map, const ModuleId& top_module,
const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const FabricGlobalPortInfo& global_ports,
const PinConstraints& pin_constraints,
@ -951,8 +950,8 @@ static void print_verilog_top_testbench_ports(
std::vector<std::string> global_port_names;
print_verilog_testbench_shared_ports(
fp, module_manager, module_name_map, global_ports, pin_constraints, atom_ctx,
netlist_annotation, clock_port_names,
fp, module_manager, module_name_map, global_ports, pin_constraints,
atom_ctx, netlist_annotation, clock_port_names,
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
@ -2337,8 +2336,7 @@ static void print_verilog_full_testbench_bitstream(
static void print_verilog_top_testbench_reset_stimuli(
std::fstream& fp, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
const FabricGlobalPortInfo& global_ports,
const PinConstraints& pin_constraints, const std::string& port_name_postfix,
const std::vector<std::string>& clock_port_names) {
@ -2369,15 +2367,15 @@ static void print_verilog_top_testbench_reset_stimuli(
/* Bypass any constained net that are mapped to a global port of the FPGA
* fabric because their stimulus cannot be random
*/
if (false ==
port_is_fabric_global_reset_port(global_ports, module_manager,
module_name_map, pin_constraints.net_pin(block_name))) {
if (false == port_is_fabric_global_reset_port(
global_ports, module_manager, module_name_map,
pin_constraints.net_pin(block_name))) {
continue;
}
size_t initial_value =
global_ports.global_port_default_value(find_fabric_global_port(
global_ports, module_manager, module_name_map, pin_constraints.net_pin(block_name)));
size_t initial_value = global_ports.global_port_default_value(
find_fabric_global_port(global_ports, module_manager, module_name_map,
pin_constraints.net_pin(block_name)));
/* Connect stimuli to greset with an optional inversion, depending on the
* default value */
@ -2521,9 +2519,9 @@ int print_verilog_full_testbench(
/* Start of testbench */
print_verilog_top_testbench_ports(
fp, module_manager, module_name_map, core_module, atom_ctx, netlist_annotation,
clock_port_names, global_ports, pin_constraints, simulation_parameters,
config_protocol, circuit_name, options);
fp, module_manager, module_name_map, core_module, atom_ctx,
netlist_annotation, clock_port_names, global_ports, pin_constraints,
simulation_parameters, config_protocol, circuit_name, options);
/* Find the clock period */
float prog_clock_period =
@ -2629,12 +2627,12 @@ int print_verilog_full_testbench(
/* Add stimuli for reset, set, clock and iopad signals */
print_verilog_top_testbench_reset_stimuli(
fp, atom_ctx, netlist_annotation, module_manager, module_name_map, global_ports,
pin_constraints, std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
clock_port_names);
fp, atom_ctx, netlist_annotation, module_manager, module_name_map,
global_ports, pin_constraints,
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX), clock_port_names);
print_verilog_testbench_random_stimuli(
fp, atom_ctx, netlist_annotation, module_manager, module_name_map, global_ports,
pin_constraints, clock_port_names,
fp, atom_ctx, netlist_annotation, module_manager, module_name_map,
global_ports, pin_constraints, clock_port_names,
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::vector<BasicPort>(

22
openfpga/src/utils/fabric_global_port_info_utils.cpp
View File

@ -72,15 +72,16 @@ std::vector<FabricGlobalPortId> find_fabric_global_programming_set_ports(
*******************************************************************/
bool port_is_fabric_global_reset_port(
const FabricGlobalPortInfo& fabric_global_port_info,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map, const BasicPort& port) {
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
const BasicPort& port) {
/* Find the top_module: the fabric global ports are always part of the ports
* of the top/core module. If there is a core module, we should consider core
* only */
ModuleId top_module =
module_manager.find_module(module_name_map.name(generate_fpga_top_module_name()));
ModuleId top_module = module_manager.find_module(
module_name_map.name(generate_fpga_top_module_name()));
VTR_ASSERT(true == module_manager.valid_module_id(top_module));
ModuleId core_module =
module_manager.find_module(module_name_map.name(generate_fpga_core_module_name()));
ModuleId core_module = module_manager.find_module(
module_name_map.name(generate_fpga_core_module_name()));
if (module_manager.valid_module_id(core_module)) {
top_module = core_module;
}
@ -111,17 +112,16 @@ bool port_is_fabric_global_reset_port(
*******************************************************************/
FabricGlobalPortId find_fabric_global_port(
const FabricGlobalPortInfo& fabric_global_port_info,
const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
const BasicPort& port) {
/* Find the top_module: the fabric global ports are always part of the ports
* of the top/core module. If there is a core module, we should consider core
* only */
ModuleId top_module =
module_manager.find_module(module_name_map.name(generate_fpga_top_module_name()));
ModuleId top_module = module_manager.find_module(
module_name_map.name(generate_fpga_top_module_name()));
VTR_ASSERT(true == module_manager.valid_module_id(top_module));
ModuleId core_module =
module_manager.find_module(module_name_map.name(generate_fpga_core_module_name()));
ModuleId core_module = module_manager.find_module(
module_name_map.name(generate_fpga_core_module_name()));
if (module_manager.valid_module_id(core_module)) {
top_module = core_module;
}

3
openfpga/src/utils/fabric_global_port_info_utils.h
View File

@ -30,8 +30,7 @@ bool port_is_fabric_global_reset_port(
FabricGlobalPortId find_fabric_global_port(
const FabricGlobalPortInfo& fabric_global_port_info,
const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
const BasicPort& port);
} /* end namespace openfpga */