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[core] now support tile port merge

This commit is contained in:
tangxifan 2023-09-25 18:16:24 -07:00
parent 3adf81046a
commit dbd466cdec
2 changed files with 10 additions and 0 deletions
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5
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1398,6 +1398,11 @@ static int build_top_module_global_net_for_given_tile_module(
vpr_device_annotation.physical_tile_pin_port_info(physical_tile,
grid_pin_index);
VTR_ASSERT(true == grid_pin_info.is_valid());
if (tile_annotation.is_tile_port_to_merge(
std::string(physical_tile->name), grid_pin_info.get_name()) &&
subtile_index != 0) {
continue;
}
/* Build nets */
for (const e_side& pin_side : pin_sides) {

5
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -944,6 +944,11 @@ static int build_top_module_global_net_for_given_grid_module(
vpr_device_annotation.physical_tile_pin_port_info(physical_tile,
grid_pin_index);
VTR_ASSERT(true == grid_pin_info.is_valid());
if (tile_annotation.is_tile_port_to_merge(
std::string(physical_tile->name), grid_pin_info.get_name()) &&
subtile_index != 0) {
continue;
}
/* Build nets */
for (const e_side& pin_side : pin_sides) {