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[core] code format

This commit is contained in:
tangxifan 2023-09-25 17:22:26 -07:00
parent 5e269e8bc4
commit 3adf81046a
8 changed files with 52 additions and 56 deletions
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5
libs/libarchopenfpga/src/tile_annotation.cpp
View File

@ -102,13 +102,14 @@ std::string TileAnnotation::global_port_clock_arch_tree_name(
return global_port_clock_arch_tree_names_[global_port_id];
}
bool TileAnnotation::is_tile_port_to_merge(const std::string& tile_name, const std::string& port_name) const {
bool TileAnnotation::is_tile_port_to_merge(const std::string& tile_name,
const std::string& port_name) const {
const auto& result = tile_ports_to_merge_.find(tile_name);
if (result == tile_ports_to_merge_.end()) {
return false;
}
return result->second.end() ==
std::find(result->second.begin(), result->second.end(), port_name);
std::find(result->second.begin(), result->second.end(), port_name);
}
/************************************************************************

3
libs/libarchopenfpga/src/tile_annotation.h
View File

@ -60,7 +60,8 @@ class TileAnnotation {
const TileGlobalPortId& global_port_id) const;
/** @brief Check if a given tile port should be merged or not */
bool is_tile_port_to_merge(const std::string& tile_name, const std::string& port_name) const;
bool is_tile_port_to_merge(const std::string& tile_name,
const std::string& port_name) const;
public: /* Public mutators */
/* By default, we do not set it as a clock.

7
openfpga/src/fabric/build_device_module.cpp
View File

@ -87,10 +87,9 @@ int build_device_module_graph(
status = build_grid_modules(
module_manager, decoder_lib, vpr_device_ctx,
openfpga_ctx.vpr_device_annotation(), openfpga_ctx.arch().circuit_lib,
openfpga_ctx.mux_lib(),
openfpga_ctx.arch().tile_annotations,
openfpga_ctx.arch().config_protocol.type(),
sram_model, duplicate_grid_pin, group_config_block, verbose);
openfpga_ctx.mux_lib(), openfpga_ctx.arch().tile_annotations,
openfpga_ctx.arch().config_protocol.type(), sram_model, duplicate_grid_pin,
group_config_block, verbose);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}

23
openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
View File

@ -55,8 +55,7 @@ void add_grid_module_duplicated_pb_type_ports(
ModuleManager& module_manager, const ModuleId& grid_module,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation,
const e_side& border_side) {
const TileAnnotation& tile_annotation, const e_side& border_side) {
/* Ensure that we have a valid grid_type_descriptor */
VTR_ASSERT(false == is_empty_type(grid_type_descriptor));
@ -100,8 +99,11 @@ void add_grid_module_duplicated_pb_type_ports(
grid_type_descriptor, ipin);
VTR_ASSERT(OPEN != subtile_index &&
subtile_index < grid_type_descriptor->capacity);
/* If the port is required to be merged, we deposit zero as subtile index */
if (tile_annotation.is_tile_port_to_merge(std::string(grid_type_descriptor->name), pin_info.get_name()) && subtile_index != 0) {
/* If the port is required to be merged, we deposit zero as subtile
* index */
if (tile_annotation.is_tile_port_to_merge(
std::string(grid_type_descriptor->name), pin_info.get_name()) &&
subtile_index != 0) {
continue;
}
/* Generate the pin name
@ -304,8 +306,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(
const ModuleId& child_module, const size_t& child_instance,
const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation,
const e_side& border_side) {
const TileAnnotation& tile_annotation, const e_side& border_side) {
/* Ensure that we have a valid grid_type_descriptor */
VTR_ASSERT(false == is_empty_type(grid_type_descriptor));
@ -322,9 +323,8 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
tile_annotation,
&(top_pb_graph_node->input_pins[iport][ipin]), border_side,
INPUT2INPUT_INTERC);
tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]),
border_side, INPUT2INPUT_INTERC);
}
}
@ -345,9 +345,8 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
tile_annotation,
&(top_pb_graph_node->clock_pins[iport][ipin]), border_side,
INPUT2INPUT_INTERC);
tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]),
border_side, INPUT2INPUT_INTERC);
}
}
}

6
openfpga/src/fabric/build_grid_module_duplicated_pins.h
View File

@ -21,16 +21,14 @@ void add_grid_module_duplicated_pb_type_ports(
ModuleManager& module_manager, const ModuleId& grid_module,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation,
const e_side& border_side);
const TileAnnotation& tile_annotation, const e_side& border_side);
void add_grid_module_nets_connect_duplicated_pb_type_ports(
ModuleManager& module_manager, const ModuleId& grid_module,
const ModuleId& child_module, const size_t& child_instance,
const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation,
const e_side& border_side);
const TileAnnotation& tile_annotation, const e_side& border_side);
} /* end namespace openfpga */

9
openfpga/src/fabric/build_grid_module_utils.cpp
View File

@ -46,8 +46,7 @@ void add_grid_module_net_connect_pb_graph_pin(
const size_t& child_inst_subtile_index,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation,
t_pb_graph_pin* pb_graph_pin,
const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin,
const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) {
/* Find the pin side for I/O grids*/
std::vector<e_side> grid_pin_sides;
@ -91,8 +90,10 @@ void add_grid_module_net_connect_pb_graph_pin(
grid_type_descriptor, grid_pin_index);
VTR_ASSERT(OPEN != subtile_index &&
subtile_index < grid_type_descriptor->capacity);
/* If the port is required to be merged, we only consider the source port to be the subtile index of 0 */
if (tile_annotation.is_tile_port_to_merge(std::string(grid_type_descriptor->name), pin_info.get_name())) {
/* If the port is required to be merged, we only consider the source port to
* be the subtile index of 0 */
if (tile_annotation.is_tile_port_to_merge(
std::string(grid_type_descriptor->name), pin_info.get_name())) {
subtile_index = 0;
}
std::string grid_port_name = generate_grid_port_name(

5
openfpga/src/fabric/build_grid_module_utils.h
View File

@ -8,8 +8,8 @@
#include "module_manager.h"
#include "openfpga_interconnect_types.h"
#include "physical_types.h"
#include "vpr_device_annotation.h"
#include "tile_annotation.h"
#include "vpr_device_annotation.h"
/********************************************************************
* Function declaration
@ -27,8 +27,7 @@ void add_grid_module_net_connect_pb_graph_pin(
const size_t& child_inst_subtile_index,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation,
t_pb_graph_pin* pb_graph_pin,
const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin,
const e_side& border_side,
const enum e_pin2pin_interc_type& pin2pin_interc_type);

50
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -41,9 +41,8 @@ namespace openfpga {
static void add_grid_module_pb_type_ports(
ModuleManager& module_manager, const ModuleId& grid_module,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation,
const e_side& border_side) {
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation, const e_side& border_side) {
/* Ensure that we have a valid grid_type_descriptor */
VTR_ASSERT(nullptr != grid_type_descriptor);
@ -88,8 +87,11 @@ static void add_grid_module_pb_type_ports(
int subtile_index =
vpr_device_annotation.physical_tile_pin_subtile_index(
grid_type_descriptor, ipin);
/* If the port is required to be merged, we deposit zero as subtile index */
if (tile_annotation.is_tile_port_to_merge(std::string(grid_type_descriptor->name), pin_info.get_name()) && subtile_index != 0) {
/* If the port is required to be merged, we deposit zero as subtile
* index */
if (tile_annotation.is_tile_port_to_merge(
std::string(grid_type_descriptor->name), pin_info.get_name()) &&
subtile_index != 0) {
continue;
}
VTR_ASSERT(OPEN != subtile_index &&
@ -118,8 +120,7 @@ static void add_grid_module_nets_connect_pb_type_ports(
const ModuleId& child_module, const size_t& child_instance,
const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation,
const e_side& border_side) {
const TileAnnotation& tile_annotation, const e_side& border_side) {
/* Ensure that we have a valid grid_type_descriptor */
VTR_ASSERT(nullptr != grid_type_descriptor);
@ -137,9 +138,8 @@ static void add_grid_module_nets_connect_pb_type_ports(
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
tile_annotation,
&(top_pb_graph_node->input_pins[iport][ipin]), border_side,
INPUT2INPUT_INTERC);
tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]),
border_side, INPUT2INPUT_INTERC);
}
}
@ -149,9 +149,8 @@ static void add_grid_module_nets_connect_pb_type_ports(
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
tile_annotation,
&(top_pb_graph_node->output_pins[iport][ipin]), border_side,
OUTPUT2OUTPUT_INTERC);
tile_annotation, &(top_pb_graph_node->output_pins[iport][ipin]),
border_side, OUTPUT2OUTPUT_INTERC);
}
}
@ -161,9 +160,8 @@ static void add_grid_module_nets_connect_pb_type_ports(
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
tile_annotation,
&(top_pb_graph_node->clock_pins[iport][ipin]), border_side,
INPUT2INPUT_INTERC);
tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]),
border_side, INPUT2INPUT_INTERC);
}
}
}
@ -1162,9 +1160,9 @@ static int build_physical_tile_module(
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model, t_physical_tile_type_ptr phy_block_type,
const TileAnnotation& tile_annotation,
const e_side& border_side, const bool& duplicate_grid_pin,
const bool& group_config_block, const bool& verbose) {
const TileAnnotation& tile_annotation, const e_side& border_side,
const bool& duplicate_grid_pin, const bool& group_config_block,
const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
/* Create a Module for the top-level physical block, and add to module manager
*/
@ -1242,8 +1240,8 @@ static int build_physical_tile_module(
if (false == duplicate_grid_pin) {
/* Default way to add these ports by following the definition in pb_types */
add_grid_module_pb_type_ports(module_manager, grid_module,
vpr_device_annotation, phy_block_type, tile_annotation,
border_side);
vpr_device_annotation, phy_block_type,
tile_annotation, border_side);
/* Add module nets to connect the pb_type ports to sub modules */
for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) {
VTR_ASSERT(sub_tile.equivalent_sites.size() == 1);
@ -1266,9 +1264,9 @@ static int build_physical_tile_module(
} else {
VTR_ASSERT_SAFE(true == duplicate_grid_pin);
/* Add these ports with duplication */
add_grid_module_duplicated_pb_type_ports(module_manager, grid_module,
vpr_device_annotation,
phy_block_type, tile_annotation, border_side);
add_grid_module_duplicated_pb_type_ports(
module_manager, grid_module, vpr_device_annotation, phy_block_type,
tile_annotation, border_side);
/* Add module nets to connect the duplicated pb_type ports to sub modules */
for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) {
@ -1427,8 +1425,8 @@ int build_grid_modules(
for (const e_side& io_type_side : io_type_sides) {
status = build_physical_tile_module(
module_manager, decoder_lib, device_annotation, circuit_lib,
sram_orgz_type, sram_model, &physical_tile, tile_annotation, io_type_side,
duplicate_grid_pin, group_config_block, verbose);
sram_orgz_type, sram_model, &physical_tile, tile_annotation,
io_type_side, duplicate_grid_pin, group_config_block, verbose);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}