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[core] fixed the bug in arch bitgen due to the tile modules

This commit is contained in:
tangxifan 2023-07-25 14:15:15 -07:00
parent 64698443c9
commit 95a32628ab
7 changed files with 116 additions and 38 deletions
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17
libs/libfpgabitstream/src/bitstream_manager.cpp
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@ -6,6 +6,7 @@
#include <algorithm>
#include "vtr_assert.h"
#include "vtr_log.h"
/* begin namespace openfpga */
namespace openfpga {
@ -200,10 +201,20 @@ ConfigBlockId BitstreamManager::create_block() {
}
ConfigBlockId BitstreamManager::add_block(const std::string& block_name) {
ConfigBlockId block = create_block();
set_block_name(block, block_name);
ConfigBlockId new_block = create_block();
set_block_name(new_block, block_name);
return new_block;
}
return block;
ConfigBlockId BitstreamManager::find_or_create_child_block(
const ConfigBlockId& block_id, const std::string& child_block_name) {
ConfigBlockId curr_block = find_child_block(block_id, child_block_name);
if (valid_block_id(curr_block)) {
return curr_block;
}
curr_block = add_block(child_block_name);
add_child_block(block_id, curr_block);
return curr_block;
}
void BitstreamManager::set_block_name(const ConfigBlockId& block_id,

8
libs/libfpgabitstream/src/bitstream_manager.h
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@ -181,6 +181,11 @@ class BitstreamManager {
/* Add a new block of configuration bits to the bitstream manager */
ConfigBlockId add_block(const std::string& block_name);
/* Try to find the child block in a bitstream manager with a given name. If
* not found, create a new child block */
ConfigBlockId find_or_create_child_block(const ConfigBlockId& block_id,
const std::string& child_block_name);
/* Set a name for a block */
void set_block_name(const ConfigBlockId& block_id,
const std::string& block_name);
@ -234,6 +239,9 @@ class BitstreamManager {
vtr::vector<ConfigBlockId, ConfigBlockId> parent_block_ids_;
vtr::vector<ConfigBlockId, std::vector<ConfigBlockId>> child_block_ids_;
/* Fast look-up by block name to ids */
std::map<std::string, ConfigBlockId> block_name2ids_;
/* The ids of the inputs of routing multiplexer blocks which is propagated to
* outputs By default, it will be -2 (which is invalid) A valid id starts from
* -1 -1 indicates an unused routing multiplexer. It will be converted to a

18
openfpga/src/fpga_bitstream/build_device_bitstream.cpp
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@ -197,20 +197,22 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
/* Create bitstream from grids */
VTR_LOGV(verbose, "Building grid bitstream...\n");
build_grid_bitstream(
bitstream_manager, top_block, openfpga_ctx.module_graph(),
openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(),
vpr_ctx.device().grid, vpr_ctx.atom(), openfpga_ctx.vpr_device_annotation(),
openfpga_ctx.vpr_clustering_annotation(),
openfpga_ctx.vpr_placement_annotation(),
openfpga_ctx.vpr_bitstream_annotation(), verbose);
build_grid_bitstream(bitstream_manager, top_block,
openfpga_ctx.module_graph(), openfpga_ctx.fabric_tile(),
openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(),
vpr_ctx.device().grid, vpr_ctx.atom(),
openfpga_ctx.vpr_device_annotation(),
openfpga_ctx.vpr_clustering_annotation(),
openfpga_ctx.vpr_placement_annotation(),
openfpga_ctx.vpr_bitstream_annotation(), verbose);
VTR_LOGV(verbose, "Done\n");
/* Create bitstream from routing architectures */
VTR_LOGV(verbose, "Building routing bitstream...\n");
build_routing_bitstream(
bitstream_manager, top_block, openfpga_ctx.module_graph(),
openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), vpr_ctx.atom(),
openfpga_ctx.fabric_tile(), openfpga_ctx.arch().circuit_lib,
openfpga_ctx.mux_lib(), vpr_ctx.atom(),
openfpga_ctx.vpr_device_annotation(), openfpga_ctx.vpr_routing_annotation(),
vpr_ctx.device().rr_graph, openfpga_ctx.device_rr_gsb(),
openfpga_ctx.flow_manager().compress_routing(), verbose);

39
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -819,9 +819,10 @@ static void build_physical_block_bitstream(
*******************************************************************/
void build_grid_bitstream(
BitstreamManager& bitstream_manager, const ConfigBlockId& top_block,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib, const DeviceGrid& grids,
const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
const ModuleManager& module_manager, const FabricTile& fabric_tile,
const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
const DeviceGrid& grids, const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprClusteringAnnotation& cluster_annotation,
const VprPlacementAnnotation& place_annotation,
const VprBitstreamAnnotation& bitstream_annotation, const bool& verbose) {
@ -841,8 +842,22 @@ void build_grid_bitstream(
}
/* Add a grid module to top_module*/
vtr::Point<size_t> grid_coord(ix, iy);
/* TODO: If the fabric tile is not empty, find the tile module and create
* the block accordingly. Also to support future hierarchy changes, when
* creating the blocks, trace backward until reach the current top block.
* If any block is missing during the back tracing, create it. */
ConfigBlockId parent_block = top_block;
FabricTileId curr_tile =
fabric_tile.find_tile_by_pb_coordinate(grid_coord);
if (fabric_tile.valid_tile_id(curr_tile)) {
vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(curr_tile);
std::string tile_inst_name = generate_tile_module_name(tile_coord);
parent_block = bitstream_manager.find_or_create_child_block(
top_block, tile_inst_name);
}
build_physical_block_bitstream(
bitstream_manager, top_block, module_manager, circuit_lib, mux_lib,
bitstream_manager, parent_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, cluster_annotation, place_annotation,
bitstream_annotation, grids, grid_coord, NUM_SIDES);
}
@ -868,8 +883,22 @@ void build_grid_bitstream(
(0 < grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) {
continue;
}
/* TODO: If the fabric tile is not empty, find the tile module and create
* the block accordingly. Also to support future hierarchy changes, when
* creating the blocks, trace backward until reach the current top block.
* If any block is missing during the back tracing, create it. */
ConfigBlockId parent_block = top_block;
FabricTileId curr_tile =
fabric_tile.find_tile_by_pb_coordinate(io_coordinate);
if (fabric_tile.valid_tile_id(curr_tile)) {
vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(curr_tile);
std::string tile_inst_name = generate_tile_module_name(tile_coord);
parent_block = bitstream_manager.find_or_create_child_block(
top_block, tile_inst_name);
}
build_physical_block_bitstream(
bitstream_manager, top_block, module_manager, circuit_lib, mux_lib,
bitstream_manager, parent_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, cluster_annotation, place_annotation,
bitstream_annotation, grids, io_coordinate, io_side);
}

8
openfpga/src/fpga_bitstream/build_grid_bitstream.h
View File

@ -9,6 +9,7 @@
#include "bitstream_manager.h"
#include "circuit_library.h"
#include "device_grid.h"
#include "fabric_tile.h"
#include "module_manager.h"
#include "mux_library.h"
#include "vpr_bitstream_annotation.h"
@ -26,9 +27,10 @@ namespace openfpga {
void build_grid_bitstream(
BitstreamManager& bitstream_manager, const ConfigBlockId& top_block,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib, const DeviceGrid& grids,
const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
const ModuleManager& module_manager, const FabricTile& fabric_tile,
const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
const DeviceGrid& grids, const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprClusteringAnnotation& cluster_annotation,
const VprPlacementAnnotation& place_annotation,
const VprBitstreamAnnotation& bitstream_annotation, const bool& verbose);

57
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -433,9 +433,9 @@ static void build_connection_block_bitstream(
static void build_connection_block_bitstreams(
BitstreamManager& bitstream_manager,
const ConfigBlockId& top_configurable_block,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const ModuleManager& module_manager, const FabricTile& fabric_tile,
const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const bool& compact_routing_hierarchy,
const t_rr_type& cb_type, const bool& verbose) {
@ -491,13 +491,26 @@ static void build_connection_block_bitstreams(
continue;
}
/* TODO: If the fabric tile is not empty, find the tile module and create
* the block accordingly. Also to support future hierarchy changes, when
* creating the blocks, trace backward until reach the current top block.
* If any block is missing during the back tracing, create it. */
ConfigBlockId parent_block = top_configurable_block;
FabricTileId curr_tile = fabric_tile.find_tile_by_cb_coordinate(
cb_type, vtr::Point<size_t>(ix, iy));
if (fabric_tile.valid_tile_id(curr_tile)) {
vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(curr_tile);
std::string tile_inst_name = generate_tile_module_name(tile_coord);
parent_block = bitstream_manager.find_or_create_child_block(
top_configurable_block, tile_inst_name);
}
/* Create a block for the bitstream which corresponds to the Switch block
*/
ConfigBlockId cb_configurable_block = bitstream_manager.add_block(
generate_connection_block_module_name(cb_type, cb_coord));
/* Set switch block as a child of top block */
bitstream_manager.add_child_block(top_configurable_block,
cb_configurable_block);
bitstream_manager.add_child_block(parent_block, cb_configurable_block);
/* Reserve child blocks for new created block */
bitstream_manager.reserve_child_blocks(
@ -524,9 +537,9 @@ static void build_connection_block_bitstreams(
void build_routing_bitstream(
BitstreamManager& bitstream_manager,
const ConfigBlockId& top_configurable_block,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const ModuleManager& module_manager, const FabricTile& fabric_tile,
const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const bool& compact_routing_hierarchy,
const bool& verbose) {
@ -573,13 +586,25 @@ void build_routing_bitstream(
continue;
}
/* TODO: If the fabric tile is not empty, find the tile module and create
* the block accordingly. Also to support future hierarchy changes, when
* creating the blocks, trace backward until reach the current top block.
* If any block is missing during the back tracing, create it. */
ConfigBlockId parent_block = top_configurable_block;
FabricTileId curr_tile = fabric_tile.find_tile_by_sb_coordinate(sb_coord);
if (fabric_tile.valid_tile_id(curr_tile)) {
vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(curr_tile);
std::string tile_inst_name = generate_tile_module_name(tile_coord);
parent_block = bitstream_manager.find_or_create_child_block(
top_configurable_block, tile_inst_name);
}
/* Create a block for the bitstream which corresponds to the Switch block
*/
ConfigBlockId sb_configurable_block = bitstream_manager.add_block(
generate_switch_block_module_name(sb_coord));
/* Set switch block as a child of top block */
bitstream_manager.add_child_block(top_configurable_block,
sb_configurable_block);
bitstream_manager.add_child_block(parent_block, sb_configurable_block);
/* Reserve child blocks for new created block */
bitstream_manager.reserve_child_blocks(
@ -605,17 +630,17 @@ void build_routing_bitstream(
VTR_LOG("Generating bitstream for X-direction Connection blocks ...");
build_connection_block_bitstreams(
bitstream_manager, top_configurable_block, module_manager, circuit_lib,
mux_lib, atom_ctx, device_annotation, routing_annotation, rr_graph,
device_rr_gsb, compact_routing_hierarchy, CHANX, verbose);
bitstream_manager, top_configurable_block, module_manager, fabric_tile,
circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation,
rr_graph, device_rr_gsb, compact_routing_hierarchy, CHANX, verbose);
VTR_LOG("Done\n");
VTR_LOG("Generating bitstream for Y-direction Connection blocks ...");
build_connection_block_bitstreams(
bitstream_manager, top_configurable_block, module_manager, circuit_lib,
mux_lib, atom_ctx, device_annotation, routing_annotation, rr_graph,
device_rr_gsb, compact_routing_hierarchy, CHANY, verbose);
bitstream_manager, top_configurable_block, module_manager, fabric_tile,
circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation,
rr_graph, device_rr_gsb, compact_routing_hierarchy, CHANY, verbose);
VTR_LOG("Done\n");
}

7
openfpga/src/fpga_bitstream/build_routing_bitstream.h
View File

@ -12,6 +12,7 @@
#include "bitstream_manager.h"
#include "circuit_library.h"
#include "device_rr_gsb.h"
#include "fabric_tile.h"
#include "module_manager.h"
#include "mux_library.h"
#include "vpr_context.h"
@ -28,9 +29,9 @@ namespace openfpga {
void build_routing_bitstream(
BitstreamManager& bitstream_manager,
const ConfigBlockId& top_configurable_block,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const ModuleManager& module_manager, const FabricTile& fabric_tile,
const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const bool& compact_routing_hierarchy,
const bool& verbose);