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[core] reworked fabric generator to use config child type

This commit is contained in:
tangxifan 2023-08-03 12:57:50 -07:00
parent 5895a1d96b
commit 2facde2097
7 changed files with 108 additions and 93 deletions
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53
openfpga/src/fabric/build_memory_modules.cpp
View File

@ -173,7 +173,7 @@ static void add_module_nets_to_cmos_memory_config_chain_module(
const CircuitLibrary& circuit_lib, const CircuitPortId& model_input_port,
const CircuitPortId& model_output_port) {
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module).size();
mem_index < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL).size();
++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
@ -194,27 +194,27 @@ static void add_module_nets_to_cmos_memory_config_chain_module(
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
} else {
/* Find the port name of previous memory module */
std::string src_port_name = circuit_lib.port_prefix(model_output_port);
net_src_module_id =
module_manager.configurable_children(parent_module)[mem_index - 1];
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module)[mem_index - 1];
parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
}
@ -248,9 +248,9 @@ static void add_module_nets_to_cmos_memory_config_chain_module(
/* Find the port name of previous memory module */
std::string src_port_name = circuit_lib.port_prefix(model_output_port);
ModuleId net_src_module_id =
module_manager.configurable_children(parent_module).back();
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL).back();
size_t net_src_instance_id =
module_manager.configurable_child_instances(parent_module).back();
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::LOGICAL).back();
ModulePortId net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
@ -310,7 +310,7 @@ static void add_module_nets_to_cmos_memory_scan_chain_module(
const CircuitLibrary& circuit_lib, const CircuitPortId& model_input_port,
const CircuitPortId& model_output_port) {
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module).size();
mem_index < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL).size();
++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
@ -331,16 +331,16 @@ static void add_module_nets_to_cmos_memory_scan_chain_module(
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
} else {
/* Find the port name of previous memory module */
std::string src_port_name = circuit_lib.port_prefix(model_output_port);
net_src_module_id =
module_manager.configurable_children(parent_module)[mem_index - 1];
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module)[mem_index - 1];
net_src_port_id =
@ -349,9 +349,9 @@ static void add_module_nets_to_cmos_memory_scan_chain_module(
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
}
@ -480,7 +480,7 @@ static void build_memory_flatten_module(ModuleManager& module_manager,
module_manager.num_instance(mem_module, sram_mem_module);
module_manager.add_child_module(mem_module, sram_mem_module);
module_manager.add_configurable_child(mem_module, sram_mem_module,
sram_mem_instance);
sram_mem_instance, ModuleManager::e_config_child_type::UNIFIED);
/* Build module nets */
/* Wire inputs of parent module to inputs of child modules */
@ -613,7 +613,7 @@ static void build_memory_chain_module(ModuleManager& module_manager,
module_manager.num_instance(mem_module, sram_mem_module);
module_manager.add_child_module(mem_module, sram_mem_module);
module_manager.add_configurable_child(mem_module, sram_mem_module,
sram_mem_instance);
sram_mem_instance, ModuleManager::e_config_child_type::UNIFIED);
/* Build module nets to wire outputs of sram modules to outputs of memory
* module */
@ -830,7 +830,7 @@ static void build_frame_memory_module(ModuleManager& module_manager,
module_manager.num_instance(mem_module, sram_mem_module);
module_manager.add_child_module(mem_module, sram_mem_module);
module_manager.add_configurable_child(mem_module, sram_mem_module,
sram_instance);
sram_instance, ModuleManager::e_config_child_type::UNIFIED);
/* Wire data_in port to SRAM BL port */
ModulePortId sram_bl_port = module_manager.find_module_port(
@ -890,7 +890,7 @@ static void build_frame_memory_module(ModuleManager& module_manager,
add_module_global_ports_from_child_modules(module_manager, mem_module);
/* Add the decoder as the last configurable children */
module_manager.add_configurable_child(mem_module, decoder_module, 0);
module_manager.add_configurable_child(mem_module, decoder_module, 0, ModuleManager::e_config_child_type::UNIFIED);
}
/*********************************************************************
@ -1292,7 +1292,7 @@ int build_memory_group_module(ModuleManager& module_manager,
ModuleId child_module = child_modules[ichild];
size_t child_instance = module_manager.num_instance(mem_module, child_module);
module_manager.add_child_module(mem_module, child_module, false);
module_manager.add_configurable_child(mem_module, child_module, child_instance, false);
module_manager.add_configurable_child(mem_module, child_module, child_instance, ModuleManager::e_config_child_type::UNIFIED);
/* Wire outputs of child module to outputs of parent module */
add_module_output_nets_to_memory_group_module(
module_manager, mem_module, out_port_name,
@ -1342,9 +1342,10 @@ int build_memory_group_module(ModuleManager& module_manager,
* we just need to find all the I/O ports from the child modules and build a
* list of it
*/
ModuleManager::e_config_child_type config_child_type = ModuleManager::e_config_child_type::PHYSICAL;
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, mem_module, circuit_lib, sram_model, sram_orgz_type);
module_manager, mem_module, circuit_lib, sram_model, sram_orgz_type, config_child_type);
if (0 < module_num_config_bits) {
add_sram_ports_to_module_manager(module_manager, mem_module, circuit_lib,
sram_model, sram_orgz_type,
@ -1355,10 +1356,10 @@ int build_memory_group_module(ModuleManager& module_manager,
* This is a one-shot addition that covers all the memory modules in this pb
* module!
*/
if (0 < module_manager.configurable_children(mem_module).size()) {
if (0 < module_manager.num_configurable_children(mem_module, config_child_type)) {
add_module_nets_memory_config_bus(module_manager, decoder_lib, mem_module,
sram_orgz_type,
circuit_lib.design_tech_type(sram_model));
circuit_lib.design_tech_type(sram_model), config_child_type);
}
return CMD_EXEC_SUCCESS;
@ -1417,7 +1418,7 @@ int add_physical_memory_module(ModuleManager& module_manager,
std::map<e_circuit_model_port_type, std::string> mem2mem_port_map;
mem2mem_port_map[CIRCUIT_MODEL_PORT_BL] = std::string(CONFIGURABLE_MEMORY_DATA_OUT_NAME);
mem2mem_port_map[CIRCUIT_MODEL_PORT_BLB] = std::string(CONFIGURABLE_MEMORY_INVERTED_DATA_OUT_NAME);
for (size_t ichild = 0; ichild < module_manager.logical_configurable_children(curr_module).size(); ++ichild) {
for (size_t ichild = 0; ichild < module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::PHYSICAL).size(); ++ichild) {
for (CircuitPortType port_type : {CIRCUIT_MODEL_PORT_BL, CIRCUIT_MODEL_PORT_BLB}) {
std::string src_port_name = mem2mem_port_map[port_type];
std::string des_port_name =
@ -1431,8 +1432,8 @@ int add_physical_memory_module(ModuleManager& module_manager,
BasicPort src_port =
module_manager.module_port(phy_mem_module, src_port_id);
ModuleId des_module = module_manager.logical_configurable_children(curr_module)[ichild];
size_t des_instance = module_manager.logical_configurable_child_instances(curr_module)[ichild];
ModuleId des_module = module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
size_t des_instance = module_manager.configurable_child_instances(curr_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
ModulePortId des_port_id =
module_manager.find_module_port(des_module, des_port_name);
if (!module_manager.valid_module_port_id(des_module, des_port_id)) {

26
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -241,15 +241,16 @@ static void build_switch_block_mux_module(
module_manager, sb_module, mux_module, mux_instance_id, mem_module,
mem_instance_id, circuit_lib, mux_model);
/* Update memory and instance list */
size_t config_child_id = module_manager.num_configurable_children(sb_module);
module_manager.add_configurable_child(sb_module, mem_module, mem_instance_id, group_config_block);
size_t config_child_id = module_manager.num_configurable_children(sb_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(sb_module, mem_module, mem_instance_id, group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
/* For logical memory, define the physical memory here */
if (group_config_block) {
std::string physical_mem_module_name =
generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size,
std::string(MEMORY_MODULE_POSTFIX));
ModuleId physical_mem_module = module_manager.find_module(physical_mem_module_name);
module_manager.set_physical_configurable_child(sb_module, config_child_id, physical_mem_module);
VTR_ASSERT(true == module_manager.valid_module_id(physical_mem_module));
module_manager.set_logical2physical_configurable_child(sb_module, config_child_id, physical_mem_module);
}
}
@ -509,9 +510,10 @@ static void build_switch_block_module(
* we just need to find all the I/O ports from the child modules and build a
* list of it
*/
ModuleManager::e_config_child_type config_child_type = group_config_block ? ModuleManager::e_config_child_type::PHYSICAL : ModuleManager::e_config_child_type::LOGICAL;
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, sb_module, circuit_lib, sram_model, sram_orgz_type);
module_manager, sb_module, circuit_lib, sram_model, sram_orgz_type, config_child_type);
if (0 < module_num_config_bits) {
add_pb_sram_ports_to_module_manager(module_manager, sb_module, circuit_lib,
sram_model, sram_orgz_type,
@ -522,10 +524,10 @@ static void build_switch_block_module(
* primitive modules This is a one-shot addition that covers all the memory
* modules in this primitive module!
*/
if (0 < module_manager.configurable_children(sb_module).size()) {
if (0 < module_manager.num_configurable_children(sb_module, config_child_type)) {
add_pb_module_nets_memory_config_bus(
module_manager, decoder_lib, sb_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model));
circuit_lib.design_tech_type(sram_model), config_child_type);
}
VTR_LOGV(verbose, "Done\n");
@ -751,14 +753,15 @@ static void build_connection_block_mux_module(
mem_instance_id, circuit_lib, mux_model);
/* Update memory and instance list */
size_t config_child_id = module_manager.num_configurable_children(cb_module);
module_manager.add_configurable_child(cb_module, mem_module, mem_instance_id, group_config_block);
module_manager.add_configurable_child(cb_module, mem_module, mem_instance_id, group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
/* For logical memory, define the physical memory here */
if (group_config_block) {
std::string physical_mem_module_name =
generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size,
std::string(MEMORY_MODULE_POSTFIX));
ModuleId physical_mem_module = module_manager.find_module(physical_mem_module_name);
module_manager.set_physical_configurable_child(cb_module, config_child_id, physical_mem_module);
VTR_ASSERT(true == module_manager.valid_module_id(physical_mem_module));
module_manager.set_logical2physical_configurable_child(cb_module, config_child_id, physical_mem_module);
}
}
@ -1016,9 +1019,10 @@ static void build_connection_block_module(
* we just need to find all the I/O ports from the child modules and build a
* list of it
*/
ModuleManager::e_config_child_type config_child_type = group_config_block ? ModuleManager::e_config_child_type::PHYSICAL : ModuleManager::e_config_child_type::LOGICAL;
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, cb_module, circuit_lib, sram_model, sram_orgz_type);
module_manager, cb_module, circuit_lib, sram_model, sram_orgz_type, config_child_type);
if (0 < module_num_config_bits) {
add_pb_sram_ports_to_module_manager(module_manager, cb_module, circuit_lib,
sram_model, sram_orgz_type,
@ -1029,10 +1033,10 @@ static void build_connection_block_module(
* primitive modules This is a one-shot addition that covers all the memory
* modules in this primitive module!
*/
if (0 < module_manager.configurable_children(cb_module).size()) {
if (0 < module_manager.num_configurable_children(cb_module, config_child_type)) {
add_pb_module_nets_memory_config_bus(
module_manager, decoder_lib, cb_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model));
circuit_lib.design_tech_type(sram_model), config_child_type);
}
VTR_LOGV(verbose, "Done\n");

12
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -1332,7 +1332,7 @@ static int build_tile_module(
circuit_lib, sram_model,
sram_orgz_type)) {
module_manager.add_configurable_child(tile_module, pb_module,
pb_instance);
pb_instance, ModuleManager::e_config_child_type::UNIFIED);
}
VTR_LOGV(
verbose,
@ -1379,7 +1379,7 @@ static int build_tile_module(
circuit_lib, sram_model,
sram_orgz_type)) {
module_manager.add_configurable_child(tile_module, cb_module,
cb_instance);
cb_instance, ModuleManager::e_config_child_type::UNIFIED);
}
VTR_LOGV(verbose,
"Added connection block module '%s' (instance: '%s') to "
@ -1418,7 +1418,7 @@ static int build_tile_module(
if (0 < find_module_num_config_bits(module_manager, sb_module, circuit_lib,
sram_model, sram_orgz_type)) {
module_manager.add_configurable_child(tile_module, sb_module,
sb_instance);
sb_instance, ModuleManager::e_config_child_type::UNIFIED);
}
VTR_LOGV(
verbose,
@ -1468,7 +1468,7 @@ static int build_tile_module(
*/
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, tile_module, circuit_lib, sram_model, sram_orgz_type);
module_manager, tile_module, circuit_lib, sram_model, sram_orgz_type, ModuleManager::e_config_child_type::LOGICAL);
if (0 < module_num_config_bits) {
add_pb_sram_ports_to_module_manager(module_manager, tile_module,
circuit_lib, sram_model, sram_orgz_type,
@ -1479,10 +1479,10 @@ static int build_tile_module(
* This is a one-shot addition that covers all the memory modules in this pb
* module!
*/
if (0 < module_manager.logical_configurable_children(tile_module).size()) {
if (0 < module_manager.num_configurable_children(tile_module, ModuleManager::e_config_child_type::LOGICAL)) {
add_pb_module_nets_memory_config_bus(
module_manager, decoder_lib, tile_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model));
circuit_lib.design_tech_type(sram_model), ModuleManager::e_config_child_type::LOGICAL);
}
VTR_LOGV(verbose, "Done\n");

2
openfpga/src/fabric/build_top_module.cpp
View File

@ -134,7 +134,7 @@ int build_top_module(
* module!
*/
if (false == frame_view) {
if (0 < module_manager.configurable_children(top_module).size()) {
if (0 < module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size()) {
add_top_module_nets_memory_config_bus(
module_manager, decoder_lib, blwl_sr_banks, top_module, circuit_lib,
config_protocol, circuit_lib.design_tech_type(sram_model),

3
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1076,7 +1076,7 @@ static void organize_top_module_tile_based_memory_modules(
const CircuitModelId& sram_model, const DeviceGrid& grids,
const vtr::Matrix<size_t>& tile_instance_ids, const FabricTile& fabric_tile) {
/* Ensure clean vectors to return */
VTR_ASSERT(true == module_manager.configurable_children(top_module).empty());
VTR_ASSERT(true == module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).empty());
std::vector<vtr::Point<size_t>> tile_coords;
bool positive_direction = true;
@ -1116,6 +1116,7 @@ static void organize_top_module_tile_based_memory_modules(
module_manager.add_configurable_child(
top_module, tile_module,
tile_instance_ids[curr_tile_coord.x()][curr_tile_coord.y()],
ModuleManager::e_config_child_type::UNIFIED,
vtr::Point<int>(curr_tile_coord.x(), curr_tile_coord.y()));
}
}

34
openfpga/src/fabric/build_top_module_memory.cpp
View File

@ -86,7 +86,7 @@ static void organize_top_module_tile_cb_modules(
module_manager.add_configurable_child(
top_module, cb_module,
cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)],
false,
ModuleManager::e_config_child_type::UNIFIED,
config_coord);
}
}
@ -174,7 +174,7 @@ static void organize_top_module_tile_memory_modules(
rr_gsb.get_sb_y() * 2 + 1);
module_manager.add_configurable_child(
top_module, sb_module,
sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()], false, config_coord);
sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()], ModuleManager::e_config_child_type::UNIFIED, config_coord);
}
}
@ -219,7 +219,8 @@ static void organize_top_module_tile_memory_modules(
sram_model, sram_orgz_type)) {
vtr::Point<int> config_coord(tile_coord.x() * 2, tile_coord.y() * 2);
module_manager.add_configurable_child(
top_module, grid_module, false,
top_module, grid_module,
ModuleManager::e_config_child_type::UNIFIED,
grid_instance_ids[tile_coord.x()][tile_coord.y()], config_coord);
}
}
@ -270,14 +271,14 @@ void build_top_module_configurable_regions(
"Build configurable regions for the top module");
/* Ensure we have valid configurable children */
VTR_ASSERT(false == module_manager.logical_configurable_children(top_module).empty());
VTR_ASSERT(false == module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).empty());
/* Ensure that our region definition is valid */
VTR_ASSERT(1 <= config_protocol.num_regions());
/* Exclude decoders from the list */
size_t num_configurable_children =
module_manager.logical_configurable_children(top_module).size();
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size();
if (CONFIG_MEM_MEMORY_BANK == config_protocol.type() ||
CONFIG_MEM_QL_MEMORY_BANK == config_protocol.type()) {
num_configurable_children -= 2;
@ -292,7 +293,7 @@ void build_top_module_configurable_regions(
bool create_region = true;
ConfigRegionId curr_region = ConfigRegionId::INVALID();
for (size_t ichild = 0;
ichild < module_manager.logical_configurable_children(top_module).size();
ichild < module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size();
++ichild) {
if (true == create_region) {
curr_region = module_manager.add_config_region(top_module);
@ -301,8 +302,8 @@ void build_top_module_configurable_regions(
/* Add the child to a region */
module_manager.add_configurable_child_to_region(
top_module, curr_region,
module_manager.logical_configurable_children(top_module)[ichild],
module_manager.logical_configurable_child_instances(top_module)[ichild], ichild);
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild],
module_manager.configurable_child_instances(top_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild], ichild);
/* See if the current region is full or not:
* For the last region, we will keep adding until we finish all the children
@ -531,7 +532,7 @@ void organize_top_module_memory_modules(
void shuffle_top_module_configurable_children(
ModuleManager& module_manager, const ModuleId& top_module,
const ConfigProtocol& config_protocol) {
size_t num_keys = module_manager.configurable_children(top_module).size();
size_t num_keys = module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size();
std::vector<size_t> shuffled_keys;
shuffled_keys.reserve(num_keys);
for (size_t ikey = 0; ikey < num_keys; ++ikey) {
@ -542,11 +543,11 @@ void shuffle_top_module_configurable_children(
/* Cache the configurable children and their instances */
std::vector<ModuleId> orig_configurable_children =
module_manager.logical_configurable_children(top_module);
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL);
std::vector<size_t> orig_configurable_child_instances =
module_manager.logical_configurable_child_instances(top_module);
module_manager.configurable_child_instances(top_module, ModuleManager::e_config_child_type::PHYSICAL);
std::vector<vtr::Point<int>> orig_configurable_child_coordinates =
module_manager.logical_configurable_child_coordinates(top_module);
module_manager.configurable_child_coordinates(top_module, ModuleManager::e_config_child_type::PHYSICAL);
/* Reorganize the configurable children */
module_manager.clear_configurable_children(top_module);
@ -555,7 +556,7 @@ void shuffle_top_module_configurable_children(
module_manager.add_configurable_child(
top_module, orig_configurable_children[shuffled_keys[ikey]],
orig_configurable_child_instances[shuffled_keys[ikey]],
false,
ModuleManager::e_config_child_type::UNIFIED,
orig_configurable_child_coordinates[shuffled_keys[ikey]]);
}
@ -653,7 +654,8 @@ int load_top_module_memory_modules_from_fabric_key(
/* Now we can add the child to configurable children of the top module */
module_manager.add_configurable_child(top_module, instance_info.first,
instance_info.second, false,
instance_info.second,
ModuleManager::e_config_child_type::UNIFIED,
fabric_key.key_coordinate(key));
module_manager.add_configurable_child_to_region(
top_module, top_module_config_region, instance_info.first,
@ -1929,10 +1931,10 @@ static void add_top_module_nets_cmos_memory_config_bus(
case CONFIG_MEM_STANDALONE:
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, config_protocol.type(),
CIRCUIT_MODEL_PORT_BL);
CIRCUIT_MODEL_PORT_BL, ModuleManager::e_config_child_type::PHYSICAL);
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, config_protocol.type(),
CIRCUIT_MODEL_PORT_WL);
CIRCUIT_MODEL_PORT_WL, ModuleManager::e_config_child_type::PHYSICAL);
break;
case CONFIG_MEM_SCAN_CHAIN: {
add_top_module_nets_cmos_memory_chain_config_bus(

71
openfpga/src/utils/module_manager_memory_utils.cpp
View File

@ -39,7 +39,7 @@ static bool submodule_memory_modules_match_fabric_key(
const FabricKey& fabric_key, const FabricKeyModuleId& key_module_id) {
/* If the length does not match, conclusion is easy to be made */
size_t len_module_memory =
module_manager.configurable_children(module_id).size();
module_manager.configurable_children(module_id, ModuleManager::e_config_child_type::PHYSICAL).size();
size_t len_fabric_sub_key = fabric_key.sub_keys(key_module_id).size();
if (len_module_memory != len_fabric_sub_key) {
return false;
@ -65,9 +65,9 @@ static bool submodule_memory_modules_match_fabric_key(
inst_info.second = fabric_key.sub_key_value(key_id);
}
if (inst_info.first !=
module_manager.configurable_children(module_id)[ikey] ||
module_manager.configurable_children(module_id, ModuleManager::e_config_child_type::PHYSICAL)[ikey] ||
inst_info.second !=
module_manager.configurable_child_instances(module_id)[ikey]) {
module_manager.configurable_child_instances(module_id, ModuleManager::e_config_child_type::PHYSICAL)[ikey]) {
return false;
}
}
@ -80,9 +80,10 @@ static bool submodule_memory_modules_match_fabric_key(
static bool update_submodule_memory_modules_from_fabric_key(
ModuleManager& module_manager, const ModuleId& module_id,
const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
const ModuleManager::e_config_child_type& config_child_type,
const FabricKey& fabric_key, const FabricKeyModuleId& key_module_id) {
/* Reset the configurable children */
module_manager.clear_configurable_children(module_id);
module_manager.clear_configurable_children(module_id, config_child_type);
for (FabricSubKeyId key_id : fabric_key.sub_keys(key_module_id)) {
std::pair<ModuleId, size_t> inst_info(ModuleId::INVALID(), 0);
@ -142,7 +143,7 @@ static bool update_submodule_memory_modules_from_fabric_key(
/* Now we can add the child to configurable children of the top module */
module_manager.add_configurable_child(module_id, inst_info.first,
inst_info.second, vtr::Point<int>());
inst_info.second, config_child_type, vtr::Point<int>());
}
return CMD_EXEC_SUCCESS;
}
@ -152,9 +153,10 @@ static bool update_submodule_memory_modules_from_fabric_key(
*******************************************************************/
static int remove_submodule_nets_cmos_memory_chain_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type) {
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type) {
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module).size();
mem_index < module_manager.configurable_children(parent_module, config_child_type).size();
++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
@ -172,9 +174,9 @@ static int remove_submodule_nets_cmos_memory_chain_config_bus(
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
net_src_module_id =
module_manager.configurable_children(parent_module)[mem_index - 1];
module_manager.configurable_children(parent_module, config_child_type)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module)[mem_index - 1];
parent_module, config_child_type)[mem_index - 1];
net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
}
@ -201,9 +203,9 @@ static int remove_submodule_nets_cmos_memory_chain_config_bus(
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
ModuleId net_src_module_id =
module_manager.configurable_children(parent_module).back();
module_manager.configurable_children(parent_module, config_child_type).back();
size_t net_src_instance_id =
module_manager.configurable_child_instances(parent_module).back();
module_manager.configurable_child_instances(parent_module, config_child_type).back();
ModulePortId net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
@ -229,11 +231,12 @@ static int remove_submodule_nets_cmos_memory_chain_config_bus(
*******************************************************************/
static int remove_submodule_nets_cmos_memory_config_bus(
ModuleManager& module_manager, const ModuleId& module_id,
const e_config_protocol_type& sram_orgz_type) {
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type) {
switch (sram_orgz_type) {
case CONFIG_MEM_SCAN_CHAIN: {
return remove_submodule_nets_cmos_memory_chain_config_bus(
module_manager, module_id, sram_orgz_type);
module_manager, module_id, sram_orgz_type, config_child_type);
break;
}
case CONFIG_MEM_STANDALONE:
@ -274,11 +277,12 @@ static int remove_submodule_nets_cmos_memory_config_bus(
*******************************************************************/
static int remove_submodule_configurable_children_nets(
ModuleManager& module_manager, const ModuleId& module_id,
const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol) {
const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
const ModuleManager::e_config_child_type& config_child_type) {
switch (circuit_lib.design_tech_type(config_protocol.memory_model())) {
case CIRCUIT_MODEL_DESIGN_CMOS:
return remove_submodule_nets_cmos_memory_config_bus(
module_manager, module_id, config_protocol.type());
module_manager, module_id, config_protocol.type(), config_child_type);
break;
case CIRCUIT_MODEL_DESIGN_RRAM:
/* TODO: */
@ -297,9 +301,10 @@ static int remove_submodule_configurable_children_nets(
*******************************************************************/
static int rebuild_submodule_nets_cmos_memory_chain_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type) {
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type) {
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module).size();
mem_index < module_manager.configurable_children(parent_module, config_child_type).size();
++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
@ -321,27 +326,27 @@ static int rebuild_submodule_nets_cmos_memory_chain_config_bus(
/* Find the port name of next memory module */
std::string sink_port_name = generate_configuration_chain_head_name();
net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
} else {
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
net_src_module_id =
module_manager.configurable_children(parent_module)[mem_index - 1];
module_manager.configurable_children(parent_module, config_child_type)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module)[mem_index - 1];
parent_module, config_child_type)[mem_index - 1];
net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
/* Find the port name of next memory module */
std::string sink_port_name = generate_configuration_chain_head_name();
net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
}
@ -375,9 +380,9 @@ static int rebuild_submodule_nets_cmos_memory_chain_config_bus(
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
ModuleId net_src_module_id =
module_manager.configurable_children(parent_module).back();
module_manager.configurable_children(parent_module, config_child_type).back();
size_t net_src_instance_id =
module_manager.configurable_child_instances(parent_module).back();
module_manager.configurable_child_instances(parent_module, config_child_type).back();
ModulePortId net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
@ -418,11 +423,12 @@ static int rebuild_submodule_nets_cmos_memory_chain_config_bus(
*******************************************************************/
static int rebuild_submodule_nets_cmos_memory_config_bus(
ModuleManager& module_manager, const ModuleId& module_id,
const e_config_protocol_type& sram_orgz_type) {
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type) {
switch (sram_orgz_type) {
case CONFIG_MEM_SCAN_CHAIN: {
return rebuild_submodule_nets_cmos_memory_chain_config_bus(
module_manager, module_id, sram_orgz_type);
module_manager, module_id, sram_orgz_type, config_child_type);
break;
}
case CONFIG_MEM_STANDALONE:
@ -464,11 +470,12 @@ static int rebuild_submodule_nets_cmos_memory_config_bus(
*******************************************************************/
static int rebuild_submodule_configurable_children_nets(
ModuleManager& module_manager, const ModuleId& module_id,
const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol) {
const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
const ModuleManager::e_config_child_type& config_child_type) {
switch (circuit_lib.design_tech_type(config_protocol.memory_model())) {
case CIRCUIT_MODEL_DESIGN_CMOS:
return rebuild_submodule_nets_cmos_memory_config_bus(
module_manager, module_id, config_protocol.type());
module_manager, module_id, config_protocol.type(), config_child_type);
break;
case CIRCUIT_MODEL_DESIGN_RRAM:
/* TODO: */
@ -502,20 +509,20 @@ static int load_and_update_submodule_memory_modules_from_fabric_key(
}
/* Do not match, now remove all the nets for the configurable children */
status = remove_submodule_configurable_children_nets(
module_manager, module_id, circuit_lib, config_protocol);
module_manager, module_id, circuit_lib, config_protocol, ModuleManager::e_config_child_type::PHYSICAL);
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
}
/* Overwrite the configurable children list */
status = update_submodule_memory_modules_from_fabric_key(
module_manager, module_id, circuit_lib, config_protocol, fabric_key,
module_manager, module_id, circuit_lib, config_protocol, ModuleManager::e_config_child_type::PHYSICAL, fabric_key,
key_module_id);
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
}
/* TODO: Create the nets for the new list of configurable children */
status = rebuild_submodule_configurable_children_nets(
module_manager, module_id, circuit_lib, config_protocol);
module_manager, module_id, circuit_lib, config_protocol, ModuleManager::e_config_child_type::PHYSICAL);
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
}