riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] reworking fabric generator based on latest changes on configurable children

This commit is contained in:
tangxifan 2023-08-02 22:50:19 -07:00
parent 27cae41123
commit 5895a1d96b
7 changed files with 130 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -357,16 +357,17 @@ static void build_primitive_block_module(
module_manager, primitive_module, logic_module, logic_instance_id,
memory_module, memory_instance_id, circuit_lib, primitive_model);
/* Record memory-related information */
size_t config_child_id = module_manager.num_configurable_children(primitive_module);
size_t config_child_id = module_manager.num_configurable_children(primitive_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(primitive_module, memory_module,
memory_instance_id, group_config_block);
memory_instance_id,
group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
/* For logical memory, define the physical memory here */
if (group_config_block) {
std::string physical_memory_module_name =
generate_memory_module_name(circuit_lib, primitive_model, sram_model,
std::string(MEMORY_MODULE_POSTFIX), false);
ModuleId physical_memory_module = module_manager.find_module(physical_memory_module_name);
module_manager.set_physical_configurable_child(primitive_module, config_child_id, physical_memory_module);
module_manager.set_logical2physical_configurable_child(primitive_module, config_child_id, physical_memory_module);
}
}
@ -374,10 +375,11 @@ static void build_primitive_block_module(
* primitive modules This is a one-shot addition that covers all the memory
* modules in this primitive module!
*/
if (0 < module_manager.configurable_children(primitive_module).size()) {
if (0 < module_manager.num_configurable_children(primitive_module, ModuleManager::e_config_child_type::LOGICAL)) {
add_module_nets_memory_config_bus(module_manager, decoder_lib,
primitive_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model));
circuit_lib.design_tech_type(sram_model),
ModuleManager::e_config_child_type::LOGICAL);
}
/* Add global ports to the pb_module:
@ -639,6 +641,11 @@ static void add_module_pb_graph_pin_interc(
std::string mux_mem_module_name =
generate_mux_subckt_name(circuit_lib, interc_circuit_model, fan_in,
std::string(MEMORY_MODULE_POSTFIX));
if (group_config_block) {
mux_mem_module_name =
generate_mux_subckt_name(circuit_lib, interc_circuit_model, fan_in,
std::string(MEMORY_FEEDTHROUGH_MODULE_POSTFIX));
}
ModuleId mux_mem_module = module_manager.find_module(mux_mem_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module));
size_t mux_mem_instance =
@ -653,8 +660,18 @@ static void add_module_pb_graph_pin_interc(
module_manager.set_child_instance_name(
pb_module, mux_mem_module, mux_mem_instance, mux_mem_instance_name);
/* Add this MUX as a configurable child to the pb_module */
size_t config_child_id = module_manager.num_configurable_child(pb_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(pb_module, mux_mem_module,
mux_mem_instance, group_config_block);
mux_mem_instance, group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
if (group_config_block) {
std::string phy_mem_module_name =
generate_mux_subckt_name(circuit_lib, interc_circuit_model, fan_in,
std::string(MEMORY_MODULE_POSTFIX));
ModuleId phy_mem_module = module_manager.find_module(phy_mem_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(phy_mem_module));
module_manager.set_logical2physical_configurable_child(pb_module, config_child_id,
phy_mem_module);
}
/* Add nets to connect SRAM ports of the MUX to the SRAM port of memory
* module */
@ -1012,7 +1029,7 @@ static void rec_build_logical_tile_modules(
circuit_lib, sram_model,
mem_module_type)) {
module_manager.add_configurable_child(pb_module, child_pb_module,
child_instance_id, group_config_block);
child_instance_id, group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
}
}
}
@ -1070,10 +1087,11 @@ static void rec_build_logical_tile_modules(
* This is a one-shot addition that covers all the memory modules in this pb
* module!
*/
if (0 < module_manager.logical_configurable_children(pb_module).size()) {
if (0 < module_manager.num_configurable_children(pb_module, ModuleManager::e_config_child_type::LOGICAL)) {
add_module_nets_memory_config_bus(module_manager, decoder_lib, pb_module,
mem_module_type,
circuit_lib.design_tech_type(sram_model));
circuit_lib.design_tech_type(sram_model),
ModuleManager::e_config_child_type::LOGICAL);
}
VTR_LOGV(verbose, "Done\n");
@ -1150,7 +1168,7 @@ static void build_physical_tile_module(
group_config_block ? CONFIG_MEM_FEEDTHROUGH : sram_orgz_type)) {
/* Only add logical configurable children here. Since we will add a physical memory block at this level */
module_manager.add_configurable_child(grid_module, pb_module,
pb_instance_id, group_config_block);
pb_instance_id, group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
}
}
}
@ -1245,9 +1263,10 @@ static void build_physical_tile_module(
* we just need to find all the I/O ports from the child modules and build a
* list of it
*/
ModuleManager::e_config_child_type config_child_type = group_config_block ? ModuleManager::e_config_child_type::PHYSICAL : ModuleManager::e_config_child_type::LOGICAL;
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type);
module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type, config_child_type);
if (0 < module_num_config_bits) {
add_pb_sram_ports_to_module_manager(module_manager, grid_module,
circuit_lib, sram_model, sram_orgz_type,
@ -1258,10 +1277,10 @@ static void build_physical_tile_module(
* This is a one-shot addition that covers all the memory modules in this pb
* module!
*/
if (0 < module_manager.logical_configurable_children(grid_module).size()) {
if (0 < module_manager.num_configurable_children(grid_module, config_child_type)) {
add_pb_module_nets_memory_config_bus(
module_manager, decoder_lib, grid_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model));
circuit_lib.design_tech_type(sram_model), config_child_type);
}
VTR_LOGV(verbose, "Done\n");

2
openfpga/src/fabric/build_memory_modules.cpp
View File

@ -1410,7 +1410,7 @@ int add_physical_memory_module(ModuleManager& module_manager,
module_manager.add_child_module(curr_module, phy_mem_module, false);
/* Register in the physical configurable children list */
module_manager.add_physical_configurable_child(curr_module, phy_mem_module, phy_mem_instance, curr_module);
module_manager.add_configurable_child(curr_module, phy_mem_module, phy_mem_instance, ModuleManager::e_config_child_type::PHYSICAL);
/* Build nets between the data output of the physical memory module and the outputs of the logical configurable children */
size_t curr_mem_pin_index = 0;

8
openfpga/src/fabric/module_manager.cpp
View File

@ -412,9 +412,13 @@ size_t ModuleManager::instance_id(const ModuleId& parent_module,
return size_t(-1);
}
size_t ModuleManager::num_logical_configurable_children(const ModuleId& parent_module) const {
size_t ModuleManager::num_configurable_children(const ModuleId& parent_module, const e_config_child_type& type) const;
VTR_ASSERT(valid_module_id(parent_module));
return logical_configurable_children_[parent_module].size();
if (type == ModuleManager::e_config_child_type::LOGICAL) {
return logical_configurable_children_[parent_module].size();
}
VTR_ASSERT(type == ModuleManager::e_config_child_type::LOGICAL);
return physical_configurable_children_[parent_module].size()
}
ModuleManager::e_module_port_type ModuleManager::port_type(

2
openfpga/src/fabric/module_manager.h
View File

@ -265,7 +265,7 @@ class ModuleManager {
const ModuleId& child_module,
const std::string& instance_name) const;
/** @brief Count the number of logical configurable children */
size_t num_logical_configurable_children(const ModuleId& parent_module) const;
size_t num_configurable_children(const ModuleId& parent_module, const e_config_child_type& type) const;
/* Find the type of a port */
ModuleManager::e_module_port_type port_type(const ModuleId& module,
const ModulePortId& port) const;

24
openfpga/src/utils/memory_utils.cpp
View File

@ -497,14 +497,14 @@ size_t estimate_num_configurable_children_to_skip_by_config_protocol(
}
int rec_find_physical_memory_children(const ModuleManager& module_manager, const ModuleId& curr_module, std::vector<ModuleId>& physical_memory_children) {
if (module_manager.logical_configurable_children(curr_module).empty()) {
if (module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL).empty()) {
return CMD_EXEC_SUCCESS;
}
for (size_t ichild = 0; ichild < module_manager.logical_configurable_children(curr_module).size(); ++ichild) {
ModuleId logical_child = module_manager.logical_configurable_children(curr_module)[ichild];
if (module_manager.logical_configurable_children(logical_child).empty()) {
for (size_t ichild = 0; ichild < module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL).size(); ++ichild) {
ModuleId logical_child = module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL)[ichild];
if (module_manager.configurable_children(logical_child, ModuleManager::e_config_child_type::LOGICAL).empty()) {
/* This is a leaf node, get the physical memory module */
physical_memory_children.push_back(module_manager.physical_configurable_children(curr_module)[ichild]);
physical_memory_children.push_back(module_manager.logical2physical_configurable_children(curr_module)[ichild]);
} else {
rec_find_physical_memory_children(module_manager, logical_child, physical_memory_children);
}
@ -513,20 +513,20 @@ int rec_find_physical_memory_children(const ModuleManager& module_manager, const
}
int rec_update_logical_memory_children_with_physical_mapping(ModuleManager& module_manager, const ModuleId& curr_module, const ModuleId& phy_mem_module, std::map<ModuleId, size_t>& logical_mem_child_inst_count) {
if (module_manager.logical_configurable_children(curr_module).empty()) {
if (module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL).empty()) {
return CMD_EXEC_SUCCESS;
}
for (size_t ichild = 0; ichild < module_manager.logical_configurable_children(curr_module).size(); ++ichild) {
ModuleId logical_child = module_manager.logical_configurable_children(curr_module)[ichild];
if (module_manager.logical_configurable_children(logical_child).empty()) {
for (size_t ichild = 0; ichild < module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL).size(); ++ichild) {
ModuleId logical_child = module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL)[ichild];
if (module_manager.configurable_children(logical_child, ModuleManager::e_config_child_type::LOGICAL).empty()) {
/* This is a leaf node, update its physical information */
ModuleId phy_mem_submodule = module_manager.physical_configurable_children(curr_module)[ichild]
ModuleId phy_mem_submodule = module_manager.logical2physical_configurable_children(curr_module)[ichild]
auto result = logical_mem_child_inst_count.find(phy_mem_submodule);
if (result == logical_mem_child_inst_count.end()) {
logical_mem_child_inst_count.find[phy_mem_submodule] = 0;
}
module_manager.set_physical_configurable_child_instance(curr_module, ichild, logical_mem_child_inst_count[phy_mem_submodule]);
module_manager.set_physical_configurable_child_parent_module(curr_module, ichild, phy_mem_module);
module_manager.set_logical2physical_configurable_child_instance(curr_module, ichild, logical_mem_child_inst_count[phy_mem_submodule]);
module_manager.set_logical2physical_configurable_child_parent_module(curr_module, ichild, phy_mem_module);
logical_mem_child_inst_count[phy_mem_submodule]++;
} else {
rec_find_physical_memory_children(module_manager, logical_child, physical_memory_children, logical_mem_child_inst_count);

117
openfpga/src/utils/module_manager_utils.cpp
View File

@ -1018,7 +1018,8 @@ void add_module_nets_between_logic_and_memory_sram_bus(
void add_module_nets_cmos_flatten_memory_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_port_type& config_port_type) {
const e_circuit_model_port_type& config_port_type,
const ModuleManager::e_config_child_type& config_child_type) {
/* A counter for the current pin id for the source port of parent module */
size_t cur_src_pin_id = 0;
@ -1040,7 +1041,7 @@ void add_module_nets_cmos_flatten_memory_config_bus(
module_manager.module_port(net_src_module_id, net_src_port_id);
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module).size();
mem_index < module_manager.num_configurable_children(parent_module, config_child_type);
++mem_index) {
ModuleId net_sink_module_id;
size_t net_sink_instance_id;
@ -1050,9 +1051,9 @@ void add_module_nets_cmos_flatten_memory_config_bus(
std::string sink_port_name =
generate_sram_port_name(sram_orgz_type, config_port_type);
net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
@ -1273,9 +1274,10 @@ void add_module_nets_cmos_memory_bank_wl_config_bus(
*********************************************************************/
void add_module_nets_cmos_memory_chain_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type) {
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type) {
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module).size();
mem_index < module_manager.num_configurable_children(parent_module, config_child_type);
++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
@ -1297,27 +1299,27 @@ void add_module_nets_cmos_memory_chain_config_bus(
/* Find the port name of next memory module */
std::string sink_port_name = generate_configuration_chain_head_name();
net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
} else {
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
net_src_module_id =
module_manager.configurable_children(parent_module)[mem_index - 1];
module_manager.configurable_children(parent_module, config_child_type)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module)[mem_index - 1];
parent_module, config_child_type)[mem_index - 1];
net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
/* Find the port name of next memory module */
std::string sink_port_name = generate_configuration_chain_head_name();
net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
}
@ -1351,9 +1353,9 @@ void add_module_nets_cmos_memory_chain_config_bus(
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
ModuleId net_src_module_id =
module_manager.configurable_children(parent_module).back();
module_manager.configurable_children(parent_module, config_child_type).back();
size_t net_src_instance_id =
module_manager.configurable_child_instances(parent_module).back();
module_manager.configurable_child_instances(parent_module, config_child_type).back();
ModulePortId net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
@ -1407,9 +1409,10 @@ void add_module_nets_cmos_memory_chain_config_bus(
*
*********************************************************************/
static void add_module_nets_cmos_memory_frame_short_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module) {
ModuleManager& module_manager, const ModuleId& parent_module,
const ModuleManager::e_config_child_type& config_child_type) {
std::vector<ModuleId> configurable_children =
module_manager.configurable_children(parent_module);
module_manager.configurable_children(parent_module, config_child_type);
VTR_ASSERT(1 == configurable_children.size());
ModuleId child_module = configurable_children[0];
@ -1491,9 +1494,10 @@ static void add_module_nets_cmos_memory_frame_short_config_bus(
*********************************************************************/
static void add_module_nets_cmos_memory_frame_decoder_config_bus(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const ModuleId& parent_module) {
const ModuleId& parent_module,
const ModuleManager::e_config_child_type& config_child_type) {
std::vector<ModuleId> configurable_children =
module_manager.configurable_children(parent_module);
module_manager.configurable_children(parent_module, config_child_type);
/* Find the decoder specification */
size_t addr_size =
@ -1572,7 +1576,7 @@ static void add_module_nets_cmos_memory_frame_decoder_config_bus(
++mem_index) {
ModuleId child_module = configurable_children[mem_index];
size_t child_instance =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
ModulePortId child_addr_port = module_manager.find_module_port(
child_module, std::string(DECODER_ADDRESS_PORT_NAME));
BasicPort child_addr_port_info =
@ -1604,7 +1608,7 @@ static void add_module_nets_cmos_memory_frame_decoder_config_bus(
++mem_index) {
ModuleId child_module = configurable_children[mem_index];
size_t child_instance =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
ModulePortId child_din_port = module_manager.find_module_port(
child_module, std::string(DECODER_DATA_IN_PORT_NAME));
add_module_bus_nets(module_manager, parent_module, parent_module, 0,
@ -1625,7 +1629,7 @@ static void add_module_nets_cmos_memory_frame_decoder_config_bus(
++mem_index) {
ModuleId child_module = configurable_children[mem_index];
size_t child_instance =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
ModulePortId child_en_port = module_manager.find_module_port(
child_module, std::string(DECODER_ENABLE_PORT_NAME));
BasicPort child_en_port_info =
@ -1649,7 +1653,7 @@ static void add_module_nets_cmos_memory_frame_decoder_config_bus(
}
/* Add the decoder as the last configurable children */
module_manager.add_configurable_child(parent_module, decoder_module, 0);
module_manager.add_configurable_child(parent_module, decoder_module, 0, config_child_type);
}
/*********************************************************************
@ -1663,18 +1667,19 @@ static void add_module_nets_cmos_memory_frame_decoder_config_bus(
**********************************************************************/
void add_module_nets_cmos_memory_frame_config_bus(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const ModuleId& parent_module) {
if (0 == module_manager.configurable_children(parent_module).size()) {
const ModuleId& parent_module,
const ModuleManager::e_config_child_type& config_child_type) {
if (0 == module_manager.num_configurable_children(parent_module, config_child_type)) {
return;
}
if (1 == module_manager.configurable_children(parent_module).size()) {
if (1 == module_manager.num_configurable_children(parent_module, config_child_type)) {
add_module_nets_cmos_memory_frame_short_config_bus(module_manager,
parent_module);
parent_module, config_child_type);
} else {
VTR_ASSERT(1 < module_manager.configurable_children(parent_module).size());
VTR_ASSERT(1 < module_manager.num_configurable_children(parent_module, config_child_type));
add_module_nets_cmos_memory_frame_decoder_config_bus(
module_manager, decoder_lib, parent_module);
module_manager, decoder_lib, parent_module, config_child_type);
}
}
@ -1724,27 +1729,33 @@ void add_module_nets_cmos_memory_frame_config_bus(
**********************************************************************/
static void add_module_nets_cmos_memory_config_bus(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const ModuleId& parent_module, const e_config_protocol_type& sram_orgz_type) {
const ModuleId& parent_module, const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type) {
switch (sram_orgz_type) {
case CONFIG_MEM_SCAN_CHAIN: {
add_module_nets_cmos_memory_chain_config_bus(
module_manager, parent_module, sram_orgz_type);
module_manager, parent_module, sram_orgz_type, config_child_type);
break;
}
case CONFIG_MEM_FEEDTHROUGH:
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL, config_child_type);
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BLB, config_child_type);
break;
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL, config_child_type);
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL, config_child_type);
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WLR);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WLR, config_child_type);
break;
case CONFIG_MEM_FRAME_BASED:
add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib,
parent_module);
parent_module, config_child_type);
break;
default:
VTR_LOGF_ERROR(__FILE__, __LINE__,
@ -1790,31 +1801,32 @@ static void add_module_nets_cmos_memory_config_bus(
**********************************************************************/
static void add_pb_module_nets_cmos_memory_config_bus(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const ModuleId& parent_module, const e_config_protocol_type& sram_orgz_type) {
const ModuleId& parent_module, const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type) {
switch (sram_orgz_type) {
case CONFIG_MEM_SCAN_CHAIN: {
add_module_nets_cmos_memory_chain_config_bus(
module_manager, parent_module, sram_orgz_type);
module_manager, parent_module, sram_orgz_type, config_child_type);
break;
}
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_QL_MEMORY_BANK:
add_module_nets_cmos_memory_bank_bl_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL, config_child_type);
add_module_nets_cmos_memory_bank_wl_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL, config_child_type);
add_module_nets_cmos_memory_bank_wl_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WLR);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WLR, config_child_type);
break;
case CONFIG_MEM_MEMORY_BANK:
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL, config_child_type);
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL, config_child_type);
break;
case CONFIG_MEM_FRAME_BASED:
add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib,
parent_module);
parent_module, config_child_type);
break;
default:
VTR_LOGF_ERROR(__FILE__, __LINE__,
@ -1880,11 +1892,12 @@ static void add_pb_module_nets_cmos_memory_config_bus(
void add_module_nets_memory_config_bus(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const ModuleId& parent_module, const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_design_tech& mem_tech) {
const e_circuit_model_design_tech& mem_tech,
const ModuleManager::e_config_child_type& config_child_type) {
switch (mem_tech) {
case CIRCUIT_MODEL_DESIGN_CMOS:
add_module_nets_cmos_memory_config_bus(module_manager, decoder_lib,
parent_module, sram_orgz_type);
parent_module, sram_orgz_type, config_child_type);
break;
case CIRCUIT_MODEL_DESIGN_RRAM:
/* TODO: */
@ -1911,11 +1924,12 @@ void add_module_nets_memory_config_bus(
void add_pb_module_nets_memory_config_bus(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const ModuleId& parent_module, const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_design_tech& mem_tech) {
const e_circuit_model_design_tech& mem_tech,
const ModuleManager::e_config_child_type& config_child_type) {
switch (mem_tech) {
case CIRCUIT_MODEL_DESIGN_CMOS:
add_pb_module_nets_cmos_memory_config_bus(module_manager, decoder_lib,
parent_module, sram_orgz_type);
parent_module, sram_orgz_type, config_child_type);
break;
case CIRCUIT_MODEL_DESIGN_RRAM:
/* TODO: */
@ -2366,7 +2380,8 @@ size_t find_module_num_shared_config_bits_from_child_modules(
size_t find_module_num_config_bits_from_child_modules(
ModuleManager& module_manager, const ModuleId& module_id,
const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type) {
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type) {
size_t num_config_bits = 0;
switch (sram_orgz_type) {
@ -2380,7 +2395,7 @@ size_t find_module_num_config_bits_from_child_modules(
* per configurable children
*/
for (const ModuleId& child :
module_manager.configurable_children(module_id)) {
module_manager.configurable_children(module_id, config_child_type)) {
num_config_bits += find_module_num_config_bits(
module_manager, child, circuit_lib, sram_model, sram_orgz_type);
}
@ -2393,7 +2408,7 @@ size_t find_module_num_config_bits_from_child_modules(
* - and the number of configurable children
*/
for (const ModuleId& child :
module_manager.configurable_children(module_id)) {
module_manager.configurable_children(module_id, config_child_type)) {
size_t temp_num_config_bits = find_module_num_config_bits(
module_manager, child, circuit_lib, sram_model, sram_orgz_type);
num_config_bits =
@ -2403,9 +2418,9 @@ size_t find_module_num_config_bits_from_child_modules(
/* If there are more than 2 configurable children, we need a decoder
* Otherwise, we can just short wire the address port to the children
*/
if (1 < module_manager.configurable_children(module_id).size()) {
if (1 < module_manager.num_configurable_children(module_id, config_child_type)) {
num_config_bits += find_mux_local_decoder_addr_size(
module_manager.configurable_children(module_id).size());
module_manager.num_configurable_children(module_id, config_child_type));
}
break;

18
openfpga/src/utils/module_manager_utils.h
View File

@ -110,7 +110,8 @@ void add_module_nets_between_logic_and_memory_sram_bus(
void add_module_nets_cmos_flatten_memory_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_port_type& config_port_type);
const e_circuit_model_port_type& config_port_type,
const ModuleManager::e_config_child_type& config_child_type);
void add_module_nets_cmos_memory_bank_bl_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module,
@ -124,21 +125,25 @@ void add_module_nets_cmos_memory_bank_wl_config_bus(
void add_module_nets_cmos_memory_chain_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type);
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type);
void add_module_nets_cmos_memory_frame_config_bus(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const ModuleId& parent_module);
const ModuleId& parent_module,
const ModuleManager::e_config_child_type& config_child_type);
void add_module_nets_memory_config_bus(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const ModuleId& parent_module, const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_design_tech& mem_tech);
const e_circuit_model_design_tech& mem_tech,
const ModuleManager::e_config_child_type& config_child_type);
void add_pb_module_nets_memory_config_bus(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const ModuleId& parent_module, const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_design_tech& mem_tech);
const e_circuit_model_design_tech& mem_tech,
const ModuleManager::e_config_child_type& config_child_type);
size_t find_module_num_shared_config_bits(const ModuleManager& module_manager,
const ModuleId& module_id);
@ -146,7 +151,8 @@ size_t find_module_num_shared_config_bits(const ModuleManager& module_manager,
size_t find_module_num_config_bits(
const ModuleManager& module_manager, const ModuleId& module_id,
const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type);
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type);
void add_module_global_input_ports_from_child_modules(
ModuleManager& module_manager, const ModuleId& module_id,