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OpenFPGA
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[core] syntax

This commit is contained in:
tangxifan 2023-09-16 18:16:30 -07:00
parent d61d88f12e
commit 6fc2924438
2 changed files with 3 additions and 2 deletions
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2
openfpga/src/base/openfpga_verilog_template.h
View File

@ -63,7 +63,7 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
openfpga_ctx.blwl_shift_register_banks(), openfpga_ctx.arch().circuit_lib,
openfpga_ctx.mux_lib(), openfpga_ctx.decoder_lib(), g_vpr_ctx.device(),
openfpga_ctx.vpr_device_annotation(), openfpga_ctx.device_rr_gsb(),
openfpga_ctx.fabric_tile(), options);
openfpga_ctx.fabric_tile(), openfpga_ctx.module_name_map(), options);
}
/********************************************************************

3
openfpga/src/fpga_verilog/verilog_routing.cpp
View File

@ -248,6 +248,7 @@ static void print_verilog_routing_switch_box_unique_module(
*******************************************************************/
static void print_verilog_flatten_connection_block_modules(
NetlistManager& netlist_manager, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const DeviceRRGSB& device_rr_gsb, const std::string& subckt_dir,
const std::string& subckt_dir_name, const t_rr_type& cb_type,
const FabricVerilogOption& options) {
@ -265,7 +266,7 @@ static void print_verilog_flatten_connection_block_modules(
continue;
}
print_verilog_routing_connection_box_unique_module(
netlist_manager, module_manager, subckt_dir, subckt_dir_name, rr_gsb,
netlist_manager, module_manager, module_name_map, subckt_dir, subckt_dir_name, rr_gsb,
cb_type, options);
}
}