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[core] fixed a bug

This commit is contained in:
tangxifan 2023-09-18 20:43:15 -07:00
parent 0495ea67cc
commit 4d11f73471
1 changed files with 3 additions and 1 deletions
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4
openfpga/src/fpga_verilog/verilog_top_module.cpp
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@ -32,7 +32,9 @@ void print_verilog_core_module(NetlistManager& netlist_manager,
/* Create a module as the top-level fabric, and add it to the module manager
*/
std::string core_module_name = generate_fpga_core_module_name();
core_module_name = module_name_map.name(core_module_name);
if (module_name_map.name_exist(core_module_name)) {
core_module_name = module_name_map.name(core_module_name);
}
ModuleId core_module = module_manager.find_module(core_module_name);
/* It could happen that the module does not exist, just return with no errors
*/