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[core] fixed a bug on cb instance name. Spot some bug in port naming for tile modules

This commit is contained in:
tangxifan 2023-07-27 10:42:56 -07:00
parent 97219fd825
commit be0715a81c
2 changed files with 6 additions and 2 deletions
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5
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -902,8 +902,9 @@ static int build_tile_module_ports_from_cb(
*/
vtr::Point<size_t> cb_coord_in_unique_tile =
fabric_tile.cb_coordinates(curr_fabric_tile_id, cb_type)[icb];
std::string cb_instance_name_in_tile =
generate_connection_block_module_name(cb_type, cb_coord_in_unique_tile);
const RRGSB& unique_rr_gsb = device_rr_gsb.get_gsb(cb_coord_in_unique_tile);
std::string cb_instance_name_in_tile = generate_connection_block_module_name(
cb_type, unique_rr_gsb.get_cb_coordinate(cb_type));
vtr::Point<size_t> tile_coord =
fabric_tile.tile_coordinate(curr_fabric_tile_id);

3
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -878,6 +878,9 @@ static int build_top_module_tile_nets_between_sb_and_cb(
cb_type, cb_port_direction, use_cb_upper_port);
std::string cb_tile_cb_port_name = generate_tile_module_port_name(
cb_instance_name_in_unique_tile, cb_port_name);
VTR_LOGV(
verbose, "Finding port '%s' from connection block in tile [%lu][%lu]\n",
cb_tile_cb_port_name.c_str(), cb_tile_coord.x(), cb_tile_coord.y());
ModulePortId cb_port_id =
module_manager.find_module_port(cb_tile_module, cb_tile_cb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(cb_tile_module,