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[core] fixed a bug on loading subkey to support fabric keys

This commit is contained in:
tangxifan 2023-08-07 10:40:22 -07:00
parent 4ed83cdb17
commit 4d37421735
9 changed files with 28 additions and 16 deletions
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2
openfpga/src/fabric/build_device_module.cpp
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@ -134,7 +134,7 @@ int build_device_module_graph(
openfpga_ctx.device_rr_gsb(), openfpga_ctx.tile_direct(),
openfpga_ctx.arch().arch_direct, openfpga_ctx.arch().config_protocol,
sram_model, fabric_tile, frame_view, compress_routing, duplicate_grid_pin,
fabric_key, generate_random_fabric_key, verbose);
fabric_key, generate_random_fabric_key, group_config_block, verbose);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;

8
openfpga/src/fabric/build_top_module.cpp
View File

@ -57,7 +57,8 @@ int build_top_module(
const CircuitModelId& sram_model, const FabricTile& fabric_tile,
const bool& frame_view, const bool& compact_routing_hierarchy,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const bool& generate_random_fabric_key, const bool& verbose) {
const bool& generate_random_fabric_key, const bool& group_config_block,
const bool& verbose) {
vtr::ScopedStartFinishTimer timer("Build FPGA fabric module");
int status = CMD_EXEC_SUCCESS;
@ -75,14 +76,15 @@ int build_top_module(
module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk,
rr_clock_lookup, vpr_device_annotation, grids, tile_annotation, rr_graph,
device_rr_gsb, tile_direct, arch_direct, config_protocol, sram_model,
frame_view, compact_routing_hierarchy, duplicate_grid_pin, fabric_key);
frame_view, compact_routing_hierarchy, duplicate_grid_pin, fabric_key,
group_config_block);
} else {
/* TODO: Build the tile instances under the top module */
status = build_top_module_tile_child_instances(
module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk,
rr_clock_lookup, vpr_device_annotation, grids, tile_annotation, rr_graph,
device_rr_gsb, tile_direct, arch_direct, fabric_tile, config_protocol,
sram_model, fabric_key, frame_view, verbose);
sram_model, fabric_key, group_config_block, frame_view, verbose);
}
if (status != CMD_EXEC_SUCCESS) {

3
openfpga/src/fabric/build_top_module.h
View File

@ -44,7 +44,8 @@ int build_top_module(
const CircuitModelId& sram_model, const FabricTile& fabric_tile,
const bool& frame_view, const bool& compact_routing_hierarchy,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const bool& generate_random_fabric_key, const bool& verbose);
const bool& generate_random_fabric_key, const bool& group_config_block,
const bool& verbose);
} /* end namespace openfpga */

5
openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp
View File

@ -436,7 +436,7 @@ int build_top_module_fine_grained_child_instances(
const ArchDirect& arch_direct, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const bool& frame_view,
const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
const FabricKey& fabric_key) {
const FabricKey& fabric_key, const bool& group_config_block) {
int status = CMD_EXEC_SUCCESS;
std::map<t_rr_type, vtr::Matrix<size_t>> cb_instance_ids;
@ -529,7 +529,8 @@ int build_top_module_fine_grained_child_instances(
/* Update the memory organization in sub module (non-top) */
status = load_submodules_memory_modules_from_fabric_key(
module_manager, circuit_lib, config_protocol, fabric_key);
module_manager, circuit_lib, config_protocol, fabric_key,
group_config_block);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}

2
openfpga/src/fabric/build_top_module_child_fine_grained_instance.h
View File

@ -43,7 +43,7 @@ int build_top_module_fine_grained_child_instances(
const ArchDirect& arch_direct, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const bool& frame_view,
const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
const FabricKey& fabric_key);
const FabricKey& fabric_key, const bool& group_config_block);
} /* end namespace openfpga */

6
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1864,7 +1864,8 @@ int build_top_module_tile_child_instances(
const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct,
const ArchDirect& arch_direct, const FabricTile& fabric_tile,
const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
const FabricKey& fabric_key, const bool& frame_view, const bool& verbose) {
const FabricKey& fabric_key, const bool& group_config_block,
const bool& frame_view, const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
vtr::Matrix<size_t> tile_instance_ids;
status = add_top_module_tile_instances(module_manager, top_module,
@ -1946,7 +1947,8 @@ int build_top_module_tile_child_instances(
/* Update the memory organization in sub module (non-top) */
status = load_submodules_memory_modules_from_fabric_key(
module_manager, circuit_lib, config_protocol, fabric_key);
module_manager, circuit_lib, config_protocol, fabric_key,
group_config_block);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}

3
openfpga/src/fabric/build_top_module_child_tile_instance.h
View File

@ -42,7 +42,8 @@ int build_top_module_tile_child_instances(
const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct,
const ArchDirect& arch_direct, const FabricTile& fabric_tile,
const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
const FabricKey& fabric_key, const bool& frame_view, const bool& verbose);
const FabricKey& fabric_key, const bool& group_config_block,
const bool& frame_view, const bool& verbose);
} /* end namespace openfpga */

12
openfpga/src/utils/module_manager_memory_utils.cpp
View File

@ -516,7 +516,8 @@ static int rebuild_submodule_configurable_children_nets(
static int load_and_update_submodule_memory_modules_from_fabric_key(
ModuleManager& module_manager, const ModuleId& module_id,
const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
const FabricKey& fabric_key, const FabricKeyModuleId& key_module_id) {
const FabricKey& fabric_key, const FabricKeyModuleId& key_module_id,
const bool& group_config_block) {
int status = CMD_EXEC_SUCCESS;
/* Compare the configurable children list */
if (submodule_memory_modules_match_fabric_key(module_manager, module_id,
@ -533,7 +534,9 @@ static int load_and_update_submodule_memory_modules_from_fabric_key(
/* Overwrite the configurable children list */
status = update_submodule_memory_modules_from_fabric_key(
module_manager, module_id, circuit_lib, config_protocol,
ModuleManager::e_config_child_type::PHYSICAL, fabric_key, key_module_id);
group_config_block ? ModuleManager::e_config_child_type::PHYSICAL
: ModuleManager::e_config_child_type::UNIFIED,
fabric_key, key_module_id);
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
}
@ -553,7 +556,8 @@ static int load_and_update_submodule_memory_modules_from_fabric_key(
*******************************************************************/
int load_submodules_memory_modules_from_fabric_key(
ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const ConfigProtocol& config_protocol, const FabricKey& fabric_key) {
const ConfigProtocol& config_protocol, const FabricKey& fabric_key,
const bool& group_config_block) {
int status = CMD_EXEC_SUCCESS;
for (FabricKeyModuleId key_module_id : fabric_key.modules()) {
std::string module_name = fabric_key.module_name(key_module_id);
@ -569,7 +573,7 @@ int load_submodules_memory_modules_from_fabric_key(
/* This is a valid module, try to load and update */
status = load_and_update_submodule_memory_modules_from_fabric_key(
module_manager, module_id, circuit_lib, config_protocol, fabric_key,
key_module_id);
key_module_id, group_config_block);
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
}

3
openfpga/src/utils/module_manager_memory_utils.h
View File

@ -34,7 +34,8 @@ namespace openfpga {
int load_submodules_memory_modules_from_fabric_key(
ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const ConfigProtocol& config_protocol, const FabricKey& fabric_key);
const ConfigProtocol& config_protocol, const FabricKey& fabric_key,
const bool& group_config_block);
} /* end namespace openfpga */