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[core] fixed some bugs in spotting the correct pin index of given subtiles

This commit is contained in:
tangxifan 2023-08-18 21:04:37 -07:00
parent 2cd8c6e0f1
commit fc523bed32
2 changed files with 25 additions and 25 deletions
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5
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1341,8 +1341,8 @@ static int build_top_module_global_net_for_given_tile_module(
return CMD_EXEC_FATAL_ERROR;
}
grid_pin_start_index =
(subtile_index - sub_tile.capacity.low) * sub_tile_num_pins +
tile_port.absolute_first_pin_index;
sub_tile.sub_tile_to_tile_pin_indices[(subtile_index - sub_tile.capacity.low) * sub_tile_num_pins +
tile_port.absolute_first_pin_index];
physical_tile_port = tile_port;
break;
}
@ -1386,6 +1386,7 @@ static int build_top_module_global_net_for_given_tile_module(
generate_tile_module_port_name(grid_instance_name, grid_port_name);
ModulePortId tile_grid_port_id =
module_manager.find_module_port(tile_module, tile_grid_port_name);
VTR_LOG("Finding global port '%s' from grid '%s'\n", tile_grid_port_name.c_str(), tile_module_name.c_str());
VTR_ASSERT(true == module_manager.valid_module_port_id(
tile_module, tile_grid_port_id));

45
openfpga/src/utils/check_tile_annotation.cpp
View File

@ -128,7 +128,6 @@ static int check_tile_annotation_conflicts_with_physical_tile(
++tile_info_id) {
/* Must find a valid physical tile in the same name */
size_t found_matched_physical_tile = 0;
size_t found_matched_physical_tile_port = 0;
std::string required_tile_name =
tile_annotation.global_port_tile_names(tile_global_port)[tile_info_id];
@ -146,6 +145,7 @@ static int check_tile_annotation_conflicts_with_physical_tile(
/* Must found a valid port where both port name and port size must
* match!!! */
for (const t_sub_tile& sub_tile : physical_tile.sub_tiles) {
size_t found_matched_physical_tile_port = 0;
for (const t_physical_tile_port& tile_port : sub_tile.ports) {
if (std::string(tile_port.name) != required_tile_port.get_name()) {
continue;
@ -167,7 +167,7 @@ static int check_tile_annotation_conflicts_with_physical_tile(
}
/* Check if port property matches */
int grid_pin_index = tile_port.absolute_first_pin_index;
int grid_pin_index = sub_tile.sub_tile_to_tile_pin_indices[tile_port.absolute_first_pin_index];
if (tile_port.is_clock !=
tile_annotation.global_port_is_clock(tile_global_port)) {
@ -215,6 +215,26 @@ static int check_tile_annotation_conflicts_with_physical_tile(
found_matched_physical_tile_port++;
}
if (0 == found_matched_physical_tile_port) {
VTR_LOGF_ERROR(
__FILE__, __LINE__,
"Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' does not match "
"any physical tile port!\n",
required_tile_name.c_str(), required_tile_port.get_name().c_str(),
required_tile_port.get_lsb(), required_tile_port.get_msb(),
tile_annotation.global_port_name(tile_global_port).c_str());
num_err++;
}
if (1 < found_matched_physical_tile_port) {
VTR_LOGF_ERROR(
__FILE__, __LINE__,
"Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' match more than "
"1 physical tile port!\n",
required_tile_name.c_str(), required_tile_port.get_name().c_str(),
required_tile_port.get_lsb(), required_tile_port.get_msb(),
tile_annotation.global_port_name(tile_global_port).c_str());
num_err++;
}
}
}
@ -228,17 +248,6 @@ static int check_tile_annotation_conflicts_with_physical_tile(
tile_annotation.global_port_name(tile_global_port).c_str());
num_err++;
}
if (0 == found_matched_physical_tile_port) {
VTR_LOGF_ERROR(
__FILE__, __LINE__,
"Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' does not match "
"any physical tile port!\n",
required_tile_name.c_str(), required_tile_port.get_name().c_str(),
required_tile_port.get_lsb(), required_tile_port.get_msb(),
tile_annotation.global_port_name(tile_global_port).c_str());
num_err++;
}
/* If we found more than 1 match, error out */
if (1 < found_matched_physical_tile) {
VTR_LOGF_ERROR(
@ -249,16 +258,6 @@ static int check_tile_annotation_conflicts_with_physical_tile(
tile_annotation.global_port_name(tile_global_port).c_str());
num_err++;
}
if (1 < found_matched_physical_tile_port) {
VTR_LOGF_ERROR(
__FILE__, __LINE__,
"Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' match more than "
"1 physical tile port!\n",
required_tile_name.c_str(), required_tile_port.get_name().c_str(),
required_tile_port.get_lsb(), required_tile_port.get_msb(),
tile_annotation.global_port_name(tile_global_port).c_str());
num_err++;
}
}
}