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[core] code format

This commit is contained in:
tangxifan 2023-09-06 22:40:59 -07:00
parent 2fee56548b
commit bcb82d43af
1 changed files with 3 additions and 3 deletions
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6
openfpga/src/fpga_verilog/verilog_writer_utils.cpp
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@ -33,8 +33,8 @@ void print_verilog_default_net_type_declaration(
VTR_ASSERT(true == valid_file_stream(fp));
fp << "//----- Default net type -----" << std::endl;
fp << "`default_nettype "
<< VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] << std::endl;
fp << "`default_nettype " << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type]
<< std::endl;
fp << std::endl;
}
@ -343,7 +343,7 @@ void print_verilog_module_declaration(
/* Apply default net type from user's option */
if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) {
print_verilog_default_net_type_declaration(fp, default_net_type);
}
}
print_verilog_module_definition(fp, module_manager, module_id);