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[core] code format

This commit is contained in:
tangxifan 2023-09-06 22:29:30 -07:00
parent f8b2eec988
commit f544953085
8 changed files with 32 additions and 20 deletions
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9
openfpga/src/fpga_verilog/verilog_essential_gates.cpp
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@ -209,7 +209,8 @@ static void print_verilog_invbuf_module(
print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
/* Put an end to the Verilog module */
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), default_net_type);
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model),
default_net_type);
}
/************************************************
@ -290,7 +291,8 @@ static void print_verilog_passgate_module(
print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
/* Put an end to the Verilog module */
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), default_net_type);
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model),
default_net_type);
}
/************************************************
@ -494,7 +496,8 @@ static void print_verilog_gate_module(
print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
/* Put an end to the Verilog module */
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), default_net_type);
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model),
default_net_type);
}
/************************************************

3
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -365,8 +365,7 @@ void print_verilog_random_top_testbench(
print_verilog_module_end(fp,
std::string(circuit_name) +
std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX),
VERILOG_DEFAULT_NET_TYPE_WIRE
);
VERILOG_DEFAULT_NET_TYPE_WIRE);
/* Close the file stream */
fp.close();

3
openfpga/src/fpga_verilog/verilog_module_writer.cpp
View File

@ -608,7 +608,8 @@ void write_verilog_module_to_file(
}
/* Print an end for the module */
print_verilog_module_end(fp, module_manager.module_name(module_id), default_net_type);
print_verilog_module_end(fp, module_manager.module_name(module_id),
default_net_type);
/* Print an empty line as splitter */
fp << std::endl;

7
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -654,9 +654,10 @@ int print_verilog_preconfig_top_module(
/* Testbench ends*/
print_verilog_module_end(
fp, std::string(circuit_name) +
std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX),
VERILOG_DEFAULT_NET_TYPE_WIRE);
fp,
std::string(circuit_name) +
std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX),
VERILOG_DEFAULT_NET_TYPE_WIRE);
/* Close the file stream */
fp.close();

7
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -2675,9 +2675,10 @@ int print_verilog_full_testbench(
/* Testbench ends*/
print_verilog_module_end(
fp, std::string(circuit_name) +
std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX),
VERILOG_DEFAULT_NET_TYPE_WIRE);
fp,
std::string(circuit_name) +
std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX),
VERILOG_DEFAULT_NET_TYPE_WIRE);
/* Close the file stream */
fp.close();

3
openfpga/src/fpga_verilog/verilog_wire.cpp
View File

@ -93,7 +93,8 @@ static void print_verilog_wire_module(
print_verilog_submodule_timing(fp, circuit_lib, wire_model);
/* Put an end to the Verilog module */
print_verilog_module_end(fp, circuit_lib.model_name(wire_model), default_net_type);
print_verilog_module_end(fp, circuit_lib.model_name(wire_model),
default_net_type);
/* Add an empty line as a splitter */
fp << std::endl;

16
openfpga/src/fpga_verilog/verilog_writer_utils.cpp
View File

@ -34,10 +34,12 @@ void print_verilog_default_net_type_declaration(
if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) {
fp << "//----- Default net type -----" << std::endl;
fp << "`default_nettype " << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type]
<< std::endl;
fp << "`default_nettype "
<< VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] << std::endl;
} else {
fp << "//----- Assume default net type to be " << VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_WIRE] << "-----" << std::endl;
fp << "//----- Assume default net type to be "
<< VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_WIRE]
<< "-----" << std::endl;
}
fp << std::endl;
}
@ -477,8 +479,9 @@ void print_verilog_module_instance(
/************************************************
* Print an end line for a Verilog module
***********************************************/
void print_verilog_module_end(std::fstream& fp,
const std::string& module_name, const e_verilog_default_net_type& default_net_type) {
void print_verilog_module_end(
std::fstream& fp, const std::string& module_name,
const e_verilog_default_net_type& default_net_type) {
VTR_ASSERT(true == valid_file_stream(fp));
fp << "endmodule" << std::endl;
@ -488,7 +491,8 @@ void print_verilog_module_end(std::fstream& fp,
/* Reset default net type to be none */
if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) {
print_verilog_default_net_type_declaration(fp, VERILOG_DEFAULT_NET_TYPE_WIRE);
print_verilog_default_net_type_declaration(fp,
VERILOG_DEFAULT_NET_TYPE_WIRE);
}
}

4
openfpga/src/fpga_verilog/verilog_writer_utils.h
View File

@ -82,7 +82,9 @@ void print_verilog_module_instance(
const std::map<std::string, BasicPort>& port2port_name_map,
const bool& use_explicit_port_map);
void print_verilog_module_end(std::fstream& fp, const std::string& module_name, const e_verilog_default_net_type& default_net_type);
void print_verilog_module_end(
std::fstream& fp, const std::string& module_name,
const e_verilog_default_net_type& default_net_type);
std::string generate_verilog_port(
const enum e_dump_verilog_port_type& dump_port_type,