diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
index fce1ae4b9..84d2e7d6c 100644
--- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
+++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
@@ -209,7 +209,8 @@ static void print_verilog_invbuf_module(
   print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
 
   /* Put an end to the Verilog module */
-  print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), default_net_type);
+  print_verilog_module_end(fp, circuit_lib.model_name(circuit_model),
+                           default_net_type);
 }
 
 /************************************************
@@ -290,7 +291,8 @@ static void print_verilog_passgate_module(
   print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
 
   /* Put an end to the Verilog module */
-  print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), default_net_type);
+  print_verilog_module_end(fp, circuit_lib.model_name(circuit_model),
+                           default_net_type);
 }
 
 /************************************************
@@ -494,7 +496,8 @@ static void print_verilog_gate_module(
   print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
 
   /* Put an end to the Verilog module */
-  print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), default_net_type);
+  print_verilog_module_end(fp, circuit_lib.model_name(circuit_model),
+                           default_net_type);
 }
 
 /************************************************
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
index 9d7ec498f..045a69024 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -365,8 +365,7 @@ void print_verilog_random_top_testbench(
   print_verilog_module_end(fp,
                            std::string(circuit_name) +
                              std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX),
-                           VERILOG_DEFAULT_NET_TYPE_WIRE
-                           );
+                           VERILOG_DEFAULT_NET_TYPE_WIRE);
 
   /* Close the file stream */
   fp.close();
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
index 251d9b063..af901e592 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
@@ -608,7 +608,8 @@ void write_verilog_module_to_file(
   }
 
   /* Print an end for the module */
-  print_verilog_module_end(fp, module_manager.module_name(module_id), default_net_type);
+  print_verilog_module_end(fp, module_manager.module_name(module_id),
+                           default_net_type);
 
   /* Print an empty line as splitter */
   fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index 3bb7b2086..550ba2d63 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -654,9 +654,10 @@ int print_verilog_preconfig_top_module(
 
   /* Testbench ends*/
   print_verilog_module_end(
-    fp, std::string(circuit_name) +
-          std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX),
-          VERILOG_DEFAULT_NET_TYPE_WIRE);
+    fp,
+    std::string(circuit_name) +
+      std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX),
+    VERILOG_DEFAULT_NET_TYPE_WIRE);
 
   /* Close the file stream */
   fp.close();
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 2fb8e1850..f7dd1b997 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -2675,9 +2675,10 @@ int print_verilog_full_testbench(
 
   /* Testbench ends*/
   print_verilog_module_end(
-    fp, std::string(circuit_name) +
-          std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX),
-          VERILOG_DEFAULT_NET_TYPE_WIRE);
+    fp,
+    std::string(circuit_name) +
+      std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX),
+    VERILOG_DEFAULT_NET_TYPE_WIRE);
 
   /* Close the file stream */
   fp.close();
diff --git a/openfpga/src/fpga_verilog/verilog_wire.cpp b/openfpga/src/fpga_verilog/verilog_wire.cpp
index e944ae8bb..544c3b7c9 100644
--- a/openfpga/src/fpga_verilog/verilog_wire.cpp
+++ b/openfpga/src/fpga_verilog/verilog_wire.cpp
@@ -93,7 +93,8 @@ static void print_verilog_wire_module(
   print_verilog_submodule_timing(fp, circuit_lib, wire_model);
 
   /* Put an end to the Verilog module */
-  print_verilog_module_end(fp, circuit_lib.model_name(wire_model), default_net_type);
+  print_verilog_module_end(fp, circuit_lib.model_name(wire_model),
+                           default_net_type);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index 2ab0888ea..a6dc76e8a 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -34,10 +34,12 @@ void print_verilog_default_net_type_declaration(
 
   if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) {
     fp << "//----- Default net type -----" << std::endl;
-    fp << "`default_nettype " << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type]
-     << std::endl;
+    fp << "`default_nettype "
+       << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] << std::endl;
   } else {
-    fp << "//----- Assume default net type to be " << VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_WIRE] << "-----" << std::endl;
+    fp << "//----- Assume default net type to be "
+       << VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_WIRE]
+       << "-----" << std::endl;
   }
   fp << std::endl;
 }
@@ -477,8 +479,9 @@ void print_verilog_module_instance(
 /************************************************
  * Print an end line for a Verilog module
  ***********************************************/
-void print_verilog_module_end(std::fstream& fp,
-                              const std::string& module_name, const e_verilog_default_net_type& default_net_type) {
+void print_verilog_module_end(
+  std::fstream& fp, const std::string& module_name,
+  const e_verilog_default_net_type& default_net_type) {
   VTR_ASSERT(true == valid_file_stream(fp));
 
   fp << "endmodule" << std::endl;
@@ -488,7 +491,8 @@ void print_verilog_module_end(std::fstream& fp,
 
   /* Reset default net type to be none */
   if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) {
-    print_verilog_default_net_type_declaration(fp, VERILOG_DEFAULT_NET_TYPE_WIRE);
+    print_verilog_default_net_type_declaration(fp,
+                                               VERILOG_DEFAULT_NET_TYPE_WIRE);
   }
 }
 
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h
index 5a7cfd040..665f191a2 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h
@@ -82,7 +82,9 @@ void print_verilog_module_instance(
   const std::map<std::string, BasicPort>& port2port_name_map,
   const bool& use_explicit_port_map);
 
-void print_verilog_module_end(std::fstream& fp, const std::string& module_name, const e_verilog_default_net_type& default_net_type);
+void print_verilog_module_end(
+  std::fstream& fp, const std::string& module_name,
+  const e_verilog_default_net_type& default_net_type);
 
 std::string generate_verilog_port(
   const enum e_dump_verilog_port_type& dump_port_type,