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[core] code format

This commit is contained in:
tangxifan 2023-08-05 20:53:58 -07:00
parent 2aab94cd6c
commit 68f07d6fc9
9 changed files with 133 additions and 118 deletions
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6
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -695,9 +695,9 @@ static void add_module_pb_graph_pin_interc(
mux_mem_module_name.c_str(), phy_mem_module_name.c_str());
module_manager.set_logical2physical_configurable_child(
pb_module, config_child_id, phy_mem_module);
std::string phy_mux_mem_instance_name = generate_pb_memory_instance_name(
GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string(""),
false);
std::string phy_mux_mem_instance_name =
generate_pb_memory_instance_name(
GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string(""), false);
module_manager.set_logical2physical_configurable_child_instance_name(
pb_module, config_child_id, phy_mux_mem_instance_name);
VTR_LOGV(verbose, "Now use a feedthrough memory for '%s'\n",

42
openfpga/src/fabric/build_memory_modules.cpp
View File

@ -7,8 +7,8 @@
#include <algorithm>
#include <ctime>
#include <string>
#include <map>
#include <string>
#include "build_decoder_modules.h"
#include "circuit_library_utils.h"
@ -1304,15 +1304,13 @@ static void add_module_output_nets_to_memory_group_module(
* - Add ports
* - Add nets
********************************************************************/
int build_memory_group_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const std::string& module_name,
const CircuitModelId& sram_model,
const std::vector<ModuleId>& child_modules,
const std::vector<std::string>& child_instance_names,
const size_t& num_mems, const bool& verbose) {
int build_memory_group_module(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type, const std::string& module_name,
const CircuitModelId& sram_model, const std::vector<ModuleId>& child_modules,
const std::vector<std::string>& child_instance_names, const size_t& num_mems,
const bool& verbose) {
VTR_LOGV(verbose, "Building memory group module '%s'...\n",
module_name.c_str());
ModuleId mem_module = module_manager.add_module(module_name);
@ -1336,13 +1334,17 @@ int build_memory_group_module(ModuleManager& module_manager,
module_manager.add_port(mem_module, outb_port,
ModuleManager::MODULE_OUTPUT_PORT);
/* Identify the duplicated instance name: This mainly comes from the grid modules, which contains multi-instanced blocks. Therefore, we just count the duplicated instance names and name each of them with a unique index, e.g., mem_lut -> mem_lut_0, mem_lut_1 etc. The only exception is for the uinque instance name, we keep the original instance name */
/* Identify the duplicated instance name: This mainly comes from the grid
* modules, which contains multi-instanced blocks. Therefore, we just count
* the duplicated instance names and name each of them with a unique index,
* e.g., mem_lut -> mem_lut_0, mem_lut_1 etc. The only exception is for the
* uinque instance name, we keep the original instance name */
std::vector<std::string> unique_child_instance_names;
unique_child_instance_names.reserve(child_instance_names.size());
std::map<std::string, size_t> unique_child_instance_name_count;
for (std::string curr_inst_name : child_instance_names) {
unique_child_instance_name_count[curr_inst_name]++;
}
}
std::map<std::string, size_t> unique_child_instance_name_scoreboard;
for (std::string curr_inst_name : child_instance_names) {
if (1 == unique_child_instance_name_count[curr_inst_name]) {
@ -1352,7 +1354,8 @@ int build_memory_group_module(ModuleManager& module_manager,
}
auto result = unique_child_instance_name_scoreboard.find(curr_inst_name);
if (result == unique_child_instance_name_scoreboard.end()) {
unique_child_instance_names.push_back(generate_instance_name(curr_inst_name, result->second));
unique_child_instance_names.push_back(
generate_instance_name(curr_inst_name, result->second));
unique_child_instance_name_scoreboard[curr_inst_name]++;
}
}
@ -1366,7 +1369,9 @@ int build_memory_group_module(ModuleManager& module_manager,
size_t child_instance =
module_manager.num_instance(mem_module, child_module);
module_manager.add_child_module(mem_module, child_module, false);
module_manager.set_child_instance_name(mem_module, child_module, child_instance, unique_child_instance_names[ichild]);
module_manager.set_child_instance_name(mem_module, child_module,
child_instance,
unique_child_instance_names[ichild]);
module_manager.add_configurable_child(
mem_module, child_module, child_instance,
ModuleManager::e_config_child_type::UNIFIED);
@ -1501,11 +1506,10 @@ int add_physical_memory_module(ModuleManager& module_manager,
module_manager.module_name(curr_module).c_str());
ModuleId phy_mem_module = module_manager.find_module(phy_mem_module_name);
if (!module_manager.valid_module_id(phy_mem_module)) {
status = build_memory_group_module(module_manager, decoder_lib, circuit_lib,
sram_orgz_type, phy_mem_module_name,
sram_model, required_phy_mem_modules,
required_phy_mem_instance_names,
module_num_config_bits, verbose);
status = build_memory_group_module(
module_manager, decoder_lib, circuit_lib, sram_orgz_type,
phy_mem_module_name, sram_model, required_phy_mem_modules,
required_phy_mem_instance_names, module_num_config_bits, verbose);
}
if (status != CMD_EXEC_SUCCESS) {
VTR_LOG_ERROR("Failed to create the physical memory module '%s'!\n",

16
openfpga/src/fabric/build_memory_modules.h
View File

@ -30,15 +30,13 @@ int build_memory_modules(ModuleManager& module_manager,
const bool& require_feedthrough_memory,
const bool& verbose);
int build_memory_group_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const std::string& module_name,
const CircuitModelId& sram_model,
const std::vector<ModuleId>& child_modules,
const std::vector<std::string>& child_instance_names,
const size_t& num_mems, const bool& verbose);
int build_memory_group_module(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type, const std::string& module_name,
const CircuitModelId& sram_model, const std::vector<ModuleId>& child_modules,
const std::vector<std::string>& child_instance_names, const size_t& num_mems,
const bool& verbose);
int add_physical_memory_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,

4
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -259,8 +259,8 @@ static void build_switch_block_mux_module(
module_manager.set_logical2physical_configurable_child(
sb_module, config_child_id, physical_mem_module);
std::string physical_mem_instance_name = generate_sb_memory_instance_name(
SWITCH_BLOCK_MEM_INSTANCE_PREFIX, chan_side, chan_node_id, std::string(""),
false);
SWITCH_BLOCK_MEM_INSTANCE_PREFIX, chan_side, chan_node_id,
std::string(""), false);
module_manager.set_logical2physical_configurable_child_instance_name(
sb_module, config_child_id, physical_mem_instance_name);
}

15
openfpga/src/fabric/module_manager.cpp
View File

@ -1004,7 +1004,8 @@ void ModuleManager::add_configurable_child(const ModuleId& parent_module,
if (type == ModuleManager::e_config_child_type::UNIFIED) {
logical2physical_configurable_children_[parent_module].push_back(
child_module);
logical2physical_configurable_child_instance_names_[parent_module].emplace_back();
logical2physical_configurable_child_instance_names_[parent_module]
.emplace_back();
} else if (type == ModuleManager::e_config_child_type::LOGICAL) {
logical2physical_configurable_children_[parent_module].emplace_back();
logical2physical_configurable_child_instance_names_[parent_module]
@ -1034,9 +1035,8 @@ void ModuleManager::set_logical2physical_configurable_child_instance_name(
num_configurable_children(
parent_module, ModuleManager::e_config_child_type::LOGICAL));
/* Create the pair */
logical2physical_configurable_child_instance_names_[parent_module]
[logical_child_id] =
physical_child_instance_name;
logical2physical_configurable_child_instance_names_
[parent_module][logical_child_id] = physical_child_instance_name;
}
void ModuleManager::reserve_configurable_child(
@ -1062,9 +1062,10 @@ void ModuleManager::reserve_configurable_child(
num_children);
}
if (num_children >
logical2physical_configurable_child_instance_names_[parent_module].size()) {
logical2physical_configurable_child_instance_names_[parent_module].reserve(
num_children);
logical2physical_configurable_child_instance_names_[parent_module]
.size()) {
logical2physical_configurable_child_instance_names_[parent_module]
.reserve(num_children);
}
}
if (type == ModuleManager::e_config_child_type::PHYSICAL ||

3
openfpga/src/fabric/module_manager.h
View File

@ -199,7 +199,8 @@ class ModuleManager {
*/
std::vector<ModuleId> logical2physical_configurable_children(
const ModuleId& parent_module) const;
/* Find all the instance names of configurable child modules under a parent module
/* Find all the instance names of configurable child modules under a parent
* module
*/
std::vector<std::string> logical2physical_configurable_child_instance_names(
const ModuleId& parent_module) const;

147
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -134,17 +134,19 @@ static void build_primitive_bitstream(
module_manager.module_port(mem_module, mem_out_port_id).get_width());
/* If there is a feedthrough module, we should consider the scoreboard */
std::string feedthru_mem_block_name = generate_memory_module_name(
circuit_lib, primitive_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX), true);
ModuleId feedthru_mem_module = module_manager.find_module(feedthru_mem_block_name);
std::string feedthru_mem_block_name =
generate_memory_module_name(circuit_lib, primitive_model, sram_models[0],
std::string(MEMORY_MODULE_POSTFIX), true);
ModuleId feedthru_mem_module =
module_manager.find_module(feedthru_mem_block_name);
if (module_manager.valid_module_id(feedthru_mem_module)) {
auto result = grouped_mem_inst_scoreboard.find(mem_block_name);
if (result == grouped_mem_inst_scoreboard.end()) {
/* Update scoreboard */
grouped_mem_inst_scoreboard[mem_block_name] = 1;
/* Update scoreboard */
grouped_mem_inst_scoreboard[mem_block_name] = 1;
} else {
mem_block_name = generate_instance_name(mem_block_name, result->second);
grouped_mem_inst_scoreboard[mem_block_name]++;
mem_block_name = generate_instance_name(mem_block_name, result->second);
grouped_mem_inst_scoreboard[mem_block_name]++;
}
}
@ -298,15 +300,17 @@ static void build_physical_block_pin_interc_bitstream(
/* If there is a feedthrough module, we should consider the scoreboard */
std::string feedthru_mem_block_name = generate_pb_memory_instance_name(
GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string(""), true);
ModuleId feedthru_mem_module = module_manager.find_module(feedthru_mem_block_name);
ModuleId feedthru_mem_module =
module_manager.find_module(feedthru_mem_block_name);
if (module_manager.valid_module_id(feedthru_mem_module)) {
auto result = grouped_mem_inst_scoreboard.find(mem_block_name);
if (result == grouped_mem_inst_scoreboard.end()) {
/* Update scoreboard */
grouped_mem_inst_scoreboard[mem_block_name] = 1;
/* Update scoreboard */
grouped_mem_inst_scoreboard[mem_block_name] = 1;
} else {
mem_block_name = generate_instance_name(mem_block_name, result->second);
grouped_mem_inst_scoreboard[mem_block_name]++;
mem_block_name =
generate_instance_name(mem_block_name, result->second);
grouped_mem_inst_scoreboard[mem_block_name]++;
}
}
ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name);
@ -383,9 +387,9 @@ static void build_physical_block_interc_port_bitstream(
for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport];
++ipin) {
build_physical_block_pin_interc_bitstream(
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, physical_pb,
bitstream_manager, grouped_mem_inst_scoreboard,
parent_configurable_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, bitstream_annotation, physical_pb,
&(physical_pb_graph_node->input_pins[iport][ipin]), physical_mode,
verbose);
}
@ -397,9 +401,9 @@ static void build_physical_block_interc_port_bitstream(
for (int ipin = 0;
ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) {
build_physical_block_pin_interc_bitstream(
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, physical_pb,
bitstream_manager, grouped_mem_inst_scoreboard,
parent_configurable_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, bitstream_annotation, physical_pb,
&(physical_pb_graph_node->output_pins[iport][ipin]), physical_mode,
verbose);
}
@ -411,9 +415,9 @@ static void build_physical_block_interc_port_bitstream(
for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport];
++ipin) {
build_physical_block_pin_interc_bitstream(
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, physical_pb,
bitstream_manager, grouped_mem_inst_scoreboard,
parent_configurable_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, bitstream_annotation, physical_pb,
&(physical_pb_graph_node->clock_pins[iport][ipin]), physical_mode,
verbose);
}
@ -456,10 +460,10 @@ static void build_physical_block_interc_bitstream(
* Note: it is not applied to primitive pb_type!
*/
build_physical_block_interc_port_bitstream(
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, module_manager, circuit_lib,
mux_lib, atom_ctx, device_annotation, bitstream_annotation,
physical_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_OUTPUT, physical_mode,
verbose);
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block,
module_manager, circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, physical_pb_graph_node, physical_pb,
CIRCUIT_PB_PORT_OUTPUT, physical_mode, verbose);
/* We check input_pins of child_pb_graph_node and its the input_edges
* Iterate over the interconnections between inputs of physical_pb_graph_node
@ -479,16 +483,16 @@ static void build_physical_block_interc_bitstream(
/* For each child_pb_graph_node input pins*/
build_physical_block_interc_port_bitstream(
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation,
child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_INPUT, physical_mode,
verbose);
bitstream_manager, grouped_mem_inst_scoreboard,
parent_configurable_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, bitstream_annotation, child_pb_graph_node,
physical_pb, CIRCUIT_PB_PORT_INPUT, physical_mode, verbose);
/* For clock pins, we should do the same work */
build_physical_block_interc_port_bitstream(
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation,
child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_CLOCK, physical_mode,
verbose);
bitstream_manager, grouped_mem_inst_scoreboard,
parent_configurable_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, bitstream_annotation, child_pb_graph_node,
physical_pb, CIRCUIT_PB_PORT_CLOCK, physical_mode, verbose);
}
}
}
@ -497,16 +501,14 @@ static void build_physical_block_interc_bitstream(
* Generate bitstream for a LUT and add it to bitstream manager
* This function supports both single-output and fracturable LUTs
*******************************************************************/
static void build_lut_bitstream(BitstreamManager& bitstream_manager,
std::map<std::string, size_t>& grouped_mem_inst_scoreboard,
const ConfigBlockId& parent_configurable_block,
const VprDeviceAnnotation& device_annotation,
const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib,
const PhysicalPb& physical_pb,
const PhysicalPbId& lut_pb_id,
t_pb_type* lut_pb_type, const bool& verbose) {
static void build_lut_bitstream(
BitstreamManager& bitstream_manager,
std::map<std::string, size_t>& grouped_mem_inst_scoreboard,
const ConfigBlockId& parent_configurable_block,
const VprDeviceAnnotation& device_annotation,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib, const PhysicalPb& physical_pb,
const PhysicalPbId& lut_pb_id, t_pb_type* lut_pb_type, const bool& verbose) {
/* Ensure a valid physical pritimive pb */
if (nullptr == lut_pb_type) {
VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid lut_pb_type!\n");
@ -648,17 +650,19 @@ static void build_lut_bitstream(BitstreamManager& bitstream_manager,
module_manager.module_port(mem_module, mem_out_port_id).get_width());
/* If there is a feedthrough module, we should consider the scoreboard */
std::string feedthru_mem_block_name = generate_memory_module_name(
circuit_lib, lut_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX), true);
ModuleId feedthru_mem_module = module_manager.find_module(feedthru_mem_block_name);
std::string feedthru_mem_block_name =
generate_memory_module_name(circuit_lib, lut_model, sram_models[0],
std::string(MEMORY_MODULE_POSTFIX), true);
ModuleId feedthru_mem_module =
module_manager.find_module(feedthru_mem_block_name);
if (module_manager.valid_module_id(feedthru_mem_module)) {
auto result = grouped_mem_inst_scoreboard.find(mem_block_name);
if (result == grouped_mem_inst_scoreboard.end()) {
/* Update scoreboard */
grouped_mem_inst_scoreboard[mem_block_name] = 1;
/* Update scoreboard */
grouped_mem_inst_scoreboard[mem_block_name] = 1;
} else {
mem_block_name = generate_instance_name(mem_block_name, result->second);
grouped_mem_inst_scoreboard[mem_block_name]++;
mem_block_name = generate_instance_name(mem_block_name, result->second);
grouped_mem_inst_scoreboard[mem_block_name]++;
}
}
@ -750,9 +754,9 @@ static void rec_build_physical_block_bitstream(
}
/* Go recursively */
rec_build_physical_block_bitstream(
bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block, module_manager, circuit_lib,
mux_lib, atom_ctx, device_annotation, bitstream_annotation,
border_side, physical_pb, child_pb,
bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block,
module_manager, circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, border_side, physical_pb, child_pb,
&(physical_pb_graph_node
->child_pb_graph_nodes[physical_mode->index][ipb][jpb]),
jpb, verbose);
@ -770,18 +774,19 @@ static void rec_build_physical_block_bitstream(
/* Special case for LUT !!!
* Mapped logical block information is stored in child_pbs of this pb!!!
*/
build_lut_bitstream(bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block,
device_annotation, module_manager, circuit_lib,
mux_lib, physical_pb, pb_id, physical_pb_type,
verbose);
build_lut_bitstream(bitstream_manager, grouped_mem_inst_scoreboard,
pb_configurable_block, device_annotation,
module_manager, circuit_lib, mux_lib, physical_pb,
pb_id, physical_pb_type, verbose);
break;
case CIRCUIT_MODEL_FF:
case CIRCUIT_MODEL_HARDLOGIC:
case CIRCUIT_MODEL_IOPAD:
/* For other types of blocks, we can apply a generic therapy */
build_primitive_bitstream(
bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block, module_manager, circuit_lib,
device_annotation, physical_pb, pb_id, physical_pb_type, verbose);
bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block,
module_manager, circuit_lib, device_annotation, physical_pb, pb_id,
physical_pb_type, verbose);
break;
default:
VTR_LOGF_ERROR(__FILE__, __LINE__,
@ -795,9 +800,10 @@ static void rec_build_physical_block_bitstream(
/* Generate the bitstream for the interconnection in this physical block */
build_physical_block_interc_bitstream(
bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block, module_manager, circuit_lib,
mux_lib, atom_ctx, device_annotation, bitstream_annotation,
physical_pb_graph_node, physical_pb, physical_mode, verbose);
bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block,
module_manager, circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, physical_pb_graph_node, physical_pb, physical_mode,
verbose);
}
/********************************************************************
@ -906,10 +912,11 @@ static void build_physical_block_bitstream(
place_annotation.grid_blocks(grid_coord)[z]) {
/* Recursively traverse the pb_graph and generate bitstream */
rec_build_physical_block_bitstream(
bitstream_manager, grouped_mem_inst_scoreboard, grid_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, border_side, PhysicalPb(),
PhysicalPbId::INVALID(), lb_type->pb_graph_head, z, verbose);
bitstream_manager, grouped_mem_inst_scoreboard,
grid_configurable_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, bitstream_annotation, border_side,
PhysicalPb(), PhysicalPbId::INVALID(), lb_type->pb_graph_head, z,
verbose);
} else {
const PhysicalPb& phy_pb = cluster_annotation.physical_pb(
place_annotation.grid_blocks(grid_coord)[z]);
@ -921,10 +928,10 @@ static void build_physical_block_bitstream(
/* Recursively traverse the pb_graph and generate bitstream */
rec_build_physical_block_bitstream(
bitstream_manager, grouped_mem_inst_scoreboard, grid_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, border_side, phy_pb, top_pb_id, pb_graph_head,
z, verbose);
bitstream_manager, grouped_mem_inst_scoreboard,
grid_configurable_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, bitstream_annotation, border_side,
phy_pb, top_pb_id, pb_graph_head, z, verbose);
}
}
}

16
openfpga/src/utils/memory_utils.cpp
View File

@ -528,17 +528,21 @@ int rec_find_physical_memory_children(
module_manager.logical2physical_configurable_child_instance_names(
curr_module)[ichild]);
VTR_LOGV(
verbose, "Collecting physical memory module '%s' with an instance name '%s'...\n",
verbose,
"Collecting physical memory module '%s' with an instance name "
"'%s'...\n",
module_manager
.module_name(module_manager.logical2physical_configurable_children(
curr_module)[ichild])
.c_str(),
module_manager.logical2physical_configurable_child_instance_names(
curr_module)[ichild].c_str()
);
module_manager
.logical2physical_configurable_child_instance_names(
curr_module)[ichild]
.c_str());
} else {
rec_find_physical_memory_children(module_manager, logical_child,
physical_memory_children, physical_memory_instance_names, verbose);
rec_find_physical_memory_children(
module_manager, logical_child, physical_memory_children,
physical_memory_instance_names, verbose);
}
}
return CMD_EXEC_SUCCESS;

2
openfpga/src/utils/memory_utils.h
View File

@ -4,8 +4,8 @@
/********************************************************************
* Include header files that are required by function declaration
*******************************************************************/
#include <vector>
#include <string>
#include <vector>
#include "circuit_types.h"
#include "config_protocol.h"