[core] code format
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@ -4,9 +4,9 @@
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*******************************************************************/
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/* Headers from system goes first */
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#include <algorithm>
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#include <string>
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#include <chrono>
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#include <ctime>
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#include <string>
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/* Headers from vtr util library */
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#include "vtr_assert.h"
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@ -28,8 +28,8 @@ namespace openfpga { // Begin namespace openfpga
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/********************************************************************
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* This function write header information to a bitstream file
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*******************************************************************/
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static void write_xml_module_name_map_file_head(std::fstream& fp,
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const bool& include_time_stamp) {
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static void write_xml_module_name_map_file_head(
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std::fstream& fp, const bool& include_time_stamp) {
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valid_file_stream(fp);
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fp << "<!--" << std::endl;
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@ -47,7 +47,6 @@ static void write_xml_module_name_map_file_head(std::fstream& fp,
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fp << std::endl;
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}
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/********************************************************************
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* A writer to output a I/O name mapping to XML format
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*
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@ -30,7 +30,8 @@ int main(int argc, const char** argv) {
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* This is optional only used when there is a second argument
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*/
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if (3 <= argc) {
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status = openfpga::write_xml_module_name_map(argv[2], module_name_map, true, true);
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status =
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openfpga::write_xml_module_name_map(argv[2], module_name_map, true, true);
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VTR_LOG("Write the module name mapping to an XML file: %s.\n", argv[2]);
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}
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@ -19,11 +19,11 @@
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#include "read_xml_fabric_key.h"
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#include "read_xml_io_name_map.h"
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#include "read_xml_module_name_map.h"
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#include "write_xml_module_name_map.h"
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#include "read_xml_tile_config.h"
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#include "rename_modules.h"
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#include "vtr_log.h"
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#include "vtr_time.h"
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#include "write_xml_module_name_map.h"
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/* begin namespace openfpga */
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namespace openfpga {
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@ -377,8 +377,9 @@ int rename_modules_template(T& openfpga_ctx, const Command& cmd,
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* Write module naming rules to a file
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*******************************************************************/
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template <class T>
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int write_module_naming_rules_template(const T& openfpga_ctx, const Command& cmd,
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const CommandContext& cmd_context) {
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int write_module_naming_rules_template(const T& openfpga_ctx,
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const Command& cmd,
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const CommandContext& cmd_context) {
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CommandOptionId opt_verbose = cmd.option("verbose");
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CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
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@ -393,12 +394,12 @@ int write_module_naming_rules_template(const T& openfpga_ctx, const Command& cmd
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std::string file_name = cmd_context.option_value(cmd, opt_file);
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/* Write hierarchy to a file */
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return write_xml_module_name_map(file_name.c_str(), openfpga_ctx.module_name_map(),
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!cmd_context.option_enable(cmd, opt_no_time_stamp),
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cmd_context.option_enable(cmd, opt_verbose));
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return write_xml_module_name_map(
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file_name.c_str(), openfpga_ctx.module_name_map(),
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!cmd_context.option_enable(cmd, opt_no_time_stamp),
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cmd_context.option_enable(cmd, opt_verbose));
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}
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} /* end namespace openfpga */
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#endif
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@ -845,9 +845,12 @@ ShellCommandId add_write_module_naming_rules_command_template(
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/* Add command to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(
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shell_cmd, "Output the naming rules for each module of an FPGA fabric to a given file", hidden);
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shell_cmd,
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"Output the naming rules for each module of an FPGA fabric to a given file",
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hidden);
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_const_execute_function(shell_cmd_id, write_module_naming_rules_template<T>);
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shell.set_command_const_execute_function(
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shell_cmd_id, write_module_naming_rules_template<T>);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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@ -855,7 +858,6 @@ ShellCommandId add_write_module_naming_rules_command_template(
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return shell_cmd_id;
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}
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template <class T>
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void add_setup_command_templates(openfpga::Shell<T>& shell,
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const bool& hidden = false) {
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@ -1093,9 +1095,9 @@ void add_setup_command_templates(openfpga::Shell<T>& shell,
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* 'build_fabric' */
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std::vector<ShellCommandId> cmd_dependency_write_module_naming_rules;
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cmd_dependency_write_module_naming_rules.push_back(build_fabric_cmd_id);
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add_write_module_naming_rules_command_template<T>(shell, openfpga_setup_cmd_class,
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cmd_dependency_write_module_naming_rules, hidden);
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add_write_module_naming_rules_command_template<T>(
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shell, openfpga_setup_cmd_class, cmd_dependency_write_module_naming_rules,
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hidden);
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}
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} /* end namespace openfpga */
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