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OpenFPGA
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[core] format

This commit is contained in:
tangxifan 2023-07-24 15:00:26 -07:00
parent 4294914987
commit 48b0ba8b78
4 changed files with 37 additions and 27 deletions
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3
openfpga/src/base/openfpga_build_fabric_template.h
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@ -186,7 +186,8 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd,
/* Build I/O location map */
openfpga_ctx.mutable_io_location_map() = build_fabric_io_location_map(
openfpga_ctx.module_graph(), g_vpr_ctx.device().grid, cmd_context.option_enable(cmd, opt_group_tile));
openfpga_ctx.module_graph(), g_vpr_ctx.device().grid,
cmd_context.option_enable(cmd, opt_group_tile));
/* Build fabric global port information */
openfpga_ctx.mutable_fabric_global_port_info() =

40
openfpga/src/fabric/build_fabric_io_location_map.cpp
View File

@ -31,8 +31,8 @@ namespace openfpga {
*io_children() list of top-level module. Here we just build a fast lookup from
*(x, y, z) coordinate to the actual indices
*******************************************************************/
static IoLocationMap build_fabric_fine_grained_io_location_map(const ModuleManager& module_manager,
const DeviceGrid& grids) {
static IoLocationMap build_fabric_fine_grained_io_location_map(
const ModuleManager& module_manager, const DeviceGrid& grids) {
vtr::ScopedStartFinishTimer timer(
"Create I/O location mapping for top module");
@ -152,8 +152,8 @@ static IoLocationMap build_fabric_fine_grained_io_location_map(const ModuleManag
*io_children() list of top-level module. Here we just build a fast lookup from
*(x, y, z) coordinate to the actual indices
*******************************************************************/
static IoLocationMap build_fabric_tiled_io_location_map(const ModuleManager& module_manager,
const DeviceGrid& grids) {
static IoLocationMap build_fabric_tiled_io_location_map(
const ModuleManager& module_manager, const DeviceGrid& grids) {
vtr::ScopedStartFinishTimer timer(
"Create I/O location mapping for top module");
@ -202,18 +202,20 @@ static IoLocationMap build_fabric_tiled_io_location_map(const ModuleManager& mod
VTR_ASSERT(size_t(phy_tile_type->capacity) ==
module_manager.io_children(child).size());
for (ModuleId tile_child : module_manager.io_children(child)) {
/* Note that we should use the subchild of the subchild module when checking the GPIO
* ports. The child module is the tile module while the subchild module is actually the grid-level I/O module, while
* the subchild module is the subtile inside grid-level I/O modules. Note
* that grid-level I/O module contains all the GPIO ports while the
* subtile may have part of it. For example, a grid I/O module may have 24
* GPINs and 12 GPOUTs, while the first subtile only have 4 GPINs, and the
* second subtile only have 3 GPOUTs. Therefore, to accurately build the
* I/O location map downto subtile level, we need to check the subchild
* module here.
/* Note that we should use the subchild of the subchild module when
* checking the GPIO ports. The child module is the tile module while the
* subchild module is actually the grid-level I/O module, while the
* subchild module is the subtile inside grid-level I/O modules. Note that
* grid-level I/O module contains all the GPIO ports while the subtile may
* have part of it. For example, a grid I/O module may have 24 GPINs and
* 12 GPOUTs, while the first subtile only have 4 GPINs, and the second
* subtile only have 3 GPOUTs. Therefore, to accurately build the I/O
* location map downto subtile level, we need to check the subchild module
* here.
*/
for (size_t isubchild = 0;
isubchild < module_manager.io_children(tile_child).size(); ++isubchild) {
isubchild < module_manager.io_children(tile_child).size();
++isubchild) {
ModuleId subchild = module_manager.io_children(tile_child)[isubchild];
vtr::Point<int> subchild_coord =
module_manager.io_child_coordinates(tile_child)[isubchild];
@ -237,9 +239,9 @@ static IoLocationMap build_fabric_tiled_io_location_map(const ModuleManager& mod
io_counter[gpio_port.get_name()] = 0;
}
/* This is a dirty hack! */
io_location_map.set_io_index(coord.x(), coord.y(), subchild_coord.x(),
gpio_port.get_name(),
io_counter[gpio_port.get_name()]);
io_location_map.set_io_index(
coord.x(), coord.y(), subchild_coord.x(), gpio_port.get_name(),
io_counter[gpio_port.get_name()]);
io_counter[gpio_port.get_name()]++;
}
}
@ -270,7 +272,8 @@ static IoLocationMap build_fabric_tiled_io_location_map(const ModuleManager& mod
/********************************************************************
* Top-level function, if tile modules are built under the top-level module
* The data to access for I/O location is different than the fine-grained grid modules
* The data to access for I/O location is different than the fine-grained grid
*modules
* FIXME: Think about a unified way for the two kinds of fabrics!!!
*******************************************************************/
IoLocationMap build_fabric_io_location_map(const ModuleManager& module_manager,
@ -282,5 +285,4 @@ IoLocationMap build_fabric_io_location_map(const ModuleManager& module_manager,
return build_fabric_fine_grained_io_location_map(module_manager, grids);
}
} /* end namespace openfpga */

5
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -1072,8 +1072,9 @@ static int build_tile_module(
pb_module_name.c_str(), tile_coord.x(), tile_coord.y());
pb_instances.push_back(pb_instance);
/* Add a custom I/O child with the grid */
module_manager.add_io_child(tile_module, pb_module, pb_instance,
vtr::Point<int>(grid_coord.x(), grid_coord.y()));
module_manager.add_io_child(
tile_module, pb_module, pb_instance,
vtr::Point<int>(grid_coord.x(), grid_coord.y()));
}
}

16
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -656,8 +656,11 @@ static int build_top_module_tile_nets_between_cb_and_pb(
top_module, net, sink_tile_module, sink_tile_instance_id,
sink_grid_port_id, sink_grid_port.pins()[pin_id]);
}
VTR_LOGV(verbose, "Built nets between connection block of tile[%lu][%lu] and grid block of tile[%lu][%lu]\n",
src_tile_coord.x(), src_tile_coord.y(), sink_tile_coord.x(), sink_tile_coord.y());
VTR_LOGV(verbose,
"Built nets between connection block of tile[%lu][%lu] and grid "
"block of tile[%lu][%lu]\n",
src_tile_coord.x(), src_tile_coord.y(), sink_tile_coord.x(),
sink_tile_coord.y());
}
}
return CMD_EXEC_SUCCESS;
@ -898,8 +901,11 @@ static int build_top_module_tile_nets_between_sb_and_cb(
tile_instance_id, sb_port_id,
itrack / 2);
}
VTR_LOGV(verbose, "Built nets between switch block of tile[%lu][%lu] and connection block of tile[%lu][%lu]\n",
sb_tile_coord.x(), sb_tile_coord.y(), cb_tile_coord.x(), cb_tile_coord.y());
VTR_LOGV(verbose,
"Built nets between switch block of tile[%lu][%lu] and "
"connection block of tile[%lu][%lu]\n",
sb_tile_coord.x(), sb_tile_coord.y(), cb_tile_coord.x(),
cb_tile_coord.y());
}
}
return CMD_EXEC_SUCCESS;
@ -1072,7 +1078,7 @@ static void organize_top_module_tile_based_memory_modules(
} else {
VTR_ASSERT(false == positive_direction);
/* For negative direction: -----> */
for (int ix = grids.width() - 1; ix >= 0; --ix) {
for (size_t ix = grids.width() - 1; ix >= 0; --ix) {
tile_coords.push_back(vtr::Point<size_t>(ix, iy));
}
}