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[core] syntax

This commit is contained in:
tangxifan 2023-08-03 17:33:57 -07:00
parent 5618f1d567
commit f4cbc95053
17 changed files with 103 additions and 92 deletions
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5
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -660,7 +660,7 @@ static void add_module_pb_graph_pin_interc(
module_manager.set_child_instance_name(
pb_module, mux_mem_module, mux_mem_instance, mux_mem_instance_name);
/* Add this MUX as a configurable child to the pb_module */
size_t config_child_id = module_manager.num_configurable_child(pb_module, ModuleManager::e_config_child_type::LOGICAL);
size_t config_child_id = module_manager.num_configurable_children(pb_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(pb_module, mux_mem_module,
mux_mem_instance, group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
if (group_config_block) {
@ -671,6 +671,7 @@ static void add_module_pb_graph_pin_interc(
VTR_ASSERT(true == module_manager.valid_module_id(phy_mem_module));
module_manager.set_logical2physical_configurable_child(pb_module, config_child_id,
phy_mem_module);
VTR_LOGV(verbose, "Now use a feedthrough memory for '%s'\n", phy_mem_module_name.c_str());
}
/* Add nets to connect SRAM ports of the MUX to the SRAM port of memory
@ -1076,7 +1077,7 @@ static void rec_build_logical_tile_modules(
*/
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, pb_module, circuit_lib, sram_model, mem_module_type);
module_manager, pb_module, circuit_lib, sram_model, mem_module_type, ModuleManager::e_config_child_type::LOGICAL);
if (0 < module_num_config_bits) {
add_sram_ports_to_module_manager(module_manager, pb_module, circuit_lib,
sram_model, mem_module_type,

18
openfpga/src/fabric/build_memory_modules.cpp
View File

@ -342,7 +342,7 @@ static void add_module_nets_to_cmos_memory_scan_chain_module(
net_src_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module)[mem_index - 1];
parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
@ -1225,7 +1225,7 @@ int build_memory_modules(ModuleManager& module_manager,
*-th pin of output port of the memory module, where W is the size of port
* 3. It assumes fixed port name for output ports
********************************************************************/
void add_module_output_nets_to_memory_group_module(
static void add_module_output_nets_to_memory_group_module(
ModuleManager& module_manager, const ModuleId& mem_module,
const std::string& mem_module_output_name, const ModuleId& child_module,
const size_t& output_pin_start_index, const size_t& child_instance) {
@ -1391,7 +1391,7 @@ int add_physical_memory_module(ModuleManager& module_manager,
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, curr_module, circuit_lib, sram_model, CONFIG_MEM_FEEDTHROUGH);
module_manager, curr_module, circuit_lib, sram_model, CONFIG_MEM_FEEDTHROUGH, ModuleManager::e_config_child_type::LOGICAL);
/* No need to build a memory when there are no configuration bits required */
if (module_num_config_bits == 0) {
return CMD_EXEC_SUCCESS;
@ -1399,7 +1399,7 @@ int add_physical_memory_module(ModuleManager& module_manager,
std::string phy_mem_module_name = generate_physical_memory_module_name(module_manager.module_name(curr_module), module_num_config_bits);
ModuleId phy_mem_module = module_manager.find_module(phy_mem_module_name);
if (!module_manager.valid_module_id(phy_mem_module)) {
status = build_memory_group_module(module_manager, decode_lib, circuit_lib, sram_orgz_type, phy_mem_module_name, sram_model, required_phy_mem_modules);
status = build_memory_group_module(module_manager, decoder_lib, circuit_lib, sram_orgz_type, phy_mem_module_name, sram_model, required_phy_mem_modules, module_num_config_bits);
}
if (status != CMD_EXEC_SUCCESS) {
VTR_LOG_ERROR("Failed to create the physical memory module '%s'!\n", phy_mem_module_name.c_str());
@ -1423,7 +1423,7 @@ int add_physical_memory_module(ModuleManager& module_manager,
mem2mem_port_map[CIRCUIT_MODEL_PORT_BL] = std::string(CONFIGURABLE_MEMORY_DATA_OUT_NAME);
mem2mem_port_map[CIRCUIT_MODEL_PORT_BLB] = std::string(CONFIGURABLE_MEMORY_INVERTED_DATA_OUT_NAME);
for (size_t ichild = 0; ichild < module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::PHYSICAL).size(); ++ichild) {
for (CircuitPortType port_type : {CIRCUIT_MODEL_PORT_BL, CIRCUIT_MODEL_PORT_BLB}) {
for (e_circuit_model_port_type port_type : {CIRCUIT_MODEL_PORT_BL, CIRCUIT_MODEL_PORT_BLB}) {
std::string src_port_name = mem2mem_port_map[port_type];
std::string des_port_name =
generate_sram_port_name(CONFIG_MEM_FEEDTHROUGH, port_type);
@ -1450,7 +1450,7 @@ int add_physical_memory_module(ModuleManager& module_manager,
/* Create a net and add source and sink to it */
ModuleNetId net = create_module_source_pin_net(
module_manager, curr_module, phy_mem_module, phy_mem_instance,
src_port_id, src_port.pins()[cur_mem_pin_index]);
src_port_id, src_port.pins()[curr_mem_pin_index]);
if (module_manager.valid_module_net_id(curr_module, net)) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1471,9 +1471,9 @@ int add_physical_memory_module(ModuleManager& module_manager,
}
/* Sanity check */
std::map<ModuleId, size_t> required_mem_child_inst_count;
for (ModuleId curr_module : module_manager.child_modules(phy_mem_module)) {
if (logical_mem_child_inst_count[curr_module] != module_manager.num_instance(phy_mem_module, curr_module)) {
VTR_LOG_ERROR("Expect the %lu instances of module '%s' under its parent '%s' while only updated %lu during logical-to-physical configurable child mapping sync-up!\n", module_manager.num_instance(phy_mem_module, curr_module), module_manager.module_name(curr_module).c_str(), module_manager.module_name(phy_mem_module).c_str(), logical_mem_child_inst_count[curr_module]);
for (ModuleId curr_child_module : module_manager.child_modules(phy_mem_module)) {
if (logical_mem_child_inst_count[curr_child_module] != module_manager.num_instance(phy_mem_module, curr_child_module)) {
VTR_LOG_ERROR("Expect the %lu instances of module '%s' under its parent '%s' while only updated %lu during logical-to-physical configurable child mapping sync-up!\n", module_manager.num_instance(phy_mem_module, curr_child_module), module_manager.module_name(curr_child_module).c_str(), module_manager.module_name(phy_mem_module).c_str(), logical_mem_child_inst_count[curr_child_module]);
return CMD_EXEC_FATAL_ERROR;
}
}

5
openfpga/src/fabric/build_memory_modules.h
View File

@ -22,7 +22,7 @@ std::vector<ModuleNetId> add_module_output_nets_to_chain_mem_modules(
const CircuitPortId& circuit_port, const ModuleId& child_module,
const size_t& child_index, const size_t& child_instance);
void build_memory_modules(ModuleManager& module_manager,
int build_memory_modules(ModuleManager& module_manager,
DecoderLibrary& arch_decoder_lib,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
@ -35,7 +35,8 @@ int build_memory_group_module(ModuleManager& module_manager,
const e_config_protocol_type& sram_orgz_type,
const std::string& module_name,
const CircuitModelId& sram_model,
const std::vector<ModuleId>& child_modules);
const std::vector<ModuleId>& child_modules,
const size_t& num_mems);
int add_physical_memory_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,

7
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -752,7 +752,7 @@ static void build_connection_block_mux_module(
module_manager, cb_module, mux_module, mux_instance_id, mem_module,
mem_instance_id, circuit_lib, mux_model);
/* Update memory and instance list */
size_t config_child_id = module_manager.num_configurable_children(cb_module);
size_t config_child_id = module_manager.num_configurable_children(cb_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(cb_module, mem_module, mem_instance_id, group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
/* For logical memory, define the physical memory here */
if (group_config_block) {
@ -991,7 +991,7 @@ static void build_connection_block_module(
/* Build a physical memory block */
if (group_config_block) {
add_physical_memory_module(module_manager, decoder_lib, sb_module, circuit_lib, sram_orgz_type, sram_model);
add_physical_memory_module(module_manager, decoder_lib, cb_module, circuit_lib, sram_orgz_type, sram_model);
}
/* Add global ports to the pb_module:
@ -1052,6 +1052,7 @@ static void build_flatten_connection_block_modules(
const DeviceRRGSB& device_rr_gsb, const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model, const t_rr_type& cb_type,
const bool& group_config_block,
const bool& verbose) {
/* Build unique X-direction connection block modules */
vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
@ -1069,7 +1070,7 @@ static void build_flatten_connection_block_modules(
build_connection_block_module(
module_manager, decoder_lib, device_annotation, device_ctx.grid,
device_ctx.rr_graph, circuit_lib, sram_orgz_type, sram_model, rr_gsb,
cb_type, verbose);
cb_type, group_config_block, verbose);
}
}
}

21
openfpga/src/fabric/build_top_module_memory.cpp
View File

@ -220,8 +220,9 @@ static void organize_top_module_tile_memory_modules(
vtr::Point<int> config_coord(tile_coord.x() * 2, tile_coord.y() * 2);
module_manager.add_configurable_child(
top_module, grid_module,
grid_instance_ids[tile_coord.x()][tile_coord.y()],
ModuleManager::e_config_child_type::UNIFIED,
grid_instance_ids[tile_coord.x()][tile_coord.y()], config_coord);
config_coord);
}
}
@ -429,7 +430,7 @@ void organize_top_module_memory_modules(
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const bool& compact_routing_hierarchy) {
/* Ensure clean vectors to return */
VTR_ASSERT(true == module_manager.configurable_children(top_module).empty());
VTR_ASSERT(true == module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).empty());
/* First, organize the I/O tiles on the border */
/* Special for the I/O tileas on RIGHT and BOTTOM,
@ -1334,16 +1335,16 @@ static void add_top_module_nets_cmos_memory_bank_config_bus(
* configurable children
*/
module_manager.add_configurable_child(top_module, bl_decoder_module,
curr_bl_decoder_instance_id, false);
curr_bl_decoder_instance_id, ModuleManager::e_config_child_type::PHYSICAL);
module_manager.add_configurable_child_to_region(
top_module, config_region, bl_decoder_module, curr_bl_decoder_instance_id,
module_manager.logical_configurable_children(top_module).size() - 1);
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size() - 1);
module_manager.add_configurable_child(top_module, wl_decoder_module,
curr_wl_decoder_instance_id, false);
curr_wl_decoder_instance_id, ModuleManager::e_config_child_type::PHYSICAL);
module_manager.add_configurable_child_to_region(
top_module, config_region, wl_decoder_module, curr_wl_decoder_instance_id,
module_manager.logical_configurable_children(top_module).size() - 1);
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size() - 1);
}
}
@ -1764,7 +1765,7 @@ static void add_top_module_nets_cmos_memory_frame_decoder_config_bus(
++mem_index) {
ModuleId child_module = configurable_children[mem_index];
size_t child_instance =
module_manager.logical_configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
ModulePortId child_din_port = module_manager.find_module_port(
child_module, std::string(DECODER_DATA_IN_PORT_NAME));
BasicPort child_din_port_info =
@ -1799,7 +1800,7 @@ static void add_top_module_nets_cmos_memory_frame_decoder_config_bus(
++mem_index) {
ModuleId child_module = configurable_children[mem_index];
size_t child_instance =
module_manager.logical_configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
ModulePortId child_en_port = module_manager.find_module_port(
child_module, std::string(DECODER_ENABLE_PORT_NAME));
BasicPort child_en_port_info =
@ -1819,11 +1820,11 @@ static void add_top_module_nets_cmos_memory_frame_decoder_config_bus(
/* Add the decoder as the last configurable children */
module_manager.add_configurable_child(parent_module, decoder_module,
decoder_instance, false);
decoder_instance, ModuleManager::e_config_child_type::PHYSICAL);
/* Register the configurable child to configuration region */
module_manager.add_configurable_child_to_region(
parent_module, config_region, decoder_module, decoder_instance,
module_manager.logical_configurable_children(parent_module).size() - 1);
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size() - 1);
}
/*********************************************************************

30
openfpga/src/fabric/build_top_module_memory_bank.cpp
View File

@ -58,7 +58,7 @@ static void add_module_nets_to_ql_memory_bank_shift_register_module(
const std::string& chain_head_port_name,
const std::string& chain_tail_port_name) {
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module).size();
mem_index < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size();
++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
@ -79,27 +79,27 @@ static void add_module_nets_to_ql_memory_bank_shift_register_module(
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
} else {
/* Find the port name of previous memory module */
std::string src_port_name = circuit_lib.port_prefix(model_output_port);
net_src_module_id =
module_manager.configurable_children(parent_module)[mem_index - 1];
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module)[mem_index - 1];
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index - 1];
net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
}
@ -133,9 +133,9 @@ static void add_module_nets_to_ql_memory_bank_shift_register_module(
/* Find the port name of previous memory module */
std::string src_port_name = circuit_lib.port_prefix(model_output_port);
ModuleId net_src_module_id =
module_manager.configurable_children(parent_module).back();
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).back();
size_t net_src_instance_id =
module_manager.configurable_child_instances(parent_module).back();
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL).back();
ModulePortId net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
@ -245,7 +245,7 @@ static ModuleId build_bl_shift_register_chain_module(
module_manager.num_instance(mem_module, sram_mem_module);
module_manager.add_child_module(mem_module, sram_mem_module);
module_manager.add_configurable_child(mem_module, sram_mem_module,
sram_mem_instance);
sram_mem_instance, ModuleManager::e_config_child_type::UNIFIED);
/* Build module nets to wire bl outputs of sram modules to BL outputs of
* memory module */
@ -363,7 +363,7 @@ static ModuleId build_wl_shift_register_chain_module(
module_manager.num_instance(mem_module, sram_mem_module);
module_manager.add_child_module(mem_module, sram_mem_module);
module_manager.add_configurable_child(mem_module, sram_mem_module,
sram_mem_instance);
sram_mem_instance, ModuleManager::e_config_child_type::UNIFIED);
/* Build module nets to wire wl outputs of sram modules to WL outputs of
* memory module */
@ -699,10 +699,10 @@ static void add_top_module_nets_cmos_ql_memory_bank_bl_decoder_config_bus(
* configurable children
*/
module_manager.add_configurable_child(top_module, bl_decoder_module,
curr_bl_decoder_instance_id);
curr_bl_decoder_instance_id, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child_to_region(
top_module, config_region, bl_decoder_module, curr_bl_decoder_instance_id,
module_manager.configurable_children(top_module).size() - 1);
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size() - 1);
}
}
@ -968,10 +968,10 @@ static void add_top_module_nets_cmos_ql_memory_bank_wl_decoder_config_bus(
* configurable children
*/
module_manager.add_configurable_child(top_module, wl_decoder_module,
curr_wl_decoder_instance_id);
curr_wl_decoder_instance_id, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child_to_region(
top_module, config_region, wl_decoder_module, curr_wl_decoder_instance_id,
module_manager.configurable_children(top_module).size() - 1);
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size() - 1);
}
}

10
openfpga/src/fabric/fabric_key_writer.cpp
View File

@ -32,7 +32,7 @@ static int add_module_keys_to_fabric_key(const ModuleManager& module_manager,
return CMD_EXEC_SUCCESS;
}
/* Bypass modules which does not have any configurable children */
if (module_manager.logical_configurable_children(curr_module).empty()) {
if (module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::PHYSICAL).empty()) {
return CMD_EXEC_SUCCESS;
}
/* Now create the module and add subkey one by one */
@ -41,12 +41,12 @@ static int add_module_keys_to_fabric_key(const ModuleManager& module_manager,
return CMD_EXEC_FATAL_ERROR;
}
size_t num_config_child =
module_manager.logical_configurable_children(curr_module).size();
module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::PHYSICAL).size();
for (size_t ichild = 0; ichild < num_config_child; ++ichild) {
ModuleId child_module =
module_manager.logical_configurable_children(curr_module)[ichild];
module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
size_t child_instance =
module_manager.logical_configurable_child_instances(curr_module)[ichild];
module_manager.configurable_child_instances(curr_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
FabricSubKeyId sub_key = fabric_key.create_module_key(key_module_id);
fabric_key.set_sub_key_name(sub_key,
@ -111,7 +111,7 @@ int write_fabric_key_to_xml_file(
/* Build a fabric key database by visiting all the configurable children */
FabricKey fabric_key;
size_t num_keys = module_manager.logical_configurable_children(top_module).size();
size_t num_keys = module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size();
fabric_key.reserve_keys(num_keys);

34
openfpga/src/fabric/module_manager.cpp
View File

@ -412,13 +412,13 @@ size_t ModuleManager::instance_id(const ModuleId& parent_module,
return size_t(-1);
}
size_t ModuleManager::num_configurable_children(const ModuleId& parent_module, const e_config_child_type& type) const;
size_t ModuleManager::num_configurable_children(const ModuleId& parent_module, const e_config_child_type& type) const {
VTR_ASSERT(valid_module_id(parent_module));
if (type == ModuleManager::e_config_child_type::LOGICAL) {
return logical_configurable_children_[parent_module].size();
}
VTR_ASSERT(type == ModuleManager::e_config_child_type::LOGICAL);
return physical_configurable_children_[parent_module].size()
return physical_configurable_children_[parent_module].size();
}
ModuleManager::e_module_port_type ModuleManager::port_type(
@ -716,12 +716,14 @@ ModuleId ModuleManager::add_module(const std::string& name) {
child_instance_names_.emplace_back();
logical_configurable_children_.emplace_back();
logical_configurable_child_instances_.emplace_back();
logical_configurable_child_regions_.emplace_back();
logical_configurable_child_coordinates_.emplace_back();
physical_configurable_children_.emplace_back();
physical_configurable_child_instances_.emplace_back();
physical_configurable_child_parents_.emplace_back();
physical_configurable_child_regions_.emplace_back();
physical_configurable_child_coordinates_.emplace_back();
logical2physical_configurable_children_.emplace_back();
logical2physical_configurable_child_instances_.emplace_back();
logical2physical_configurable_child_parents_.emplace_back();
config_region_ids_.emplace_back();
config_region_children_.emplace_back();
@ -1001,7 +1003,7 @@ void ModuleManager::add_configurable_child(const ModuleId& parent_module,
void ModuleManager::set_logical2physical_configurable_child(const ModuleId& parent_module, const size_t& logical_child_id, const ModuleId& physical_child_module) {
/* Sanity checks */
VTR_ASSERT(valid_module_id(parent_module));
VTR_ASSERT(logical_child_id < num_logical_configurable_children(parent_module));
VTR_ASSERT(logical_child_id < num_configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL));
/* Create the pair */
logical2physical_configurable_children_[parent_module][logical_child_id] = physical_child_module;
}
@ -1009,7 +1011,7 @@ void ModuleManager::set_logical2physical_configurable_child(const ModuleId& pare
void ModuleManager::set_logical2physical_configurable_child_instance(const ModuleId& parent_module, const size_t& logical_child_id, const size_t& physical_child_instance) {
/* Sanity checks */
VTR_ASSERT(valid_module_id(parent_module));
VTR_ASSERT(logical_child_id < num_logical_configurable_children(parent_module));
VTR_ASSERT(logical_child_id < num_configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL));
/* Create the pair */
logical2physical_configurable_child_instances_[parent_module][logical_child_id] = physical_child_instance;
}
@ -1017,7 +1019,7 @@ void ModuleManager::set_logical2physical_configurable_child_instance(const Modul
void ModuleManager::set_logical2physical_configurable_child_parent_module(const ModuleId& parent_module, const size_t& logical_child_id, const ModuleId& physical_child_parent_module) {
/* Sanity checks */
VTR_ASSERT(valid_module_id(parent_module));
VTR_ASSERT(logical_child_id < num_logical_configurable_children(parent_module));
VTR_ASSERT(logical_child_id < num_configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL));
/* Create the pair */
logical2physical_configurable_child_parents_[parent_module][logical_child_id] = physical_child_parent_module;
}
@ -1086,9 +1088,9 @@ void ModuleManager::add_configurable_child_to_region(
/* Ensure that the child module is in the configurable children list */
VTR_ASSERT(child_module ==
physical_configurable_children(parent_module)[config_child_id]);
configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[config_child_id]);
VTR_ASSERT(child_instance ==
physical_configurable_child_instances(parent_module)[config_child_id]);
configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[config_child_id]);
/* If the child is already in another region, error out */
if ((true ==
@ -1426,12 +1428,14 @@ void ModuleManager::clear_configurable_children(const ModuleId& parent_module) {
logical_configurable_children_[parent_module].clear();
logical_configurable_child_instances_[parent_module].clear();
logical_configurable_child_regions_[parent_module].clear();
logical_configurable_child_coordinates_[parent_module].clear();
physical_configurable_children_[parent_module].clear();
physical_configurable_child_instances_[parent_module].clear();
physical_configurable_child_parents_[parent_module].clear();
physical_configurable_child_regions_[parent_module].clear();
physical_configurable_child_coordinates_[parent_module].clear();
logical2physical_configurable_children_[parent_module].clear();
logical2physical_configurable_child_instances_[parent_module].clear();
logical2physical_configurable_child_parents_[parent_module].clear();
}
void ModuleManager::clear_config_region(const ModuleId& parent_module) {

2
openfpga/src/fpga_bitstream/build_device_bitstream.cpp
View File

@ -193,7 +193,7 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
/* Reserve child blocks for the top level block */
bitstream_manager.reserve_child_blocks(
top_block, count_module_manager_module_configurable_children(
openfpga_ctx.module_graph(), top_module), ModuleManager::e_config_child_type::PHYSICAL);
openfpga_ctx.module_graph(), top_module, ModuleManager::e_config_child_type::PHYSICAL));
/* Create bitstream from grids */
VTR_LOGV(verbose, "Building grid bitstream...\n");

2
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -778,7 +778,7 @@ static void build_physical_block_bitstream(
if (!module_manager.unified_configurable_children(grid_module)) {
VTR_ASSERT(1 == module_manager.configurable_children(grid_module, ModuleManager::e_config_child_type::PHYSICAL).size());
std::string phy_mem_instance_name = module_manager.instance_name(grid_module, module_manager.configurable_children(grid_module, ModuleManager::e_config_child_type::PHYSICAL)[0], module_manager.configurable_child_instances(grid_module, ModuleManager::e_config_child_type::PHYSICAL)[0]);
ConfigBlockId grid_grouped_config_block = bitstream_manager.add_child_block(phy_mem_instance_name);
ConfigBlockId grid_grouped_config_block = bitstream_manager.add_block(phy_mem_instance_name);
bitstream_manager.add_child_block(grid_configurable_block, grid_grouped_config_block);
grid_configurable_block = grid_grouped_config_block;
}

4
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -534,7 +534,7 @@ static void build_connection_block_bitstreams(
if (!module_manager.unified_configurable_children(cb_module)) {
VTR_ASSERT(1 == module_manager.configurable_children(cb_module, ModuleManager::e_config_child_type::PHYSICAL).size());
std::string phy_mem_instance_name = module_manager.instance_name(cb_module, module_manager.configurable_children(cb_module, ModuleManager::e_config_child_type::PHYSICAL)[0], module_manager.configurable_child_instances(cb_module, ModuleManager::e_config_child_type::PHYSICAL)[0]);
ConfigBlockId cb_grouped_config_block = bitstream_manager.add_child_block(phy_mem_instance_name);
ConfigBlockId cb_grouped_config_block = bitstream_manager.add_block(phy_mem_instance_name);
bitstream_manager.add_child_block(cb_configurable_block, cb_grouped_config_block);
cb_configurable_block = cb_grouped_config_block;
}
@ -645,7 +645,7 @@ void build_routing_bitstream(
if (!module_manager.unified_configurable_children(sb_module)) {
VTR_ASSERT(1 == module_manager.configurable_children(sb_module, ModuleManager::e_config_child_type::PHYSICAL).size());
std::string phy_mem_instance_name = module_manager.instance_name(sb_module, module_manager.configurable_children(sb_module, ModuleManager::e_config_child_type::PHYSICAL)[0], module_manager.configurable_child_instances(sb_module, ModuleManager::e_config_child_type::PHYSICAL)[0]);
ConfigBlockId sb_grouped_config_block = bitstream_manager.add_child_block(phy_mem_instance_name);
ConfigBlockId sb_grouped_config_block = bitstream_manager.add_block(phy_mem_instance_name);
bitstream_manager.add_child_block(sb_configurable_block, sb_grouped_config_block);
sb_configurable_block = sb_grouped_config_block;
}

8
openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
View File

@ -49,13 +49,13 @@ static void rec_print_pnr_sdc_constrain_configurable_chain(
ModuleId& previous_module) {
/* For each configurable child, we will go one level down in priority */
for (size_t child_index = 0;
child_index < module_manager.configurable_children(parent_module).size();
child_index < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size();
++child_index) {
std::string child_module_path = parent_module_path;
ModuleId child_module_id =
module_manager.configurable_children(parent_module)[child_index];
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_index];
size_t child_instance_id =
module_manager.configurable_child_instances(parent_module)[child_index];
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_index];
std::string child_instance_name;
if (true ==
module_manager
@ -79,7 +79,7 @@ static void rec_print_pnr_sdc_constrain_configurable_chain(
/* If there is no configurable children any more, this is a leaf module, print
* a SDC command for disable timing */
if (0 < module_manager.configurable_children(parent_module).size()) {
if (0 < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size()) {
return;
}

8
openfpga/src/fpga_sdc/sdc_memory_utils.cpp
View File

@ -45,13 +45,13 @@ void rec_print_pnr_sdc_disable_configurable_memory_module_output(
/* For each configurable child, we will go one level down in priority */
for (size_t child_index = 0;
child_index < module_manager.configurable_children(parent_module).size();
child_index < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size();
++child_index) {
std::string child_module_path = parent_module_path;
ModuleId child_module_id =
module_manager.configurable_children(parent_module)[child_index];
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_index];
size_t child_instance_id =
module_manager.configurable_child_instances(parent_module)[child_index];
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_index];
std::string child_instance_name;
if (true ==
module_manager
@ -96,7 +96,7 @@ void rec_print_pnr_sdc_disable_configurable_memory_module_output(
/* If there is no configurable children any more, this is a leaf module, print
* a SDC command for disable timing */
if (0 < module_manager.configurable_children(parent_module).size()) {
if (0 < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size()) {
return;
}

9
openfpga/src/utils/memory_utils.cpp
View File

@ -2,9 +2,8 @@
* This file includes functions that are used for
* generating ports for memory modules
*********************************************************************/
/* Headers from vtrutil library */
#include "memory_utils.h"
#include "command_exit_codes.h"
#include "decoder_library_utils.h"
#include "openfpga_naming.h"
#include "vtr_assert.h"
@ -520,16 +519,16 @@ int rec_update_logical_memory_children_with_physical_mapping(ModuleManager& modu
ModuleId logical_child = module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL)[ichild];
if (module_manager.configurable_children(logical_child, ModuleManager::e_config_child_type::LOGICAL).empty()) {
/* This is a leaf node, update its physical information */
ModuleId phy_mem_submodule = module_manager.logical2physical_configurable_children(curr_module)[ichild]
ModuleId phy_mem_submodule = module_manager.logical2physical_configurable_children(curr_module)[ichild];
auto result = logical_mem_child_inst_count.find(phy_mem_submodule);
if (result == logical_mem_child_inst_count.end()) {
logical_mem_child_inst_count.find[phy_mem_submodule] = 0;
logical_mem_child_inst_count[phy_mem_submodule] = 0;
}
module_manager.set_logical2physical_configurable_child_instance(curr_module, ichild, logical_mem_child_inst_count[phy_mem_submodule]);
module_manager.set_logical2physical_configurable_child_parent_module(curr_module, ichild, phy_mem_module);
logical_mem_child_inst_count[phy_mem_submodule]++;
} else {
rec_find_physical_memory_children(module_manager, logical_child, physical_memory_children, logical_mem_child_inst_count);
rec_update_logical_memory_children_with_physical_mapping(module_manager, logical_child, phy_mem_module, logical_mem_child_inst_count);
}
}
return CMD_EXEC_SUCCESS;

2
openfpga/src/utils/module_manager_memory_utils.cpp
View File

@ -83,7 +83,7 @@ static bool update_submodule_memory_modules_from_fabric_key(
const ModuleManager::e_config_child_type& config_child_type,
const FabricKey& fabric_key, const FabricKeyModuleId& key_module_id) {
/* Reset the configurable children */
module_manager.clear_configurable_children(module_id, config_child_type);
module_manager.clear_configurable_children(module_id);
for (FabricSubKeyId key_id : fabric_key.sub_keys(key_module_id)) {
std::pair<ModuleId, size_t> inst_info(ModuleId::INVALID(), 0);

18
openfpga/src/utils/module_manager_utils.cpp
View File

@ -1107,7 +1107,8 @@ void add_module_nets_cmos_flatten_memory_config_bus(
void add_module_nets_cmos_memory_bank_bl_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_port_type& config_port_type) {
const e_circuit_model_port_type& config_port_type,
const ModuleManager::e_config_child_type& config_child_type) {
/* A counter for the current pin id for the source port of parent module */
size_t cur_src_pin_id = 0;
@ -1124,15 +1125,15 @@ void add_module_nets_cmos_memory_bank_bl_config_bus(
module_manager.module_port(net_src_module_id, net_src_port_id);
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module).size();
mem_index < module_manager.configurable_children(parent_module, config_child_type).size();
++mem_index) {
/* Find the port name of next memory module */
std::string sink_port_name =
generate_sram_port_name(sram_orgz_type, config_port_type);
ModuleId net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
size_t net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
ModulePortId net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
@ -1190,7 +1191,8 @@ void add_module_nets_cmos_memory_bank_bl_config_bus(
void add_module_nets_cmos_memory_bank_wl_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_port_type& config_port_type) {
const e_circuit_model_port_type& config_port_type,
const ModuleManager::e_config_child_type& config_child_type) {
/* A counter for the current pin id for the source port of parent module */
size_t cur_src_pin_id = 0;
@ -1219,15 +1221,15 @@ void add_module_nets_cmos_memory_bank_wl_config_bus(
module_manager.module_port(net_src_module_id, net_bl_port_id);
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module).size();
mem_index < module_manager.configurable_children(parent_module, config_child_type).size();
++mem_index) {
/* Find the port name of next memory module */
std::string sink_port_name =
generate_sram_port_name(sram_orgz_type, config_port_type);
ModuleId net_sink_module_id =
module_manager.configurable_children(parent_module)[mem_index];
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
size_t net_sink_instance_id =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
ModulePortId net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);

12
openfpga/src/utils/module_manager_utils.h
View File

@ -116,12 +116,14 @@ void add_module_nets_cmos_flatten_memory_config_bus(
void add_module_nets_cmos_memory_bank_bl_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_port_type& config_port_type);
const e_circuit_model_port_type& config_port_type,
const ModuleManager::e_config_child_type& config_child_type);
void add_module_nets_cmos_memory_bank_wl_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_port_type& config_port_type);
const e_circuit_model_port_type& config_port_type,
const ModuleManager::e_config_child_type& config_child_type);
void add_module_nets_cmos_memory_chain_config_bus(
ModuleManager& module_manager, const ModuleId& parent_module,
@ -151,8 +153,7 @@ size_t find_module_num_shared_config_bits(const ModuleManager& module_manager,
size_t find_module_num_config_bits(
const ModuleManager& module_manager, const ModuleId& module_id,
const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type);
const e_config_protocol_type& sram_orgz_type);
void add_module_global_input_ports_from_child_modules(
ModuleManager& module_manager, const ModuleId& module_id,
@ -176,7 +177,8 @@ size_t find_module_num_shared_config_bits_from_child_modules(
size_t find_module_num_config_bits_from_child_modules(
ModuleManager& module_manager, const ModuleId& module_id,
const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type);
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type);
ModuleNetId create_module_source_pin_net(ModuleManager& module_manager,
const ModuleId& cur_module_id,