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[core] developing top-level nets for tiles

This commit is contained in:
tangxifan 2023-07-21 23:21:53 -07:00
parent fcf308fcd6
commit 93c5a68592
5 changed files with 329 additions and 52 deletions
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226
openfpga/src/annotation/fabric_tile.cpp
View File

@ -78,6 +78,84 @@ FabricTileId FabricTile::find_tile(const vtr::Point<size_t>& coord) const {
return tile_coord2id_lookup_[coord.x()][coord.y()];
}
FabricTileId FabricTile::find_tile_by_pb_coordinate(const vtr::Point<size_t>& coord) const {
if (coord.x() >= pb_coord2id_lookup_.size()) {
VTR_LOG_ERROR(
"Programmable block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n",
coord.x(), coord.y(), pb_coord2id_lookup_.size(),
pb_coord2id_lookup_[0].size());
return FabricTileId::INVALID();
}
if (coord.y() >= pb_coord2id_lookup_[coord.x()].size()) {
VTR_LOG_ERROR(
"Programmable block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n",
coord.x(), coord.y(), pb_coord2id_lookup_.size(),
pb_coord2id_lookup_[0].size());
return FabricTileId::INVALID();
}
return pb_coord2id_lookup_[coord.x()][coord.y()];
}
FabricTileId FabricTile::find_tile_by_cb_coordinate(const t_rr_type& cb_type, const vtr::Point<size_t>& coord) const {
switch (cb_type) {
case CHANX: {
if (coord.x() >= cbx_coord2id_lookup_.size()) {
VTR_LOG_ERROR(
"X-direction connection block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n",
coord.x(), coord.y(), cbx_coord2id_lookup_.size(),
cbx_coord2id_lookup_[0].size());
return FabricTileId::INVALID();
}
if (coord.y() >= cbx_coord2id_lookup_[coord.x()].size()) {
VTR_LOG_ERROR(
"X-direction connection block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n",
coord.x(), coord.y(), cbx_coord2id_lookup_.size(),
cbx_coord2id_lookup_[0].size());
return FabricTileId::INVALID();
}
return cbx_coord2id_lookup_[coord.x()][coord.y()];
}
case CHANY: {
if (coord.x() >= cby_coord2id_lookup_.size()) {
VTR_LOG_ERROR(
"Y-direction connection block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n",
coord.x(), coord.y(), cby_coord2id_lookup_.size(),
cby_coord2id_lookup_[0].size());
return FabricTileId::INVALID();
}
if (coord.y() >= cby_coord2id_lookup_[coord.x()].size()) {
VTR_LOG_ERROR(
"Y-direction connection block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n",
coord.x(), coord.y(), cby_coord2id_lookup_.size(),
cby_coord2id_lookup_[0].size());
return FabricTileId::INVALID();
}
return cby_coord2id_lookup_[coord.x()][coord.y()];
}
default:
VTR_LOG("Invalid type of connection block!\n");
exit(1);
}
}
FabricTileId FabricTile::find_tile_by_sb_coordinate(const vtr::Point<size_t>& coord) const {
if (coord.x() >= sb_coord2id_lookup_.size()) {
VTR_LOG_ERROR(
"Switch block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n",
coord.x(), coord.y(), sb_coord2id_lookup_.size(),
sb_coord2id_lookup_[0].size());
return FabricTileId::INVALID();
}
if (coord.y() >= sb_coord2id_lookup_[coord.x()].size()) {
VTR_LOG_ERROR(
"Switch block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n",
coord.x(), coord.y(), sb_coord2id_lookup_.size(),
sb_coord2id_lookup_[0].size());
return FabricTileId::INVALID();
}
return sb_coord2id_lookup_[coord.x()][coord.y()];
}
bool FabricTile::pb_in_tile(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord,
const bool& use_gsb_coord) const {
@ -204,8 +282,16 @@ FabricTileId FabricTile::create_tile(const vtr::Point<size_t>& coord) {
void FabricTile::init(const vtr::Point<size_t>& max_coord) {
tile_coord2id_lookup_.resize(max_coord.x());
pb_coord2id_lookup_.resize(max_coord.x());
cbx_coord2id_lookup_.resize(max_coord.x());
cby_coord2id_lookup_.resize(max_coord.x());
sb_coord2id_lookup_.resize(max_coord.x());
for (size_t ix = 0; ix < max_coord.x(); ++ix) {
tile_coord2id_lookup_[ix].resize(max_coord.y(), FabricTileId::INVALID());
pb_coord2id_lookup_[ix].resize(max_coord.y(), FabricTileId::INVALID());
cbx_coord2id_lookup_[ix].resize(max_coord.y(), FabricTileId::INVALID());
cby_coord2id_lookup_[ix].resize(max_coord.y(), FabricTileId::INVALID());
sb_coord2id_lookup_[ix].resize(max_coord.y(), FabricTileId::INVALID());
}
tile_coord2unique_tile_ids_.resize(max_coord.x());
for (size_t ix = 0; ix < max_coord.x(); ++ix) {
@ -240,10 +326,130 @@ bool FabricTile::register_tile_in_lookup(const FabricTileId& tile_id,
return true;
}
bool FabricTile::register_pb_in_lookup(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord) {
if (coord.x() >= pb_coord2id_lookup_.size()) {
VTR_LOG_ERROR(
"Fast look-up has not been re-allocated properly! Given x='%lu' exceeds "
"the upper-bound '%lu'!\n",
coord.x(), pb_coord2id_lookup_.size());
return false;
}
if (coord.y() >= pb_coord2id_lookup_[coord.x()].size()) {
VTR_LOG_ERROR(
"Fast look-up has not been re-allocated properly! Given y='%lu' exceeds "
"the upper-bound '%lu'!\n",
coord.y(), pb_coord2id_lookup_[coord.x()].size());
return false;
}
/* Throw error if this coord is already registered! */
if (pb_coord2id_lookup_[coord.x()][coord.y()]) {
VTR_LOG_ERROR("Programmable block at [%lu][%lu] has already been registered!\n");
return false;
}
pb_coord2id_lookup_[coord.x()][coord.y()] = tile_id;
return true;
}
bool FabricTile::register_cbx_in_lookup(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord) {
if (coord.x() >= cbx_coord2id_lookup_.size()) {
VTR_LOG_ERROR(
"Fast look-up has not been re-allocated properly! Given x='%lu' exceeds "
"the upper-bound '%lu'!\n",
coord.x(), cbx_coord2id_lookup_.size());
return false;
}
if (coord.y() >= cbx_coord2id_lookup_[coord.x()].size()) {
VTR_LOG_ERROR(
"Fast look-up has not been re-allocated properly! Given y='%lu' exceeds "
"the upper-bound '%lu'!\n",
coord.y(), cbx_coord2id_lookup_[coord.x()].size());
return false;
}
/* Throw error if this coord is already registered! */
if (cbx_coord2id_lookup_[coord.x()][coord.y()]) {
VTR_LOG_ERROR("X-direction connection block at [%lu][%lu] has already been registered!\n");
return false;
}
cbx_coord2id_lookup_[coord.x()][coord.y()] = tile_id;
return true;
}
bool FabricTile::register_cby_in_lookup(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord) {
if (coord.x() >= cby_coord2id_lookup_.size()) {
VTR_LOG_ERROR(
"Fast look-up has not been re-allocated properly! Given x='%lu' exceeds "
"the upper-bound '%lu'!\n",
coord.x(), cby_coord2id_lookup_.size());
return false;
}
if (coord.y() >= cby_coord2id_lookup_[coord.x()].size()) {
VTR_LOG_ERROR(
"Fast look-up has not been re-allocated properly! Given y='%lu' exceeds "
"the upper-bound '%lu'!\n",
coord.y(), cby_coord2id_lookup_[coord.x()].size());
return false;
}
/* Throw error if this coord is already registered! */
if (cby_coord2id_lookup_[coord.x()][coord.y()]) {
VTR_LOG_ERROR("Y-direction connection block at [%lu][%lu] has already been registered!\n");
return false;
}
cby_coord2id_lookup_[coord.x()][coord.y()] = tile_id;
return true;
}
bool FabricTile::register_sb_in_lookup(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord) {
if (coord.x() >= sb_coord2id_lookup_.size()) {
VTR_LOG_ERROR(
"Fast look-up has not been re-allocated properly! Given x='%lu' exceeds "
"the upper-bound '%lu'!\n",
coord.x(), sb_coord2id_lookup_.size());
return false;
}
if (coord.y() >= sb_coord2id_lookup_[coord.x()].size()) {
VTR_LOG_ERROR(
"Fast look-up has not been re-allocated properly! Given y='%lu' exceeds "
"the upper-bound '%lu'!\n",
coord.y(), sb_coord2id_lookup_[coord.x()].size());
return false;
}
/* Throw error if this coord is already registered! */
if (sb_coord2id_lookup_[coord.x()][coord.y()]) {
VTR_LOG_ERROR("Switch block at [%lu][%lu] has already been registered!\n");
return false;
}
sb_coord2id_lookup_[coord.x()][coord.y()] = tile_id;
return true;
}
void FabricTile::invalidate_tile_in_lookup(const vtr::Point<size_t>& coord) {
tile_coord2id_lookup_[coord.x()][coord.y()] = FabricTileId::INVALID();
}
void FabricTile::invalidate_pb_in_lookup(const vtr::Point<size_t>& coord) {
pb_coord2id_lookup_[coord.x()][coord.y()] = FabricTileId::INVALID();
}
void FabricTile::invalidate_cbx_in_lookup(const vtr::Point<size_t>& coord) {
cbx_coord2id_lookup_[coord.x()][coord.y()] = FabricTileId::INVALID();
}
void FabricTile::invalidate_cby_in_lookup(const vtr::Point<size_t>& coord) {
cby_coord2id_lookup_[coord.x()][coord.y()] = FabricTileId::INVALID();
}
void FabricTile::invalidate_sb_in_lookup(const vtr::Point<size_t>& coord) {
sb_coord2id_lookup_[coord.x()][coord.y()] = FabricTileId::INVALID();
}
bool FabricTile::set_tile_coordinate(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord) {
VTR_ASSERT(valid_tile_id(tile_id));
@ -255,35 +461,41 @@ bool FabricTile::set_tile_coordinate(const FabricTileId& tile_id,
return register_tile_in_lookup(tile_id, coord);
}
void FabricTile::add_pb_coordinate(const FabricTileId& tile_id,
int FabricTile::add_pb_coordinate(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord,
const vtr::Point<size_t>& gsb_coord) {
VTR_ASSERT(valid_tile_id(tile_id));
pb_coords_[tile_id].push_back(coord);
pb_gsb_coords_[tile_id].push_back(gsb_coord);
/* Register in fast look-up */
return register_pb_in_lookup(tile_id, coord);
}
void FabricTile::add_cb_coordinate(const FabricTileId& tile_id,
int FabricTile::add_cb_coordinate(const FabricTileId& tile_id,
const t_rr_type& cb_type,
const vtr::Point<size_t>& coord) {
VTR_ASSERT(valid_tile_id(tile_id));
switch (cb_type) {
case CHANX:
cbx_coords_[tile_id].push_back(coord);
break;
/* Register in fast look-up */
return register_cbx_in_lookup(tile_id, coord);
case CHANY:
cby_coords_[tile_id].push_back(coord);
break;
/* Register in fast look-up */
return register_cby_in_lookup(tile_id, coord);
default:
VTR_LOG("Invalid type of connection block!\n");
exit(1);
}
}
void FabricTile::add_sb_coordinate(const FabricTileId& tile_id,
int FabricTile::add_sb_coordinate(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord) {
VTR_ASSERT(valid_tile_id(tile_id));
sb_coords_[tile_id].push_back(coord);
/* Register in fast look-up */
return register_sb_in_lookup(tile_id, coord);
}
void FabricTile::clear() {
@ -295,6 +507,10 @@ void FabricTile::clear() {
cby_coords_.clear();
sb_coords_.clear();
tile_coord2id_lookup_.clear();
pb_coord2id_lookup_.clear();
cbx_coord2id_lookup_.clear();
cby_coord2id_lookup_.clear();
sb_coord2id_lookup_.clear();
tile_coord2unique_tile_ids_.clear();
unique_tile_ids_.clear();
}

29
openfpga/src/annotation/fabric_tile.h
View File

@ -36,6 +36,12 @@ class FabricTile {
FabricTileId unique_tile(const vtr::Point<size_t>& coord) const;
/** @brief Find the tile info with a given coordinate */
FabricTileId find_tile(const vtr::Point<size_t>& coord) const;
/** @brief Find the id of a tile, with a given coordinate of the programmable block under the tile */
FabricTileId find_tile_by_pb_coordinate(const vtr::Point<size_t>& coord) const;
/** @brief Find the id of a tile, with a given coordinate of the connection block under the tile */
FabricTileId find_tile_by_cb_coordinate(const t_rr_type& cb_type, const vtr::Point<size_t>& coord) const;
/** @brief Find the id of a tile, with a given coordinate of the switch block under the tile */
FabricTileId find_tile_by_sb_coordinate(const vtr::Point<size_t>& coord) const;
/** @brief Find the coordinate of the unique tile w.r.t the tile with a tile
* id */
vtr::Point<size_t> unique_tile_coordinate(const FabricTileId& tile_id) const;
@ -75,12 +81,12 @@ class FabricTile {
FabricTileId create_tile(const vtr::Point<size_t>& coord);
bool set_tile_coordinate(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord);
void add_pb_coordinate(const FabricTileId& tile_id,
int add_pb_coordinate(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord,
const vtr::Point<size_t>& gsb_coord);
void add_cb_coordinate(const FabricTileId& tile_id, const t_rr_type& cb_type,
int add_cb_coordinate(const FabricTileId& tile_id, const t_rr_type& cb_type,
const vtr::Point<size_t>& coord);
void add_sb_coordinate(const FabricTileId& tile_id,
int add_sb_coordinate(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord);
/** @brief Build a list of unique tiles by comparing the coordinates in
* DeviceRRGSB */
@ -105,8 +111,20 @@ class FabricTile {
private: /* Internal builders */
void invalidate_tile_in_lookup(const vtr::Point<size_t>& coord);
void invalidate_pb_in_lookup(const vtr::Point<size_t>& coord);
void invalidate_cbx_in_lookup(const vtr::Point<size_t>& coord);
void invalidate_cby_in_lookup(const vtr::Point<size_t>& coord);
void invalidate_sb_in_lookup(const vtr::Point<size_t>& coord);
bool register_tile_in_lookup(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord);
bool register_pb_in_lookup(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord);
bool register_cbx_in_lookup(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord);
bool register_cby_in_lookup(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord);
bool register_sb_in_lookup(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord);
private: /* Internal Data */
vtr::vector<FabricTileId, FabricTileId> ids_;
@ -124,6 +142,11 @@ class FabricTile {
vtr::vector<FabricTileId, std::vector<vtr::Point<size_t>>> cbx_coords_;
vtr::vector<FabricTileId, std::vector<vtr::Point<size_t>>> cby_coords_;
vtr::vector<FabricTileId, std::vector<vtr::Point<size_t>>> sb_coords_;
/* A few fast lookup to spot tile by coordinate of programmable blocks, connection blocks and switch blocks */
std::vector<std::vector<FabricTileId>> pb_coord2id_lookup_;
std::vector<std::vector<FabricTileId>> cbx_coord2id_lookup_;
std::vector<std::vector<FabricTileId>> cby_coord2id_lookup_;
std::vector<std::vector<FabricTileId>> sb_coord2id_lookup_;
/* A fast lookup to spot tile by coordinate */
std::vector<std::vector<FabricTileId>> tile_coord2id_lookup_;
std::vector<std::vector<FabricTileId>>

9
openfpga/src/base/openfpga_naming.cpp
View File

@ -498,13 +498,20 @@ std::string generate_switch_block_module_name(
}
/*********************************************************************
* Generate the module name for a switch block with a given index
* Generate the module name for a tile module with a given coordinate
*********************************************************************/
std::string generate_tile_module_name(const vtr::Point<size_t>& tile_coord) {
return std::string("tile_" + std::to_string(tile_coord.x()) + "__" +
std::to_string(tile_coord.y()) + "_");
}
/*********************************************************************
* Generate the port name for a tile. Note that use the index to make the tile port name unique!
*********************************************************************/
std::string generate_tile_module_port_name(const std::string& prefix, const std::string& port_name) {
return prefix + port_name;
}
/*********************************************************************
* Generate the netlist name of a grid block
**********************************************************************/

2
openfpga/src/base/openfpga_naming.h
View File

@ -112,6 +112,8 @@ std::string generate_connection_block_module_name(
std::string generate_tile_module_name(const vtr::Point<size_t>& tile_coord);
std::string generate_tile_module_port_name(const vtr::Point<size_t>& tile_coord, const std::string& port_name);
std::string generate_tile_module_netlist_name(const std::string& block_name,
const std::string& postfix);

115
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -278,17 +278,22 @@ static void add_top_module_tile_io_children(
*******************************************************************/
static int build_top_module_tile_nets_between_sb_and_pb(
ModuleManager& module_manager, const ModuleId& top_module,
const ModuleId& tile_module, const size_t& tile_instance_id,
const ModuleId& curr_tile_module,
const vtr::Matrix<size_t>& tile_instance_ids,
const size_t& curr_tile_instance_id,
const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation,
const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph,
const RRGSB& rr_gsb, const FabricTile& fabric_tile,
const FabricTileId& fabric_tile_id,
const bool& frame_view, const bool& verbose) {
const bool& compact_routing_hierarchy,
const bool& verbose) {
/* Skip those Switch blocks that do not exist */
if (false == rr_gsb.is_sb_exist()) {
return CMD_EXEC_SUCCESS;
}
vtr::Point<size_t> sink_tile_coord = fabric_tile.tile_coordinate(curr_fabric_tile_id);
/* We could have two different coordinators, one is the instance, the other is
* the module */
vtr::Point<size_t> instance_sb_coordinate(rr_gsb.get_sb_x(),
@ -312,9 +317,6 @@ static int build_top_module_tile_nets_between_sb_and_pb(
/* Collect sink-related information */
std::string sink_sb_module_name =
generate_switch_block_module_name(module_sb_coordinate);
ModuleId sink_sb_module = module_manager.find_module(sink_sb_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(sink_sb_module));
size_t sink_sb_instance = sb_instance;
/* Connect grid output pins (OPIN) to switch block grid pins */
for (size_t side = 0; side < module_sb.get_num_sides(); ++side) {
@ -323,19 +325,28 @@ static int build_top_module_tile_nets_between_sb_and_pb(
inode < module_sb.get_num_opin_nodes(side_manager.get_side());
++inode) {
/* Collect source-related information */
/* Generate the grid module name by considering if it locates on the
* border */
vtr::Point<size_t> grid_coordinate(
rr_graph.node_xlow(
rr_gsb.get_opin_node(side_manager.get_side(), inode)),
rr_graph.node_ylow(
rr_gsb.get_opin_node(side_manager.get_side(), inode)));
std::string src_grid_module_name =
generate_grid_block_module_name_in_top_module(
std::string(GRID_MODULE_NAME_PREFIX), grids, grid_coordinate);
ModuleId src_grid_module =
module_manager.find_module(src_grid_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module));
/* Check if the grid is inside the tile, if not, create ports */
if (fabric_tile.pb_in_tile(fabric_tile_id, grid_coordinate)) {
continue;
}
/* Find the source tile id, coordinate etc., which is required to find source tile module and port */
FabricTileId src_fabric_tile_id = fabric_tile.find_tile_by_pb_coordinate(grid_coordinate);
size_t pb_idx_in_src_fabric_tile = fabric_tile.find_pb_index_in_tile(src_fabric_tile_id, grid_coordinate);
vtr::Point<size_t> src_tile_coord = fabric_tile.tile_coordinate(src_fabric_tile_id);
vtr::Point<size_t> src_unique_tile_coord = fabric_tile.unique_tile_coordinate(src_fabric_tile_id);
FabricTileId src_unique_tile = fabric_tile.unique_tile(src_tile_coord);
vtr::Point<size_t> src_pb_coord_in_unique_tile = fabric_tile.pb_coordinates(src_unique_tile)[pb_idx_in_src_fabric_tile];
std::string src_tile_module_name =
generate_tile_module_name(src_unique_tile_coord);
ModuleId src_tile_module =
module_manager.find_module(src_tile_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(src_tile_module));
size_t src_grid_pin_index = rr_graph.node_pin_num(
rr_gsb.get_opin_node(side_manager.get_side(), inode));
@ -358,12 +369,14 @@ static int build_top_module_tile_nets_between_sb_and_pb(
get_rr_graph_single_node_side(
rr_graph, rr_gsb.get_opin_node(side_manager.get_side(), inode)),
src_grid_pin_info);
ModulePortId src_grid_port_id =
module_manager.find_module_port(src_grid_module, src_grid_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module,
src_grid_port_id));
BasicPort src_grid_port =
module_manager.module_port(src_grid_module, src_grid_port_id);
std::string src_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(GRID_MODULE_NAME_PREFIX), grids, src_pb_coord_in_unique_tile);
std::string src_tile_grid_port_name = generate_tile_module_port_name(src_grid_module_name, src_grid_port_name);
ModulePortId src_tile_grid_port_id =
module_manager.find_module_port(src_tile_module, src_tile_grid_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(src_tile_module,
src_tile_grid_port_id));
BasicPort src_tile_grid_port =
module_manager.module_port(src_tile_module, src_tile_grid_port_id);
/* Collect sink-related information */
vtr::Point<size_t> sink_sb_port_coord(
@ -377,19 +390,37 @@ static int build_top_module_tile_nets_between_sb_and_pb(
rr_graph, module_sb.get_opin_node(side_manager.get_side(), inode)),
grids, vpr_device_annotation, rr_graph,
module_sb.get_opin_node(side_manager.get_side(), inode));
ModulePortId sink_sb_port_id =
module_manager.find_module_port(sink_sb_module, sink_sb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module,
sink_sb_port_id));
BasicPort sink_sb_port =
module_manager.module_port(sink_sb_module, sink_sb_port_id);
std::string sink_tile_sb_port_name = generate_tile_module_port_name(sink_sb_module_name, sink_sb_port_name);
ModulePortId sink_tile_sb_port_id =
module_manager.find_module_port(tile_module, sink_tile_sb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(tile_module,
sink_tile_sb_port_id));
BasicPort sink_tile_sb_port =
module_manager.module_port(tile_module, sink_tile_sb_port_id);
/* Check if the grid is inside the tile, if not, create ports */
if (fabric_tile.pb_in_tile(fabric_tile_id, grid_coordinate)) {
continue;
}
/* TODO: Create nets */
if (!frame_view) {
/* Create nets */
VTR_LOGV(verbose,
"Build inter-tile nets between switch block '%s' in tile[%lu][%lu] and "
"programmable block in tile[%lu][%lu]\n",
sink_sb_module_name.c_str(),
sink_tile_coord.x(), sink_tile_coord.y(),
src_tile_coord.x(), src_tile_coord.y());
size_t src_tile_instance =
tile_instance_ids[src_tile_coord.x(), src_tile_coord.y()];
/* Source and sink port should match in size */
VTR_ASSERT(src_tile_grid_port.get_width() == sink_tile_sb_port.get_width());
/* Create a net for each pin */
for (size_t pin_id = 0; pin_id < src_tile_grid_port.pins().size();
++pin_id) {
ModuleNetId net = create_module_source_pin_net(
module_manager, top_module, src_tile_module, src_tile_instance,
src_tile_grid_port_id, src_tile_grid_port.pins()[pin_id]);
/* Configure the net sink */
module_manager.add_module_net_sink(
top_module, net, curr_tile_module, curr_tile_instance_id,
sink_tile_sb_port_id, sink_tile_sb_port.pins()[pin_id]);
}
}
}
@ -460,7 +491,7 @@ static int build_top_module_tile_nets_between_cb_and_pb(
const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph,
const RRGSB& rr_gsb, const FabricTile& fabric_tile,
const FabricTileId& fabric_tile_id, const t_rr_type& cb_type,
const bool& frame_view,
const bool& compact_routing_hierarchy,
const bool& verbose) {
/* We could have two different coordinators, one is the instance, the other is
* the module */
@ -568,8 +599,6 @@ static int build_top_module_tile_nets_between_cb_and_pb(
continue;
}
/* TODO: Create nets */
if (!frame_view) {
}
}
}
return CMD_EXEC_SUCCESS;
@ -622,7 +651,8 @@ static int build_top_module_tile_nets_between_sb_and_cb(
const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph,
const RRGSB& rr_gsb, const FabricTile& fabric_tile,
const FabricTileId& fabric_tile_id,
const bool& frame_view, const bool& verbose) {
const bool& compact_routing_hierarchy,
const bool& verbose) {
/* We could have two different coordinators, one is the instance, the other is
* the module */
vtr::Point<size_t> instance_sb_coordinate(rr_gsb.get_sb_x(),
@ -721,8 +751,6 @@ static int build_top_module_tile_nets_between_sb_and_cb(
continue;
}
/* TODO: Create nets */
if (!frame_view) {
}
}
return CMD_EXEC_SUCCESS;
}
@ -735,7 +763,8 @@ static int build_top_module_tile_nets_between_pbs(
const ModuleId& tile_module, const size_t& tile_instance_id,
const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation,
const vtr::Point<size_t>& pb_coord, const size_t& pb_instance,
const bool& frame_view, const bool& verbose) {
const bool& compact_routing_hierarchy,
const bool& verbose) {
t_physical_tile_type_ptr phy_tile =
grids.get_physical_type(pb_coord.x(), pb_coord.y());
/* Empty type does not require a module */
@ -877,8 +906,8 @@ static int add_top_module_nets_around_one_tile(
fabric_tile.sb_coordinates(fabric_tile_id)[isb];
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(sb_coord);
status_code = build_top_module_tile_nets_between_sb_and_pb(
module_manager, top_module, tile_module, tile_instance_id, grids, vpr_device_annotation, device_rr_gsb,
rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id, verbose);
module_manager, top_module, tile_module, tile_instance_ids, tile_instance_id, grids, vpr_device_annotation, device_rr_gsb,
rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id, true, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -895,7 +924,7 @@ static int add_top_module_nets_around_one_tile(
status_code = build_top_module_tile_nets_between_cb_and_pb(
module_manager, tile_module, grids, vpr_device_annotation,
device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id,
cb_type, pb_instances, cb_instances.at(cb_type)[icb], true, frame_view,
cb_type, pb_instances, cb_instances.at(cb_type)[icb], true,
verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
@ -912,7 +941,7 @@ static int add_top_module_nets_around_one_tile(
status_code = build_top_module_tile_nets_between_sb_and_cb(
module_manager, tile_module, device_rr_gsb, rr_graph_view, rr_gsb,
fabric_tile, fabric_tile_id, cb_instances, sb_instances[isb], true,
frame_view, verbose);
verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -925,7 +954,7 @@ static int add_top_module_nets_around_one_tile(
fabric_tile.pb_coordinates(fabric_tile_id)[ipb];
status_code = build_top_module_tile_nets_between_pbs(
module_manager, tile_module, grids, vpr_device_annotation, pb_coord,
pb_instances[ipb], frame_view, verbose);
pb_instances[ipb], verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}