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[core] fixed bugs in bitgen

This commit is contained in:
tangxifan 2023-09-16 18:34:55 -07:00
parent 058bb1ef51
commit 200ecad74a
3 changed files with 9 additions and 7 deletions
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1
openfpga/src/fpga_bitstream/build_device_bitstream.cpp
View File

@ -220,6 +220,7 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
VTR_LOGV(verbose, "Building routing bitstream...\n");
build_routing_bitstream(
bitstream_manager, top_block, openfpga_ctx.module_graph(),
openfpga_ctx.module_name_map(),
openfpga_ctx.fabric_tile(), openfpga_ctx.arch().circuit_lib,
openfpga_ctx.mux_lib(), vpr_ctx.atom(),
openfpga_ctx.vpr_device_annotation(), openfpga_ctx.vpr_routing_annotation(),

12
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -452,7 +452,7 @@ static void build_connection_block_bitstream(
static void build_connection_block_bitstreams(
BitstreamManager& bitstream_manager,
const ConfigBlockId& top_configurable_block,
const ModuleManager& module_manager, const FabricTile& fabric_tile,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map, const FabricTile& fabric_tile,
const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
@ -501,7 +501,7 @@ static void build_connection_block_bitstreams(
cb_module_name =
generate_connection_block_module_name(cb_type, unique_cb_coord);
}
ModuleId cb_module = module_manager.find_module(cb_module_name);
ModuleId cb_module = module_manager.find_module(module_name_map.name(cb_module_name));
VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
/* Bypass empty blocks which have none configurable children */
@ -596,7 +596,7 @@ static void build_connection_block_bitstreams(
void build_routing_bitstream(
BitstreamManager& bitstream_manager,
const ConfigBlockId& top_configurable_block,
const ModuleManager& module_manager, const FabricTile& fabric_tile,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map, const FabricTile& fabric_tile,
const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
@ -636,7 +636,7 @@ void build_routing_bitstream(
unique_sb_coord.set_y(unique_mirror.get_sb_y());
sb_module_name = generate_switch_block_module_name(unique_sb_coord);
}
ModuleId sb_module = module_manager.find_module(sb_module_name);
ModuleId sb_module = module_manager.find_module(module_name_map.name(sb_module_name));
VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
/* Bypass empty blocks which have none configurable children */
@ -725,7 +725,7 @@ void build_routing_bitstream(
VTR_LOG("Generating bitstream for X-direction Connection blocks ...");
build_connection_block_bitstreams(
bitstream_manager, top_configurable_block, module_manager, fabric_tile,
bitstream_manager, top_configurable_block, module_manager, module_name_map, fabric_tile,
circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation,
rr_graph, device_rr_gsb, compact_routing_hierarchy, CHANX, verbose);
VTR_LOG("Done\n");
@ -733,7 +733,7 @@ void build_routing_bitstream(
VTR_LOG("Generating bitstream for Y-direction Connection blocks ...");
build_connection_block_bitstreams(
bitstream_manager, top_configurable_block, module_manager, fabric_tile,
bitstream_manager, top_configurable_block, module_manager, module_name_map, fabric_tile,
circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation,
rr_graph, device_rr_gsb, compact_routing_hierarchy, CHANY, verbose);
VTR_LOG("Done\n");

3
openfpga/src/fpga_bitstream/build_routing_bitstream.h
View File

@ -14,6 +14,7 @@
#include "device_rr_gsb.h"
#include "fabric_tile.h"
#include "module_manager.h"
#include "module_name_map.h"
#include "mux_library.h"
#include "vpr_context.h"
#include "vpr_device_annotation.h"
@ -29,7 +30,7 @@ namespace openfpga {
void build_routing_bitstream(
BitstreamManager& bitstream_manager,
const ConfigBlockId& top_configurable_block,
const ModuleManager& module_manager, const FabricTile& fabric_tile,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map, const FabricTile& fabric_tile,
const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,