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[core] working on logical and physical children

This commit is contained in:
tangxifan 2023-08-02 19:46:27 -07:00
parent c05f12ac11
commit 87f2822ef8
16 changed files with 91 additions and 75 deletions
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20
openfpga/src/base/openfpga_naming.cpp
View File

@ -234,7 +234,7 @@ std::string generate_memory_module_name(const CircuitLibrary& circuit_lib,
const bool& feedthrough_memory) {
std::string mid_name;
if (feedthrough_memory) {
mid_name = "feedthrough_"
mid_name = "feedthrough_";
}
return std::string(circuit_lib.model_name(circuit_model) + "_" + mid_name +
circuit_lib.model_name(sram_model) + postfix);
@ -531,8 +531,8 @@ std::string generate_tile_module_netlist_name(const std::string& block_name,
/*********************************************************************
* Generate the module name of a physical memory module
**********************************************************************/
std::string generate_physical_memory_module_name(const size_t& mem_size) {
return std::string("physical_config_mem_size") + std::to_string(mem_size);
std::string generate_physical_memory_module_name(const std::string& prefix, const size_t& mem_size) {
return prefix + std::string("_config_group_mem_size") + std::to_string(mem_size);
}
/*********************************************************************
@ -764,7 +764,7 @@ std::string generate_sram_port_name(
port_name = std::string(MEMORY_FEEDTHROUGH_DATA_IN_PORT_NAME);
} else {
VTR_ASSERT(CIRCUIT_MODEL_PORT_BLB == port_type);
port_name = std::string(MEMEMORY_FEEDTHROUGH_DATA_IN_INV_PORT_NAME);
port_name = std::string(MEMORY_FEEDTHROUGH_DATA_IN_INV_PORT_NAME);
}
break;
case CONFIG_MEM_SCAN_CHAIN:
@ -1099,10 +1099,10 @@ std::string generate_sb_memory_instance_name(const std::string& prefix,
const e_side& sb_side,
const size_t& track_id,
const std::string& postfix,
const bool& logical_memory) {
const bool& feedthrough_memory) {
std::string instance_name(prefix);
if (logical_memory) {
instance_name = std::string("virtual_") + instance_name;
if (feedthrough_memory) {
instance_name = std::string("feedthrough_") + instance_name;
}
instance_name += SideManager(sb_side).to_string();
instance_name += std::string("_track_") + std::to_string(track_id);
@ -1141,10 +1141,10 @@ std::string generate_cb_memory_instance_name(const std::string& prefix,
const e_side& cb_side,
const size_t& pin_id,
const std::string& postfix,
const bool& logical_memory) {
const bool& feedthrough_memory) {
std::string instance_name(prefix);
if (logical_memory) {
instance_name = std::string("virtual_") + instance_name;
if (feedthrough_memory) {
instance_name = std::string("feedthrough_") + instance_name;
}
instance_name += SideManager(cb_side).to_string();

6
openfpga/src/base/openfpga_naming.h
View File

@ -119,7 +119,7 @@ std::string generate_tile_module_port_name(const std::string& prefix,
std::string generate_tile_module_netlist_name(const std::string& block_name,
const std::string& postfix);
std::string generate_physical_memory_module_name(const size_t& mem_size);
std::string generate_physical_memory_module_name(const std::string& prefix, const size_t& mem_size);
std::string generate_sb_mux_instance_name(const std::string& prefix,
const e_side& sb_side,
@ -130,7 +130,7 @@ std::string generate_sb_memory_instance_name(const std::string& prefix,
const e_side& sb_side,
const size_t& track_id,
const std::string& postfix,
const bool& logical_memory = false);
const bool& feedthrough_memory = false);
std::string generate_cb_mux_instance_name(const std::string& prefix,
const e_side& cb_side,
@ -141,7 +141,7 @@ std::string generate_cb_memory_instance_name(const std::string& prefix,
const e_side& cb_side,
const size_t& pin_id,
const std::string& postfix,
const bool& logical_memory = false);
const bool& feedthrough_memory = false);
std::string generate_pb_mux_instance_name(const std::string& prefix,
t_pb_graph_pin* pb_graph_pin,

11
openfpga/src/base/openfpga_setup_command_template.h
View File

@ -413,12 +413,11 @@ ShellCommandId add_build_fabric_command_template(
shell_cmd.set_option_require_value(opt_group_tile, openfpga::OPT_STRING);
/* Add an option '--group_config_block' */
CommandOptionId opt_group_config_block =
shell_cmd.add_option("group_config_block", false,
"group configuration memory blocks under CLB/SB/CB "
"blocks etc. This helps to "
"reduce optimize the density of configuration memory "
"through physical design");
shell_cmd.add_option("group_config_block", false,
"group configuration memory blocks under CLB/SB/CB "
"blocks etc. This helps to "
"reduce optimize the density of configuration memory "
"through physical design");
/* Add an option '--generate_random_fabric_key' */
shell_cmd.add_option("generate_random_fabric_key", false,

2
openfpga/src/fabric/build_fpga_core_wrapper_module.cpp
View File

@ -381,7 +381,7 @@ int add_fpga_core_to_device_module_graph(ModuleManager& module_manager,
/* Now fpga_core should be the only configurable child under the top-level
* module */
module_manager.add_configurable_child(new_top_module, top_module, 0);
module_manager.add_configurable_child(new_top_module, top_module, 0, false);
return status;
}

6
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -966,7 +966,7 @@ static void rec_build_logical_tile_modules(
std::vector<ModuleId> memory_modules;
std::vector<size_t> memory_instances;
e_config_protocol mem_module_type = group_config_block ? CONFIG_MEM_FEEDTHROUGH : sram_orgz_type;
e_config_protocol_type mem_module_type = group_config_block ? CONFIG_MEM_FEEDTHROUGH : sram_orgz_type;
/* Add all the child Verilog modules as instances */
for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) {
@ -1070,7 +1070,7 @@ static void rec_build_logical_tile_modules(
* This is a one-shot addition that covers all the memory modules in this pb
* module!
*/
if (0 < module_manager.configurable_children(pb_module).size()) {
if (0 < module_manager.logical_configurable_children(pb_module).size()) {
add_module_nets_memory_config_bus(module_manager, decoder_lib, pb_module,
mem_module_type,
circuit_lib.design_tech_type(sram_model));
@ -1258,7 +1258,7 @@ static void build_physical_tile_module(
* This is a one-shot addition that covers all the memory modules in this pb
* module!
*/
if (0 < module_manager.configurable_children(grid_module).size()) {
if (0 < module_manager.logical_configurable_children(grid_module).size()) {
add_pb_module_nets_memory_config_bus(
module_manager, decoder_lib, grid_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model));

4
openfpga/src/fabric/build_memory_modules.cpp
View File

@ -1391,7 +1391,7 @@ int add_physical_memory_module(ModuleManager& module_manager,
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, curr_module, circuit_lib, sram_model, CONFIG_MEM_FEEDTHROUGH);
std::string phy_mem_module_name = generate_physical_memory_module_name(module_num_config_bits);
std::string phy_mem_module_name = generate_physical_memory_module_name(module_manager.module_name(curr_module), module_num_config_bits);
ModuleId phy_mem_module = module_manager.find_module(phy_mem_module_name);
if (!module_manager.valid_module_id(phy_mem_module)) {
status = build_memory_group_module(module_manager, decode_lib, circuit_lib, sram_orgz_type, phy_mem_module_name, sram_model, required_phy_mem_modules);
@ -1414,7 +1414,7 @@ int add_physical_memory_module(ModuleManager& module_manager,
/* Build nets between the data output of the physical memory module and the outputs of the logical configurable children */
size_t curr_mem_pin_index = 0;
std::map<CircuitPortType, std::string> mem2mem_port_map;
std::map<e_circuit_model_port_type, std::string> mem2mem_port_map;
mem2mem_port_map[CIRCUIT_MODEL_PORT_BL] = std::string(CONFIGURABLE_MEMORY_DATA_OUT_NAME);
mem2mem_port_map[CIRCUIT_MODEL_PORT_BLB] = std::string(CONFIGURABLE_MEMORY_INVERTED_DATA_OUT_NAME);
for (size_t ichild = 0; ichild < module_manager.logical_configurable_children(curr_module).size(); ++ichild) {

2
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -1479,7 +1479,7 @@ static int build_tile_module(
* This is a one-shot addition that covers all the memory modules in this pb
* module!
*/
if (0 < module_manager.configurable_children(tile_module).size()) {
if (0 < module_manager.logical_configurable_children(tile_module).size()) {
add_pb_module_nets_memory_config_bus(
module_manager, decoder_lib, tile_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model));

40
openfpga/src/fabric/build_top_module_memory.cpp
View File

@ -86,6 +86,7 @@ static void organize_top_module_tile_cb_modules(
module_manager.add_configurable_child(
top_module, cb_module,
cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)],
false,
config_coord);
}
}
@ -173,7 +174,7 @@ static void organize_top_module_tile_memory_modules(
rr_gsb.get_sb_y() * 2 + 1);
module_manager.add_configurable_child(
top_module, sb_module,
sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()], config_coord);
sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()], false, config_coord);
}
}
@ -218,7 +219,7 @@ static void organize_top_module_tile_memory_modules(
sram_model, sram_orgz_type)) {
vtr::Point<int> config_coord(tile_coord.x() * 2, tile_coord.y() * 2);
module_manager.add_configurable_child(
top_module, grid_module,
top_module, grid_module, false,
grid_instance_ids[tile_coord.x()][tile_coord.y()], config_coord);
}
}
@ -269,14 +270,14 @@ void build_top_module_configurable_regions(
"Build configurable regions for the top module");
/* Ensure we have valid configurable children */
VTR_ASSERT(false == module_manager.configurable_children(top_module).empty());
VTR_ASSERT(false == module_manager.logical_configurable_children(top_module).empty());
/* Ensure that our region definition is valid */
VTR_ASSERT(1 <= config_protocol.num_regions());
/* Exclude decoders from the list */
size_t num_configurable_children =
module_manager.configurable_children(top_module).size();
module_manager.logical_configurable_children(top_module).size();
if (CONFIG_MEM_MEMORY_BANK == config_protocol.type() ||
CONFIG_MEM_QL_MEMORY_BANK == config_protocol.type()) {
num_configurable_children -= 2;
@ -291,7 +292,7 @@ void build_top_module_configurable_regions(
bool create_region = true;
ConfigRegionId curr_region = ConfigRegionId::INVALID();
for (size_t ichild = 0;
ichild < module_manager.configurable_children(top_module).size();
ichild < module_manager.logical_configurable_children(top_module).size();
++ichild) {
if (true == create_region) {
curr_region = module_manager.add_config_region(top_module);
@ -300,8 +301,8 @@ void build_top_module_configurable_regions(
/* Add the child to a region */
module_manager.add_configurable_child_to_region(
top_module, curr_region,
module_manager.configurable_children(top_module)[ichild],
module_manager.configurable_child_instances(top_module)[ichild], ichild);
module_manager.logical_configurable_children(top_module)[ichild],
module_manager.logical_configurable_child_instances(top_module)[ichild], ichild);
/* See if the current region is full or not:
* For the last region, we will keep adding until we finish all the children
@ -541,11 +542,11 @@ void shuffle_top_module_configurable_children(
/* Cache the configurable children and their instances */
std::vector<ModuleId> orig_configurable_children =
module_manager.configurable_children(top_module);
module_manager.logical_configurable_children(top_module);
std::vector<size_t> orig_configurable_child_instances =
module_manager.configurable_child_instances(top_module);
module_manager.logical_configurable_child_instances(top_module);
std::vector<vtr::Point<int>> orig_configurable_child_coordinates =
module_manager.configurable_child_coordinates(top_module);
module_manager.logical_configurable_child_coordinates(top_module);
/* Reorganize the configurable children */
module_manager.clear_configurable_children(top_module);
@ -554,6 +555,7 @@ void shuffle_top_module_configurable_children(
module_manager.add_configurable_child(
top_module, orig_configurable_children[shuffled_keys[ikey]],
orig_configurable_child_instances[shuffled_keys[ikey]],
false,
orig_configurable_child_coordinates[shuffled_keys[ikey]]);
}
@ -651,7 +653,7 @@ int load_top_module_memory_modules_from_fabric_key(
/* Now we can add the child to configurable children of the top module */
module_manager.add_configurable_child(top_module, instance_info.first,
instance_info.second,
instance_info.second, false,
fabric_key.key_coordinate(key));
module_manager.add_configurable_child_to_region(
top_module, top_module_config_region, instance_info.first,
@ -1330,16 +1332,16 @@ static void add_top_module_nets_cmos_memory_bank_config_bus(
* configurable children
*/
module_manager.add_configurable_child(top_module, bl_decoder_module,
curr_bl_decoder_instance_id);
curr_bl_decoder_instance_id, false);
module_manager.add_configurable_child_to_region(
top_module, config_region, bl_decoder_module, curr_bl_decoder_instance_id,
module_manager.configurable_children(top_module).size() - 1);
module_manager.logical_configurable_children(top_module).size() - 1);
module_manager.add_configurable_child(top_module, wl_decoder_module,
curr_wl_decoder_instance_id);
curr_wl_decoder_instance_id, false);
module_manager.add_configurable_child_to_region(
top_module, config_region, wl_decoder_module, curr_wl_decoder_instance_id,
module_manager.configurable_children(top_module).size() - 1);
module_manager.logical_configurable_children(top_module).size() - 1);
}
}
@ -1760,7 +1762,7 @@ static void add_top_module_nets_cmos_memory_frame_decoder_config_bus(
++mem_index) {
ModuleId child_module = configurable_children[mem_index];
size_t child_instance =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.logical_configurable_child_instances(parent_module)[mem_index];
ModulePortId child_din_port = module_manager.find_module_port(
child_module, std::string(DECODER_DATA_IN_PORT_NAME));
BasicPort child_din_port_info =
@ -1795,7 +1797,7 @@ static void add_top_module_nets_cmos_memory_frame_decoder_config_bus(
++mem_index) {
ModuleId child_module = configurable_children[mem_index];
size_t child_instance =
module_manager.configurable_child_instances(parent_module)[mem_index];
module_manager.logical_configurable_child_instances(parent_module)[mem_index];
ModulePortId child_en_port = module_manager.find_module_port(
child_module, std::string(DECODER_ENABLE_PORT_NAME));
BasicPort child_en_port_info =
@ -1815,11 +1817,11 @@ static void add_top_module_nets_cmos_memory_frame_decoder_config_bus(
/* Add the decoder as the last configurable children */
module_manager.add_configurable_child(parent_module, decoder_module,
decoder_instance);
decoder_instance, false);
/* Register the configurable child to configuration region */
module_manager.add_configurable_child_to_region(
parent_module, config_region, decoder_module, decoder_instance,
module_manager.configurable_children(parent_module).size() - 1);
module_manager.logical_configurable_children(parent_module).size() - 1);
}
/*********************************************************************

10
openfpga/src/fabric/fabric_key_writer.cpp
View File

@ -32,7 +32,7 @@ static int add_module_keys_to_fabric_key(const ModuleManager& module_manager,
return CMD_EXEC_SUCCESS;
}
/* Bypass modules which does not have any configurable children */
if (module_manager.configurable_children(curr_module).empty()) {
if (module_manager.logical_configurable_children(curr_module).empty()) {
return CMD_EXEC_SUCCESS;
}
/* Now create the module and add subkey one by one */
@ -41,12 +41,12 @@ static int add_module_keys_to_fabric_key(const ModuleManager& module_manager,
return CMD_EXEC_FATAL_ERROR;
}
size_t num_config_child =
module_manager.configurable_children(curr_module).size();
module_manager.logical_configurable_children(curr_module).size();
for (size_t ichild = 0; ichild < num_config_child; ++ichild) {
ModuleId child_module =
module_manager.configurable_children(curr_module)[ichild];
module_manager.logical_configurable_children(curr_module)[ichild];
size_t child_instance =
module_manager.configurable_child_instances(curr_module)[ichild];
module_manager.logical_configurable_child_instances(curr_module)[ichild];
FabricSubKeyId sub_key = fabric_key.create_module_key(key_module_id);
fabric_key.set_sub_key_name(sub_key,
@ -111,7 +111,7 @@ int write_fabric_key_to_xml_file(
/* Build a fabric key database by visiting all the configurable children */
FabricKey fabric_key;
size_t num_keys = module_manager.configurable_children(top_module).size();
size_t num_keys = module_manager.logical_configurable_children(top_module).size();
fabric_key.reserve_keys(num_keys);

6
openfpga/src/fabric/module_manager.cpp
View File

@ -1384,9 +1384,9 @@ void ModuleManager::clear_configurable_children(const ModuleId& parent_module) {
logical_configurable_child_regions_[parent_module].clear();
logical_configurable_child_coordinates_[parent_module].clear();
parent_configurable_children_[parent_module].clear();
parent_configurable_child_instances_[parent_module].clear();
parent_configurable_child_parents_[parent_module].clear();
physical_configurable_children_[parent_module].clear();
physical_configurable_child_instances_[parent_module].clear();
physical_configurable_child_parents_[parent_module].clear();
}
void ModuleManager::clear_config_region(const ModuleId& parent_module) {

17
openfpga/src/fabric/module_manager.h
View File

@ -555,8 +555,23 @@ class ModuleManager {
physical_configurable_child_instances_; /* Instances of child modules with
configurable memory bits that this module
contain */
vtr::vector<ModuleId, std::vector<ConfigRegionId>>
physical_configurable_child_regions_; /* Instances of child modules with configurable
memory bits that this module contain */
vtr::vector<ModuleId, std::vector<vtr::Point<int>>>
physical_configurable_child_coordinates_; /* Relative coorindates of child modules
with configurable memory bits that this
module contain */
vtr::vector<ModuleId, std::vector<ModuleId>>
physical_configurable_child_parents_; /* Parent modules with configurable memory bits that
logical2physical_configurable_children_; /* Child modules with configurable memory bits that
this module contain */
vtr::vector<ModuleId, std::vector<size_t>>
logical2physical_configurable_child_instances_; /* Instances of child modules with
configurable memory bits that this module
contain */
vtr::vector<ModuleId, std::vector<ModuleId>>
logical2physical_configurable_child_parents_; /* Parent modules with configurable memory bits that
this module contain */
/* Configurable regions to group the physical configurable children

12
openfpga/src/fpga_bitstream/build_device_bitstream.cpp
View File

@ -35,15 +35,15 @@ static size_t rec_estimate_device_bitstream_num_blocks(
* actually configurable memory elements
* We skip them in couting
*/
if (0 == module_manager.configurable_children(top_module).size()) {
if (0 == module_manager.logical_configurable_children(top_module).size()) {
return 0;
}
size_t num_configurable_children =
module_manager.configurable_children(top_module).size();
module_manager.logical_configurable_children(top_module).size();
for (size_t ichild = 0; ichild < num_configurable_children; ++ichild) {
ModuleId child_module =
module_manager.configurable_children(top_module)[ichild];
module_manager.logical_configurable_children(top_module)[ichild];
num_blocks +=
rec_estimate_device_bitstream_num_blocks(module_manager, child_module);
}
@ -68,7 +68,7 @@ static size_t rec_estimate_device_bitstream_num_bits(
/* If a child module has no configurable children, this is a leaf node
* We can count it in. Otherwise, we should go recursively.
*/
if (0 == module_manager.configurable_children(parent_module).size()) {
if (0 == module_manager.logical_configurable_children(parent_module).size()) {
return 1;
}
@ -105,7 +105,7 @@ static size_t rec_estimate_device_bitstream_num_bits(
VTR_ASSERT_SAFE(parent_module != top_module);
size_t num_configurable_children =
module_manager.configurable_children(parent_module).size();
module_manager.logical_configurable_children(parent_module).size();
/* Frame-based configuration protocol will have 1 decoder
* if there are more than 1 configurable children
@ -117,7 +117,7 @@ static size_t rec_estimate_device_bitstream_num_bits(
for (size_t ichild = 0; ichild < num_configurable_children; ++ichild) {
ModuleId child_module =
module_manager.configurable_children(parent_module)[ichild];
module_manager.logical_configurable_children(parent_module)[ichild];
num_bits += rec_estimate_device_bitstream_num_bits(
module_manager, top_module, child_module, config_protocol);
}

20
openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
View File

@ -74,12 +74,12 @@ static void rec_build_module_fabric_dependent_chain_bitstream(
} else {
for (size_t child_id = 0;
child_id <
module_manager.configurable_children(parent_module).size();
module_manager.logical_configurable_children(parent_module).size();
++child_id) {
ModuleId child_module =
module_manager.configurable_children(parent_module)[child_id];
module_manager.logical_configurable_children(parent_module)[child_id];
size_t child_instance =
module_manager.configurable_child_instances(parent_module)[child_id];
module_manager.logical_configurable_child_instances(parent_module)[child_id];
/* Get the instance name and ensure it is not empty */
std::string instance_name = module_manager.instance_name(
parent_module, child_module, child_instance);
@ -196,7 +196,7 @@ static void rec_build_module_fabric_dependent_memory_bank_bitstream(
* - no need to exclude decoders as they are not there
*/
std::vector<ModuleId> configurable_children =
module_manager.configurable_children(parent_module);
module_manager.logical_configurable_children(parent_module);
size_t num_configurable_children = configurable_children.size();
@ -212,7 +212,7 @@ static void rec_build_module_fabric_dependent_memory_bank_bitstream(
++child_id) {
ModuleId child_module = configurable_children[child_id];
size_t child_instance =
module_manager.configurable_child_instances(parent_module)[child_id];
module_manager.logical_configurable_child_instances(parent_module)[child_id];
/* Get the instance name and ensure it is not empty */
std::string instance_name = module_manager.instance_name(
@ -324,9 +324,9 @@ static void rec_build_module_fabric_dependent_frame_bitstream(
} else {
VTR_ASSERT(top_module != parent_module);
configurable_children =
module_manager.configurable_children(parent_module);
module_manager.logical_configurable_children(parent_module);
configurable_child_instances =
module_manager.configurable_child_instances(parent_module);
module_manager.logical_configurable_child_instances(parent_module);
}
size_t num_configurable_children = configurable_children.size();
@ -361,9 +361,9 @@ static void rec_build_module_fabric_dependent_frame_bitstream(
* configurable children in all the regions
*/
for (const ModuleId& child_module :
module_manager.configurable_children(parent_module)) {
module_manager.logical_configurable_children(parent_module)) {
/* Bypass any decoder module (which no configurable children */
if (module_manager.configurable_children(child_module).empty()) {
if (module_manager.logical_configurable_children(child_module).empty()) {
continue;
}
const ModulePortId& child_addr_port_id =
@ -494,7 +494,7 @@ static void rec_build_module_fabric_dependent_frame_bitstream(
} else {
VTR_ASSERT(top_module != parent_modules.back());
configurable_children =
module_manager.configurable_children(parent_modules.back());
module_manager.logical_configurable_children(parent_modules.back());
}
ModuleId decoder_module = configurable_children.back();

4
openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp
View File

@ -123,7 +123,7 @@ static void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(
* - no need to exclude decoders as they are not there
*/
std::vector<ModuleId> configurable_children =
module_manager.configurable_children(parent_module);
module_manager.logical_configurable_children(parent_module);
size_t num_configurable_children = configurable_children.size();
@ -139,7 +139,7 @@ static void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(
++child_id) {
ModuleId child_module = configurable_children[child_id];
size_t child_instance =
module_manager.configurable_child_instances(parent_module)[child_id];
module_manager.logical_configurable_child_instances(parent_module)[child_id];
/* Get the instance name and ensure it is not empty */
std::string instance_name = module_manager.instance_name(

2
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -636,7 +636,7 @@ static void rec_build_physical_block_bitstream(
VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
/* Skip module with no configurable children */
if (0 == module_manager.configurable_children(pb_module).size()) {
if (0 == module_manager.logical_configurable_children(pb_module).size()) {
return;
}

4
openfpga/src/utils/module_manager_utils.cpp
View File

@ -89,8 +89,8 @@ size_t count_module_manager_module_configurable_children(
const ModuleManager& module_manager, const ModuleId& module) {
size_t num_config_children = 0;
for (const ModuleId& child : module_manager.configurable_children(module)) {
if (0 != module_manager.configurable_children(child).size()) {
for (const ModuleId& child : module_manager.logical_configurable_children(module)) {
if (0 != module_manager.logical_configurable_children(child).size()) {
num_config_children++;
}
}