riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] fixed some bugs

This commit is contained in:
tangxifan 2023-09-23 12:15:31 -07:00
parent 860cfd53c6
commit 11de8965a8
3 changed files with 33 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga/src/base/openfpga_build_fabric_template.h
View File

@ -369,7 +369,7 @@ int rename_modules_template(T& openfpga_ctx, const Command& cmd,
}
/* Apply renaming on the user version */
status = rename_fabric_modules(openfpga_ctx.mutable_module_graph(),
status = partial_rename_fabric_modules(openfpga_ctx.mutable_module_graph(),
user_module_name_map,
cmd_context.option_enable(cmd, opt_verbose));
if (status != CMD_EXEC_SUCCESS) {

28
openfpga/src/fabric/rename_modules.cpp
View File

@ -92,6 +92,7 @@ int update_module_map_name_with_indexing_names(ModuleNameMap& module_name_map,
return CMD_EXEC_SUCCESS;
}
/** @brief Apply module renaming for all the modules. Require the module name map cover all the modules */
int rename_fabric_modules(ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const bool& verbose) {
@ -118,6 +119,33 @@ int rename_fabric_modules(ModuleManager& module_manager,
return status;
}
/** @brief Apply module renaming based on the pairs given by module name map only. So not all the modules are renamed. So the module name map just cover a subset of modules */
int partial_rename_fabric_modules(ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
size_t cnt = 0;
for (std::string built_in_name : module_name_map.tags()) {
ModuleId curr_module = module_manager.find_module(built_in_name);
if (!module_manager.valid_module_id(curr_module)) {
VTR_LOG_ERROR("The built-in module name '%s' does not exist! Abort renaming...\n", built_in_name.c_str());
return CMD_EXEC_FATAL_ERROR;
}
std::string new_name =
module_name_map.name(built_in_name);
if (new_name != built_in_name) {
VTR_LOGV(verbose, "Rename module '%s' to its new name '%s'\n",
built_in_name.c_str(),
new_name.c_str());
module_manager.set_module_name(curr_module, new_name);
}
cnt++;
}
VTR_LOG("Renamed %lu modules\n", cnt);
return status;
}
/** @brief The module name map kept in openfpga context always has a built-in name with coordinates.
* while users apply renaming or other internal renaming is applied, e.g., through option '--name_module_using_index', the module name in the module graph can be changed. So in the user's version, the built-in name may become index or anything else.
* We have to keep the built-in name consistent (use coordinates, otherwise other engines may not work, which rely on this convention) while the given name should follow the users' definition. So we need an update here

4
openfpga/src/fabric/rename_modules.h
View File

@ -29,6 +29,10 @@ int rename_fabric_modules(ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const bool& verbose);
int partial_rename_fabric_modules(ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const bool& verbose);
int update_module_name_map_with_user_version(ModuleNameMap& curr_module_name_map,
const ModuleNameMap& user_module_name_map,
const bool& verbose);