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[core] code format

This commit is contained in:
tangxifan 2023-09-15 23:32:40 -07:00
parent c85c64eb5a
commit 37573abc22
14 changed files with 144 additions and 102 deletions
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15
libs/libnamemanager/src/base/module_name_map.cpp
View File

@ -20,7 +20,8 @@ namespace openfpga {
std::string ModuleNameMap::name(const std::string& tag) const {
auto result = tag2names_.find(tag);
if (result == tag2names_.end()) {
VTR_LOG_ERROR("The given built-in name '%s' does not exist!\n", tag.c_str());
VTR_LOG_ERROR("The given built-in name '%s' does not exist!\n",
tag.c_str());
return std::string();
}
return result->second;
@ -34,9 +35,10 @@ std::vector<std::string> ModuleNameMap::tags() const {
return keys;
}
int ModuleNameMap::set_tag_to_name_pair(const std::string& tag, const std::string& name) {
int ModuleNameMap::set_tag_to_name_pair(const std::string& tag,
const std::string& name) {
/* tagA <--x--> nameA
* |
* |
* +----> nameB
* tagB <--x--> nameB
* Scenarios to be considered:
@ -45,7 +47,10 @@ int ModuleNameMap::set_tag_to_name_pair(const std::string& tag, const std::strin
*/
auto result = name2tags_.find(name);
if (result != name2tags_.end() && result->second != tag) {
VTR_LOG_ERROR("The customized name '%s' has already been mapped to a built-in name '%s'! Fail to bind it to a new built-in name '%s'\n", name.c_str(), result->second.c_str(), tag.c_str());
VTR_LOG_ERROR(
"The customized name '%s' has already been mapped to a built-in name "
"'%s'! Fail to bind it to a new built-in name '%s'\n",
name.c_str(), result->second.c_str(), tag.c_str());
return CMD_EXEC_FATAL_ERROR;
}
/* Clean up */
@ -54,7 +59,7 @@ int ModuleNameMap::set_tag_to_name_pair(const std::string& tag, const std::strin
name2tags_[name] = tag;
tag2names_[tag] = name;
return CMD_EXEC_SUCCESS;
}
}
void ModuleNameMap::clear() {
tag2names_.clear();

12
libs/libnamemanager/src/base/module_name_map.h
View File

@ -4,15 +4,16 @@
/********************************************************************
* Include header files required by the data structure definition
*******************************************************************/
#include <map>
#include <string>
#include <vector>
#include <map>
/* Begin namespace openfpga */
namespace openfpga {
/**
* @brief Module name map is a data structure to show mapping between a tag (built-in name) and customized names (may be given by users)
* @brief Module name map is a data structure to show mapping between a tag
* (built-in name) and customized names (may be given by users)
*/
class ModuleNameMap {
public: /* Public accessors */
@ -22,13 +23,16 @@ class ModuleNameMap {
std::vector<std::string> tags() const;
public: /* Public mutators */
/** @brief Create the one-on-one mapping between an built-in name and a customized name. Return 0 for success, return 1 for fail */
/** @brief Create the one-on-one mapping between an built-in name and a
* customized name. Return 0 for success, return 1 for fail */
int set_tag_to_name_pair(const std::string& tag, const std::string& name);
/** @brief Reset to empty status. Clear all the storage */
void clear();
private: /* Internal Data */
/* built-in name -> customized_name
* Create a double link to check any customized name is mapped to more than 1 built-in name!
* Create a double link to check any customized name is mapped to more than 1
* built-in name!
*/
std::map<std::string, std::string> tag2names_;
std::map<std::string, std::string> name2tags_;

10
libs/libnamemanager/src/io/read_xml_module_name_map.cpp
View File

@ -27,8 +27,8 @@ namespace openfpga { // Begin namespace openfpga
* Parse XML codes of a <port> to an object of I/O naming
*******************************************************************/
static int read_xml_module_name_binding(pugi::xml_node& xml_binding,
const pugiutil::loc_data& loc_data,
ModuleNameMap& module_name_map) {
const pugiutil::loc_data& loc_data,
ModuleNameMap& module_name_map) {
std::string default_name =
get_attribute(xml_binding, XML_MODULE_NAME_ATTRIBUTE_DEFAULT, loc_data)
.as_string();
@ -42,7 +42,8 @@ static int read_xml_module_name_binding(pugi::xml_node& xml_binding,
/********************************************************************
* Parse XML codes about <ports> to an object of ClockNetwork
*******************************************************************/
int read_xml_module_name_map(const char* fname, ModuleNameMap& module_name_map) {
int read_xml_module_name_map(const char* fname,
ModuleNameMap& module_name_map) {
vtr::ScopedStartFinishTimer timer("Read module rename rules");
int status = CMD_EXEC_SUCCESS;
@ -62,7 +63,8 @@ int read_xml_module_name_map(const char* fname, ModuleNameMap& module_name_map)
if (xml_binding.name() != std::string(XML_MODULE_NAME_NODE_NAME)) {
bad_tag(xml_binding, loc_data, xml_root, {XML_MODULE_NAME_NODE_NAME});
}
status = read_xml_module_name_binding(xml_binding, loc_data, module_name_map);
status =
read_xml_module_name_binding(xml_binding, loc_data, module_name_map);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}

17
libs/libnamemanager/src/io/write_xml_module_name_map.cpp
View File

@ -30,8 +30,9 @@ namespace openfpga { // Begin namespace openfpga
* Return 1 if there are more serious bugs in the architecture
* Return 2 if fail when creating files
*******************************************************************/
static int write_xml_module_name_binding(std::fstream& fp, const ModuleNameMap& module_name_map,
const std::string& built_in_name) {
static int write_xml_module_name_binding(std::fstream& fp,
const ModuleNameMap& module_name_map,
const std::string& built_in_name) {
/* Validate the file stream */
if (false == openfpga::valid_file_stream(fp)) {
return 2;
@ -44,11 +45,11 @@ static int write_xml_module_name_binding(std::fstream& fp, const ModuleNameMap&
std::string given_name = module_name_map.name(built_in_name);
if (given_name.empty()) {
VTR_LOG_ERROR("Default name '%s' is not mapped to any given name!\n", built_in_name.c_str());
VTR_LOG_ERROR("Default name '%s' is not mapped to any given name!\n",
built_in_name.c_str());
return 1;
}
write_xml_attribute(fp, XML_MODULE_NAME_ATTRIBUTE_GIVEN,
given_name.c_str());
write_xml_attribute(fp, XML_MODULE_NAME_ATTRIBUTE_GIVEN, given_name.c_str());
fp << ">"
<< "\n";
@ -62,7 +63,8 @@ static int write_xml_module_name_binding(std::fstream& fp, const ModuleNameMap&
* Return 1 if there are more serious bugs in the architecture
* Return 2 if fail when creating files
*******************************************************************/
int write_xml_module_name_map(const char* fname, const ModuleNameMap& module_name_map) {
int write_xml_module_name_map(const char* fname,
const ModuleNameMap& module_name_map) {
vtr::ScopedStartFinishTimer timer("Write module renaming rules");
/* Create a file handler */
@ -83,7 +85,8 @@ int write_xml_module_name_map(const char* fname, const ModuleNameMap& module_nam
/* Write each port */
for (std::string built_in_name : module_name_map.tags()) {
/* Write bus */
err_code = write_xml_module_name_binding(fp, module_name_map, built_in_name);
err_code =
write_xml_module_name_binding(fp, module_name_map, built_in_name);
if (0 != err_code) {
return err_code;
}

3
libs/libnamemanager/src/io/write_xml_module_name_map.h
View File

@ -13,7 +13,8 @@
*******************************************************************/
namespace openfpga { // Begin namespace openfpga
int write_xml_module_name_map(const char* fname, const ModuleNameMap& module_name_map);
int write_xml_module_name_map(const char* fname,
const ModuleNameMap& module_name_map);
} // End of namespace openfpga

20
openfpga/src/base/openfpga_build_fabric_template.h
View File

@ -20,9 +20,9 @@
#include "read_xml_io_name_map.h"
#include "read_xml_module_name_map.h"
#include "read_xml_tile_config.h"
#include "rename_modules.h"
#include "vtr_log.h"
#include "vtr_time.h"
#include "rename_modules.h"
/* begin namespace openfpga */
namespace openfpga {
@ -105,7 +105,8 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd,
CommandOptionId opt_load_fabric_key = cmd.option("load_fabric_key");
CommandOptionId opt_group_tile = cmd.option("group_tile");
CommandOptionId opt_group_config_block = cmd.option("group_config_block");
CommandOptionId opt_name_module_using_index = cmd.option("name_module_using_index");
CommandOptionId opt_name_module_using_index =
cmd.option("name_module_using_index");
CommandOptionId opt_verbose = cmd.option("verbose");
/* Report conflicts with options:
@ -176,10 +177,9 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd,
curr_status = build_device_module_graph(
openfpga_ctx.mutable_module_graph(), openfpga_ctx.mutable_decoder_lib(),
openfpga_ctx.mutable_blwl_shift_register_banks(),
openfpga_ctx.mutable_fabric_tile(),
openfpga_ctx.mutable_module_name_map(),
const_cast<const T&>(openfpga_ctx),
g_vpr_ctx.device(), cmd_context.option_enable(cmd, opt_frame_view),
openfpga_ctx.mutable_fabric_tile(), openfpga_ctx.mutable_module_name_map(),
const_cast<const T&>(openfpga_ctx), g_vpr_ctx.device(),
cmd_context.option_enable(cmd, opt_frame_view),
cmd_context.option_enable(cmd, opt_compress_routing),
cmd_context.option_enable(cmd, opt_duplicate_grid_pin),
predefined_fabric_key, tile_config,
@ -360,12 +360,16 @@ int rename_modules_template(T& openfpga_ctx, const Command& cmd,
std::string file_name = cmd_context.option_value(cmd, opt_file);
if (CMD_EXEC_SUCCESS != read_xml_module_name_map(file_name.c_str(), openfpga_ctx.mutable_module_name_map())) {
if (CMD_EXEC_SUCCESS !=
read_xml_module_name_map(file_name.c_str(),
openfpga_ctx.mutable_module_name_map())) {
return CMD_EXEC_FATAL_ERROR;
}
/* Write hierarchy to a file */
return rename_fabric_modules(openfpga_ctx.mutable_module_graph(), openfpga_ctx.module_name_map(), cmd_context.option_enable(cmd, opt_verbose));
return rename_fabric_modules(openfpga_ctx.mutable_module_graph(),
openfpga_ctx.module_name_map(),
cmd_context.option_enable(cmd, opt_verbose));
}
} /* end namespace openfpga */

10
openfpga/src/base/openfpga_context.h
View File

@ -13,9 +13,9 @@
#include "fabric_tile.h"
#include "io_location_map.h"
#include "io_name_map.h"
#include "module_name_map.h"
#include "memory_bank_shift_register_banks.h"
#include "module_manager.h"
#include "module_name_map.h"
#include "mux_library.h"
#include "netlist_manager.h"
#include "openfpga_arch.h"
@ -108,7 +108,9 @@ class OpenfpgaContext : public Context {
return io_location_map_;
}
const openfpga::IoNameMap& io_name_map() const { return io_name_map_; }
const openfpga::ModuleNameMap& module_name_map() const { return module_name_map_; }
const openfpga::ModuleNameMap& module_name_map() const {
return module_name_map_;
}
const openfpga::FabricTile& fabric_tile() const { return fabric_tile_; }
const openfpga::FabricGlobalPortInfo& fabric_global_port_info() const {
return fabric_global_port_info_;
@ -169,7 +171,9 @@ class OpenfpgaContext : public Context {
return io_location_map_;
}
openfpga::IoNameMap& mutable_io_name_map() { return io_name_map_; }
openfpga::ModuleNameMap& mutable_module_name_map() { return module_name_map_; }
openfpga::ModuleNameMap& mutable_module_name_map() {
return module_name_map_;
}
openfpga::FabricTile& mutable_fabric_tile() { return fabric_tile_; }
openfpga::FabricGlobalPortInfo& mutable_fabric_global_port_info() {
return fabric_global_port_info_;

9
openfpga/src/base/openfpga_naming.cpp
View File

@ -506,10 +506,8 @@ std::string generate_switch_block_module_name(
/*********************************************************************
* Generate the module name for a switch block with a given index
*********************************************************************/
std::string generate_switch_block_module_name_using_index(
const size_t& index) {
return std::string("sb_" + std::to_string(index) +
std::string("_"));
std::string generate_switch_block_module_name_using_index(const size_t& index) {
return std::string("sb_" + std::to_string(index) + std::string("_"));
}
/*********************************************************************
@ -594,8 +592,7 @@ std::string generate_connection_block_module_name_using_index(
exit(1);
}
return std::string(prefix + std::to_string(index) +
std::string("_"));
return std::string(prefix + std::to_string(index) + std::string("_"));
}
/*********************************************************************

3
openfpga/src/base/openfpga_naming.h
View File

@ -108,8 +108,7 @@ std::string generate_routing_track_middle_output_port_name(
std::string generate_switch_block_module_name(
const vtr::Point<size_t>& coordinate);
std::string generate_switch_block_module_name_using_index(
const size_t& index);
std::string generate_switch_block_module_name_using_index(const size_t& index);
std::string generate_connection_block_module_name(
const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate);

16
openfpga/src/base/openfpga_setup_command_template.h
View File

@ -397,7 +397,8 @@ ShellCommandId add_build_fabric_command_template(
/* Add an option '--name_module_using_index' */
shell_cmd.add_option("name_module_using_index", false,
"Use index to name modules, such as cbx_0_, rather than coordinates, such as cbx_1__0_");
"Use index to name modules, such as cbx_0_, rather than "
"coordinates, such as cbx_1__0_");
/* Add an option '--load_fabric_key' */
CommandOptionId opt_load_fkey = shell_cmd.add_option(
@ -801,8 +802,8 @@ ShellCommandId add_rename_modules_command_template(
const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
Command shell_cmd("rename_modules");
/* Add an option '--file' in short '-f'*/
CommandOptionId opt_file =
shell_cmd.add_option("file", true, "file path to the XML file that contains renaming rules");
CommandOptionId opt_file = shell_cmd.add_option(
"file", true, "file path to the XML file that contains renaming rules");
shell_cmd.set_option_short_name(opt_file, "f");
shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
@ -812,8 +813,7 @@ ShellCommandId add_rename_modules_command_template(
ShellCommandId shell_cmd_id = shell.add_command(
shell_cmd, "Rename modules with a set of given rules", hidden);
shell.set_command_class(shell_cmd_id, cmd_class_id);
shell.set_command_execute_function(shell_cmd_id,
rename_modules_template<T>);
shell.set_command_execute_function(shell_cmd_id, rename_modules_template<T>);
/* Add command dependency to the Shell */
shell.set_command_dependency(shell_cmd_id, dependent_cmds);
@ -1048,10 +1048,8 @@ void add_setup_command_templates(openfpga::Shell<T>& shell,
* 'build_fabric' */
std::vector<ShellCommandId> cmd_dependency_rename_modules;
cmd_dependency_rename_modules.push_back(build_fabric_cmd_id);
add_rename_modules_command_template<T>(
shell, openfpga_setup_cmd_class, cmd_dependency_rename_modules,
hidden);
add_rename_modules_command_template<T>(shell, openfpga_setup_cmd_class,
cmd_dependency_rename_modules, hidden);
}
} /* end namespace openfpga */

22
openfpga/src/fabric/build_device_module.cpp
View File

@ -35,14 +35,12 @@ namespace openfpga {
int build_device_module_graph(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
MemoryBankShiftRegisterBanks& blwl_sr_banks, FabricTile& fabric_tile,
ModuleNameMap& module_name_map,
const OpenfpgaContext& openfpga_ctx, const DeviceContext& vpr_device_ctx,
const bool& frame_view, const bool& compress_routing,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const TileConfig& tile_config, const bool& group_config_block,
const bool& name_module_using_index,
const bool& generate_random_fabric_key,
const bool& verbose) {
ModuleNameMap& module_name_map, const OpenfpgaContext& openfpga_ctx,
const DeviceContext& vpr_device_ctx, const bool& frame_view,
const bool& compress_routing, const bool& duplicate_grid_pin,
const FabricKey& fabric_key, const TileConfig& tile_config,
const bool& group_config_block, const bool& name_module_using_index,
const bool& generate_random_fabric_key, const bool& verbose) {
vtr::ScopedStartFinishTimer timer("Build fabric module graph");
int status = CMD_EXEC_SUCCESS;
@ -156,18 +154,20 @@ int build_device_module_graph(
openfpga_ctx.arch().circuit_lib);
/* Collect module names and initialize module name mapping */
status = init_fabric_module_name_map(module_name_map, module_manager, verbose);
status =
init_fabric_module_name_map(module_name_map, module_manager, verbose);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}
if (name_module_using_index) {
/* Update module name data */
status = update_module_map_name_with_indexing_names(module_name_map, openfpga_ctx.device_rr_gsb(), fabric_tile, verbose);
status = update_module_map_name_with_indexing_names(
module_name_map, openfpga_ctx.device_rr_gsb(), fabric_tile, verbose);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}
/* Apply module naming */
status = rename_fabric_modules(module_manager, module_name_map, verbose);
status = rename_fabric_modules(module_manager, module_name_map, verbose);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}

11
openfpga/src/fabric/build_device_module.h
View File

@ -22,12 +22,11 @@ namespace openfpga {
int build_device_module_graph(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
MemoryBankShiftRegisterBanks& blwl_sr_banks, FabricTile& fabric_tile,
ModuleNameMap& module_name_map,
const OpenfpgaContext& openfpga_ctx, const DeviceContext& vpr_device_ctx,
const bool& frame_view, const bool& compress_routing,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const TileConfig& tile_config, const bool& group_config_block,
const bool& name_module_using_index,
ModuleNameMap& module_name_map, const OpenfpgaContext& openfpga_ctx,
const DeviceContext& vpr_device_ctx, const bool& frame_view,
const bool& compress_routing, const bool& duplicate_grid_pin,
const FabricKey& fabric_key, const TileConfig& tile_config,
const bool& group_config_block, const bool& name_module_using_index,
const bool& generate_random_fabric_key, const bool& verbose);
} /* end namespace openfpga */

78
openfpga/src/fabric/rename_modules.cpp
View File

@ -1,26 +1,29 @@
/* Headers from vtrutil library */
#include "rename_modules.h"
#include "command_exit_codes.h"
#include "openfpga_naming.h"
#include "vtr_assert.h"
#include "vtr_log.h"
#include "vtr_time.h"
#include "command_exit_codes.h"
#include "openfpga_naming.h"
#include "rename_modules.h"
/* begin namespace openfpga */
namespace openfpga {
/** @brief Initialize a module name map with the existing module names from a module manager. In this case, all the built-in names are the same as customized names */
int init_fabric_module_name_map(
ModuleNameMap& module_name_map,
const ModuleManager& module_manager,
const bool& verbose) {
/** @brief Initialize a module name map with the existing module names from a
* module manager. In this case, all the built-in names are the same as
* customized names */
int init_fabric_module_name_map(ModuleNameMap& module_name_map,
const ModuleManager& module_manager,
const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
/* the module name map should be empty! */
module_name_map.clear();
size_t cnt = 0;
for (ModuleId curr_module : module_manager.modules()) {
status = module_name_map.set_tag_to_name_pair(module_manager.module_name(curr_module), module_manager.module_name(curr_module));
status = module_name_map.set_tag_to_name_pair(
module_manager.module_name(curr_module),
module_manager.module_name(curr_module));
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_SUCCESS;
}
@ -30,33 +33,46 @@ int init_fabric_module_name_map(
return CMD_EXEC_SUCCESS;
}
int update_module_map_name_with_indexing_names(ModuleNameMap& module_name_map, const DeviceRRGSB& device_rr_gsb, const FabricTile& fabric_tile, const bool& verbose) {
int update_module_map_name_with_indexing_names(ModuleNameMap& module_name_map,
const DeviceRRGSB& device_rr_gsb,
const FabricTile& fabric_tile,
const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
/* Walk through the device rr gsb on the unique routing modules */
for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
vtr::Point<size_t> gsb_coordinate(unique_mirror.get_sb_x(), unique_mirror.get_sb_y());
std::string name_using_coord = generate_switch_block_module_name(gsb_coordinate);
std::string name_using_index = generate_switch_block_module_name_using_index(isb);
status = module_name_map.set_tag_to_name_pair(name_using_coord, name_using_index);
vtr::Point<size_t> gsb_coordinate(unique_mirror.get_sb_x(),
unique_mirror.get_sb_y());
std::string name_using_coord =
generate_switch_block_module_name(gsb_coordinate);
std::string name_using_index =
generate_switch_block_module_name_using_index(isb);
status =
module_name_map.set_tag_to_name_pair(name_using_coord, name_using_index);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_SUCCESS;
}
VTR_LOGV(verbose, "Now use indexing name for module '%s' (was '%s')\n", name_using_index.c_str(), name_using_coord.c_str());
VTR_LOGV(verbose, "Now use indexing name for module '%s' (was '%s')\n",
name_using_index.c_str(), name_using_coord.c_str());
}
for (t_rr_type cb_type : {CHANX, CHANY}) {
for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(cb_type);
++icb) {
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, icb);
const RRGSB& unique_mirror =
device_rr_gsb.get_cb_unique_module(cb_type, icb);
vtr::Point<size_t> gsb_coordinate(unique_mirror.get_cb_x(cb_type),
unique_mirror.get_cb_y(cb_type));
std::string name_using_coord = generate_connection_block_module_name(cb_type, gsb_coordinate);
std::string name_using_index = generate_connection_block_module_name_using_index(cb_type, icb);
status = module_name_map.set_tag_to_name_pair(name_using_coord, name_using_index);
std::string name_using_coord =
generate_connection_block_module_name(cb_type, gsb_coordinate);
std::string name_using_index =
generate_connection_block_module_name_using_index(cb_type, icb);
status = module_name_map.set_tag_to_name_pair(name_using_coord,
name_using_index);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_SUCCESS;
}
VTR_LOGV(verbose, "Now use indexing name for module '%s' (was '%s')\n", name_using_index.c_str(), name_using_coord.c_str());
VTR_LOGV(verbose, "Now use indexing name for module '%s' (was '%s')\n",
name_using_index.c_str(), name_using_coord.c_str());
}
}
/* Walk through the fabric tile on the unique routing modules */
@ -65,29 +81,35 @@ int update_module_map_name_with_indexing_names(ModuleNameMap& module_name_map, c
vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(fabric_tile_id);
std::string name_using_coord = generate_tile_module_name(tile_coord);
std::string name_using_index = generate_tile_module_name_using_index(itile);
status = module_name_map.set_tag_to_name_pair(name_using_coord, name_using_index);
status =
module_name_map.set_tag_to_name_pair(name_using_coord, name_using_index);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_SUCCESS;
}
VTR_LOGV(verbose, "Now use indexing name for module '%s' (was '%s')\n", name_using_index.c_str(), name_using_coord.c_str());
VTR_LOGV(verbose, "Now use indexing name for module '%s' (was '%s')\n",
name_using_index.c_str(), name_using_coord.c_str());
}
return CMD_EXEC_SUCCESS;
}
int rename_fabric_modules(ModuleManager& module_manager, const ModuleNameMap& module_name_map, const bool& verbose) {
int rename_fabric_modules(ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
size_t cnt = 0;
for (ModuleId curr_module : module_manager.modules()) {
std::string new_name = module_name_map.name(module_manager.module_name(curr_module));
std::string new_name =
module_name_map.name(module_manager.module_name(curr_module));
if (new_name != module_manager.module_name(curr_module)) {
VTR_LOGV(verbose, "Rename module '%s' to its new name '%s'\n", module_manager.module_name(curr_module).c_str(), new_name.c_str());
VTR_LOGV(verbose, "Rename module '%s' to its new name '%s'\n",
module_manager.module_name(curr_module).c_str(),
new_name.c_str());
module_manager.set_module_name(curr_module, new_name);
}
cnt++;
}
VTR_LOG("Renamed %lu modules\n", cnt);
return status;
}
}
} /* end namespace openfpga */

20
openfpga/src/fabric/rename_modules.h
View File

@ -4,10 +4,10 @@
/********************************************************************
* Include header files that are required by function declaration
*******************************************************************/
#include "fabric_tile.h"
#include "device_rr_gsb.h"
#include "module_name_map.h"
#include "fabric_tile.h"
#include "module_manager.h"
#include "module_name_map.h"
/********************************************************************
* Function declaration
@ -16,14 +16,18 @@
/* begin namespace openfpga */
namespace openfpga {
int init_fabric_module_name_map(
ModuleNameMap& module_name_map,
const ModuleManager& module_manager,
const bool& verbose);
int init_fabric_module_name_map(ModuleNameMap& module_name_map,
const ModuleManager& module_manager,
const bool& verbose);
int update_module_map_name_with_indexing_names(ModuleNameMap& module_name_map, const DeviceRRGSB& device_rr_gsb, const FabricTile& fabric_tile, const bool& verbose);
int update_module_map_name_with_indexing_names(ModuleNameMap& module_name_map,
const DeviceRRGSB& device_rr_gsb,
const FabricTile& fabric_tile,
const bool& verbose);
int rename_fabric_modules(ModuleManager& module_manager, const ModuleNameMap& module_name_map, const bool& verbose);
int rename_fabric_modules(ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const bool& verbose);
} /* end namespace openfpga */