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[core] fixing bugs

This commit is contained in:
tangxifan 2023-09-17 17:57:57 -07:00
parent d5152dc16d
commit c14277a674
4 changed files with 11 additions and 6 deletions
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1
openfpga/src/base/openfpga_bitstream_template.h
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@ -73,6 +73,7 @@ int build_fabric_bitstream_template(T& openfpga_ctx, const Command& cmd,
/* Build fabric bitstream here */
openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(
openfpga_ctx.bitstream_manager(), openfpga_ctx.module_graph(),
openfpga_ctx.module_name_map(),
openfpga_ctx.arch().circuit_lib, openfpga_ctx.arch().config_protocol,
cmd_context.option_enable(cmd, opt_verbose));

4
openfpga/src/fpga_bitstream/build_device_bitstream.cpp
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@ -161,14 +161,14 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
/* Create the top-level block for bitstream
* This is related to the top-level module of fpga
*/
std::string top_block_name = generate_fpga_top_module_name();
std::string top_block_name = openfpga_ctx.module_name_map().name(generate_fpga_top_module_name());
ConfigBlockId top_block = bitstream_manager.add_block(top_block_name);
ModuleId top_module = openfpga_ctx.module_graph().find_module(top_block_name);
VTR_ASSERT(true == openfpga_ctx.module_graph().valid_module_id(top_module));
/* Create the core block when the fpga_core is added */
size_t num_blocks_to_reserve = 0;
std::string core_block_name = generate_fpga_core_module_name();
std::string core_block_name = openfpga_ctx.module_name_map().name(generate_fpga_core_module_name());
const ModuleId& core_module =
openfpga_ctx.module_graph().find_module(core_block_name);
if (openfpga_ctx.module_graph().valid_module_id(core_module)) {

7
openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
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@ -772,14 +772,15 @@ static void build_module_fabric_dependent_bitstream(
*******************************************************************/
FabricBitstream build_fabric_dependent_bitstream(
const BitstreamManager& bitstream_manager,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
const CircuitLibrary& circuit_lib,
const ConfigProtocol& config_protocol, const bool& verbose) {
FabricBitstream fabric_bitstream;
vtr::ScopedStartFinishTimer timer("\nBuild fabric dependent bitstream\n");
/* Get the top module name in module manager, which is our starting point */
std::string top_module_name = generate_fpga_top_module_name();
std::string top_module_name = module_name_map.name(generate_fpga_top_module_name());
ModuleId top_module = module_manager.find_module(top_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(top_module));
@ -793,7 +794,7 @@ FabricBitstream build_fabric_dependent_bitstream(
ConfigBlockId top_block = top_blocks[0];
/* Create the core block when the fpga_core is added */
std::string core_block_name = generate_fpga_core_module_name();
std::string core_block_name = module_name_map.name(generate_fpga_core_module_name());
const ModuleId& core_module = module_manager.find_module(core_block_name);
if (module_manager.valid_module_id(core_module)) {
/* Now we use the core_block as the top-level block for the remaining

5
openfpga/src/fpga_bitstream/build_fabric_bitstream.h
View File

@ -11,6 +11,7 @@
#include "config_protocol.h"
#include "fabric_bitstream.h"
#include "module_manager.h"
#include "module_name_map.h"
/********************************************************************
* Function declaration
@ -21,7 +22,9 @@ namespace openfpga {
FabricBitstream build_fabric_dependent_bitstream(
const BitstreamManager& bitstream_manager,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const CircuitLibrary& circuit_lib,
const ConfigProtocol& config_protocol, const bool& verbose);
} /* end namespace openfpga */