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[core] code format

This commit is contained in:
tangxifan 2023-08-08 16:28:56 -07:00
parent 867da98d3f
commit 94d80a9b7c
27 changed files with 309 additions and 317 deletions
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25
openfpga/src/annotation/annotate_rr_graph.cpp
View File

@ -21,8 +21,7 @@ namespace openfpga {
/* Build a RRChan Object with the given channel type and coorindators */
static RRChan build_one_rr_chan(const DeviceContext& vpr_device_ctx,
const t_rr_type& chan_type,
const size_t& layer,
const t_rr_type& chan_type, const size_t& layer,
vtr::Point<size_t>& chan_coord) {
std::vector<RRNodeId> chan_rr_nodes;
@ -153,8 +152,8 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
gsb_coord.y() + 1, OPIN, opin_grid_side[0]);
/* Include Grid[x+1][y+1] Left side output pins */
temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x() + 1,
gsb_coord.y() + 1, OPIN, opin_grid_side[1]);
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer,
gsb_coord.x() + 1, gsb_coord.y() + 1, OPIN, opin_grid_side[1]);
break;
case RIGHT: /* RIGHT = 1 */
@ -182,12 +181,12 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
/* include Grid[x+1][y+1] Bottom side output pins */
temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x() + 1,
gsb_coord.y() + 1, OPIN, opin_grid_side[0]);
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer,
gsb_coord.x() + 1, gsb_coord.y() + 1, OPIN, opin_grid_side[0]);
/* include Grid[x+1][y] Top side output pins */
temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x() + 1,
gsb_coord.y(), OPIN, opin_grid_side[1]);
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer,
gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]);
break;
case BOTTOM: /* BOTTOM = 2*/
/* For the border, we should take special care */
@ -213,8 +212,8 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
opin_grid_side[1] = RIGHT;
/* include Grid[x+1][y] Left side output pins */
temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x() + 1,
gsb_coord.y(), OPIN, opin_grid_side[0]);
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer,
gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[0]);
/* include Grid[x][y] Right side output pins */
temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x(),
@ -371,9 +370,9 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
continue;
}
/* Collect IPIN rr_nodes*/
temp_ipin_rr_nodes =
find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, ix,
iy, IPIN, ipin_rr_node_grid_side, include_clock);
temp_ipin_rr_nodes = find_rr_graph_grid_nodes(
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, ix, iy, IPIN,
ipin_rr_node_grid_side, include_clock);
/* Fill the ipin nodes of RRGSB */
for (const RRNodeId& inode : temp_ipin_rr_nodes) {
/* Skip those has no configurable outgoing, they should NOT appear in the

2
openfpga/src/annotation/annotate_simulation_setting.cpp
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@ -15,8 +15,8 @@
/* Headers from vpr library */
#include "AnalysisDelayCalculator.h"
#include "annotate_simulation_setting.h"
#include "net_delay.h"
#include "concrete_timing_info.h"
#include "net_delay.h"
/* begin namespace openfpga */
namespace openfpga {

67
openfpga/src/annotation/append_clock_rr_graph.cpp
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@ -88,9 +88,9 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids,
static void add_rr_graph_block_clock_nodes(
RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup,
const RRGraphView& rr_graph_view, const ClockNetwork& clk_ntwk,
const size_t& layer,
const vtr::Point<size_t> chan_coord, const t_rr_type& chan_type,
const int& cost_index_offset, const bool& verbose) {
const size_t& layer, const vtr::Point<size_t> chan_coord,
const t_rr_type& chan_type, const int& cost_index_offset,
const bool& verbose) {
size_t orig_chan_width =
rr_graph_view.node_lookup()
.find_channel_nodes(layer, chan_coord.x(), chan_coord.y(), chan_type)
@ -148,14 +148,11 @@ static void add_rr_graph_block_clock_nodes(
* Add clock nodes one by one to the routing resource graph.
* Assign node-level attributes properly and register in dedicated lookup
*******************************************************************/
static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder,
RRClockSpatialLookup& clk_rr_lookup,
const RRGraphView& rr_graph_view,
const DeviceGrid& grids,
const size_t& layer,
const bool& through_channel,
const ClockNetwork& clk_ntwk,
const bool& verbose) {
static void add_rr_graph_clock_nodes(
RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup,
const RRGraphView& rr_graph_view, const DeviceGrid& grids,
const size_t& layer, const bool& through_channel,
const ClockNetwork& clk_ntwk, const bool& verbose) {
/* Pre-allocate memory: Must do otherwise data will be messed up! */
clk_rr_lookup.reserve_nodes(grids.width(), grids.height(),
clk_ntwk.num_trees(), clk_ntwk.max_tree_depth(),
@ -171,9 +168,9 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder,
(false == is_chanx_exist(grids, layer, chanx_coord))) {
continue;
}
add_rr_graph_block_clock_nodes(rr_graph_builder, clk_rr_lookup,
rr_graph_view, clk_ntwk, layer, chanx_coord,
CHANX, CHANX_COST_INDEX_START, verbose);
add_rr_graph_block_clock_nodes(
rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer,
chanx_coord, CHANX, CHANX_COST_INDEX_START, verbose);
VTR_ASSERT(rr_graph_view.valid_node(
clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0),
ClockTreePinId(0), Direction::INC)));
@ -194,9 +191,9 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder,
continue;
}
add_rr_graph_block_clock_nodes(
rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer, chany_coord,
CHANY, CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments(),
verbose);
rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer,
chany_coord, CHANY,
CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments(), verbose);
VTR_ASSERT(rr_graph_view.valid_node(
clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0),
ClockTreePinId(0), Direction::INC)));
@ -397,11 +394,11 @@ static std::vector<RRNodeId> find_clock_track2track_node(
static void try_find_and_add_clock_track2ipin_node(
std::vector<RRNodeId>& des_nodes, const DeviceGrid& grids,
const RRGraphView& rr_graph_view, const size_t& layer,
const vtr::Point<size_t>& grid_coord,
const e_side& pin_side, const ClockNetwork& clk_ntwk,
const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) {
t_physical_tile_type_ptr grid_type =
grids.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
const vtr::Point<size_t>& grid_coord, const e_side& pin_side,
const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree,
const ClockTreePinId& clk_pin) {
t_physical_tile_type_ptr grid_type = grids.get_physical_type(
t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
for (std::string tap_pin_name :
clk_ntwk.tree_flatten_taps(clk_tree, clk_pin)) {
/* tap pin name could be 'io[5:5].a2f[0]' */
@ -445,17 +442,17 @@ static void try_find_and_add_clock_track2ipin_node(
*******************************************************************/
static std::vector<RRNodeId> find_clock_track2ipin_node(
const DeviceGrid& grids, const RRGraphView& rr_graph_view,
const t_rr_type& chan_type, const size_t& layer, const vtr::Point<size_t>& chan_coord,
const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree,
const ClockTreePinId& clk_pin) {
const t_rr_type& chan_type, const size_t& layer,
const vtr::Point<size_t>& chan_coord, const ClockNetwork& clk_ntwk,
const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) {
std::vector<RRNodeId> des_nodes;
if (chan_type == CHANX) {
/* Get the clock IPINs at the BOTTOM side of adjacent grids [x][y+1] */
vtr::Point<size_t> bot_grid_coord(chan_coord.x(), chan_coord.y() + 1);
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
layer, bot_grid_coord, BOTTOM, clk_ntwk,
clk_tree, clk_pin);
layer, bot_grid_coord, BOTTOM,
clk_ntwk, clk_tree, clk_pin);
/* Get the clock IPINs at the TOP side of adjacent grids [x][y] */
vtr::Point<size_t> top_grid_coord(chan_coord.x(), chan_coord.y());
@ -467,14 +464,14 @@ static std::vector<RRNodeId> find_clock_track2ipin_node(
/* Get the clock IPINs at the LEFT side of adjacent grids [x][y+1] */
vtr::Point<size_t> left_grid_coord(chan_coord.x() + 1, chan_coord.y());
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
layer, left_grid_coord, LEFT, clk_ntwk,
clk_tree, clk_pin);
layer, left_grid_coord, LEFT,
clk_ntwk, clk_tree, clk_pin);
/* Get the clock IPINs at the RIGHT side of adjacent grids [x][y] */
vtr::Point<size_t> right_grid_coord(chan_coord.x(), chan_coord.y());
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
layer, right_grid_coord, RIGHT, clk_ntwk,
clk_tree, clk_pin);
layer, right_grid_coord, RIGHT,
clk_ntwk, clk_tree, clk_pin);
}
return des_nodes;
@ -486,9 +483,7 @@ static std::vector<RRNodeId> find_clock_track2ipin_node(
static void add_rr_graph_block_clock_edges(
RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create,
const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view,
const DeviceGrid& grids,
const size_t& layer,
const ClockNetwork& clk_ntwk,
const DeviceGrid& grids, const size_t& layer, const ClockNetwork& clk_ntwk,
const vtr::Point<size_t>& chan_coord, const t_rr_type& chan_type,
const bool& verbose) {
size_t edge_count = 0;
@ -542,8 +537,8 @@ static void add_rr_graph_block_clock_edges(
if (clk_ntwk.is_last_level(itree, ilvl)) {
size_t curr_edge_count = edge_count;
for (RRNodeId des_node : find_clock_track2ipin_node(
grids, rr_graph_view, chan_type, layer, chan_coord, clk_ntwk, itree,
ClockTreePinId(ipin))) {
grids, rr_graph_view, chan_type, layer, chan_coord, clk_ntwk,
itree, ClockTreePinId(ipin))) {
/* Create edges */
VTR_ASSERT(rr_graph_view.valid_node(des_node));
rr_graph_builder.create_edge(src_node, des_node,

12
openfpga/src/annotation/openfpga_annotate_routing.cpp
View File

@ -3,8 +3,9 @@
* from VPR to OpenFPGA
*******************************************************************/
#include "openfpga_annotate_routing.h"
#include "old_traceback.h"
#include "annotate_routing.h"
#include "old_traceback.h"
#include "vtr_assert.h"
#include "vtr_log.h"
@ -133,14 +134,17 @@ void annotate_rr_node_previous_nodes(
/* Cache Previous nodes */
RRNodeId prev_node = RRNodeId::INVALID();
t_trace* tptr = TracebackCompat::traceback_from_route_tree(routing_ctx.route_trees[net_id].value());
t_trace* tptr = TracebackCompat::traceback_from_route_tree(
routing_ctx.route_trees[net_id].value());
while (tptr != nullptr) {
RRNodeId rr_node = RRNodeId(tptr->index);
/* Find the right previous node */
prev_node = find_previous_node_from_routing_traces(
device_ctx.rr_graph, TracebackCompat::traceback_from_route_tree(routing_ctx.route_trees[net_id].value()), prev_node,
rr_node);
device_ctx.rr_graph,
TracebackCompat::traceback_from_route_tree(
routing_ctx.route_trees[net_id].value()),
prev_node, rr_node);
/* Only update mapped nodes */
if (prev_node) {

5
openfpga/src/annotation/vpr_placement_annotation.cpp
View File

@ -32,8 +32,9 @@ void VprPlacementAnnotation::init_mapped_blocks(const DeviceGrid& grids) {
for (size_t x = 0; x < grids.width(); ++x) {
for (size_t y = 0; y < grids.height(); ++y) {
/* Deposit invalid ids and we will fill later */
blocks_[x][y].resize(grids.get_physical_type(t_physical_tile_loc(x, y, 0))->capacity,
ClusterBlockId::INVALID());
blocks_[x][y].resize(
grids.get_physical_type(t_physical_tile_loc(x, y, 0))->capacity,
ClusterBlockId::INVALID());
}
}
}

33
openfpga/src/base/openfpga_pb_pin_fixup.cpp
View File

@ -34,14 +34,13 @@ namespace openfpga {
static void update_cluster_pin_with_post_routing_results(
const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx,
const VprRoutingAnnotation& vpr_routing_annotation,
VprClusteringAnnotation& vpr_clustering_annotation,
const size_t& layer,
VprClusteringAnnotation& vpr_clustering_annotation, const size_t& layer,
const vtr::Point<size_t>& grid_coord, const ClusterBlockId& blk_id,
const e_side& border_side, const size_t& z, const bool& verbose) {
/* Handle each pin */
auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
auto physical_tile =
device_ctx.grid.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
auto physical_tile = device_ctx.grid.get_physical_type(
t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
for (int j = 0; j < logical_block->pb_type->num_pins; j++) {
/* Get the ptc num for the pin in rr_graph, we need t consider the z offset
@ -87,7 +86,8 @@ static void update_cluster_pin_with_post_routing_results(
/* Find the net mapped to this pin in routing results */
const RRNodeId& rr_node = device_ctx.rr_graph.node_lookup().find_node(
layer, grid_coord.x(), grid_coord.y(), rr_node_type, physical_pin, pin_side);
layer, grid_coord.x(), grid_coord.y(), rr_node_type, physical_pin,
pin_side);
if (false == device_ctx.rr_graph.valid_node(rr_node)) {
continue;
}
@ -197,14 +197,17 @@ void update_pb_pin_with_post_routing_results(
/* Update the core logic (center blocks of the FPGA) */
for (size_t x = 1; x < device_ctx.grid.width() - 1; ++x) {
for (size_t y = 1; y < device_ctx.grid.height() - 1; ++y) {
t_physical_tile_type_ptr phy_tile = device_ctx.grid.get_physical_type(t_physical_tile_loc(x, y, layer));
t_physical_tile_type_ptr phy_tile =
device_ctx.grid.get_physical_type(t_physical_tile_loc(x, y, layer));
/* Bypass the EMPTY tiles */
if (true == is_empty_type(phy_tile)) {
continue;
}
/* Get the mapped blocks to this grid */
for (int isubtile = 0; isubtile < phy_tile->capacity; ++isubtile) {
ClusterBlockId cluster_blk_id = placement_ctx.grid_blocks.block_at_location({(int)x, (int)y, (int)isubtile, (int)layer});
for (int isubtile = 0; isubtile < phy_tile->capacity; ++isubtile) {
ClusterBlockId cluster_blk_id =
placement_ctx.grid_blocks.block_at_location(
{(int)x, (int)y, (int)isubtile, (int)layer});
/* Skip invalid ids */
if (ClusterBlockId::INVALID() == cluster_blk_id) {
continue;
@ -214,8 +217,9 @@ void update_pb_pin_with_post_routing_results(
vtr::Point<size_t> grid_coord(x, y);
update_cluster_pin_with_post_routing_results(
device_ctx, clustering_ctx, vpr_routing_annotation,
vpr_clustering_annotation, layer, grid_coord, cluster_blk_id, NUM_SIDES,
placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, verbose);
vpr_clustering_annotation, layer, grid_coord, cluster_blk_id,
NUM_SIDES, placement_ctx.block_locs[cluster_blk_id].loc.sub_tile,
verbose);
}
}
}
@ -227,14 +231,17 @@ void update_pb_pin_with_post_routing_results(
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coord : io_coordinates[io_side]) {
t_physical_tile_type_ptr phy_tile_type =
device_ctx.grid.get_physical_type(t_physical_tile_loc(io_coord.x(), io_coord.y(), layer));
device_ctx.grid.get_physical_type(
t_physical_tile_loc(io_coord.x(), io_coord.y(), layer));
/* Bypass EMPTY grid */
if (true == is_empty_type(phy_tile_type)) {
continue;
}
/* Get the mapped blocks to this grid */
for (int isubtile = 0; isubtile < phy_tile_type->capacity; ++isubtile) {
ClusterBlockId cluster_blk_id = placement_ctx.grid_blocks.block_at_location({(int)io_coord.x(), (int)io_coord.y(), (int)isubtile, (int)layer});
for (int isubtile = 0; isubtile < phy_tile_type->capacity; ++isubtile) {
ClusterBlockId cluster_blk_id =
placement_ctx.grid_blocks.block_at_location(
{(int)io_coord.x(), (int)io_coord.y(), (int)isubtile, (int)layer});
/* Skip invalid ids */
if (ClusterBlockId::INVALID() == cluster_blk_id) {
continue;

6
openfpga/src/fabric/build_fabric_io_location_map.cpp
View File

@ -32,7 +32,8 @@ namespace openfpga {
*(x, y, z) coordinate to the actual indices
*******************************************************************/
static IoLocationMap build_fabric_fine_grained_io_location_map(
const ModuleManager& module_manager, const DeviceGrid& grids, const size_t& layer) {
const ModuleManager& module_manager, const DeviceGrid& grids,
const size_t& layer) {
vtr::ScopedStartFinishTimer timer(
"Create I/O location mapping for top module");
@ -154,7 +155,8 @@ static IoLocationMap build_fabric_fine_grained_io_location_map(
*(x, y, z) coordinate to the actual indices
*******************************************************************/
static IoLocationMap build_fabric_tiled_io_location_map(
const ModuleManager& module_manager, const DeviceGrid& grids, const size_t& layer) {
const ModuleManager& module_manager, const DeviceGrid& grids,
const size_t& layer) {
vtr::ScopedStartFinishTimer timer(
"Create I/O location mapping for top module");

3
openfpga/src/fabric/build_fabric_tile.cpp
View File

@ -38,7 +38,8 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile,
for (size_t ix = 0; ix < grids.width(); ++ix) {
for (size_t iy = 0; iy < grids.height(); ++iy) {
t_physical_tile_loc tile_loc(ix, iy, layer);
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc);
t_physical_tile_type_ptr phy_tile_type =
grids.get_physical_type(tile_loc);
bool skip_add_pb = false;
vtr::Point<size_t> curr_tile_coord(ix, iy);
vtr::Point<size_t> curr_gsb_coord(ix, iy - 1);

12
openfpga/src/fabric/build_routing_module_utils.cpp
View File

@ -76,8 +76,10 @@ std::string generate_sb_module_grid_port_name(
/* Collect the attributes of the rr_node required to generate the port name */
int pin_id = rr_graph.node_pin_num(rr_node);
e_side pin_side = get_rr_graph_single_node_side(rr_graph, rr_node);
t_physical_tile_type_ptr physical_tile = vpr_device_grid.get_physical_type(
t_physical_tile_loc(rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), rr_graph.node_layer(rr_node)));
t_physical_tile_type_ptr physical_tile =
vpr_device_grid.get_physical_type(t_physical_tile_loc(
rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node),
rr_graph.node_layer(rr_node)));
int pin_width_offset = physical_tile->pin_width_offset[pin_id];
int pin_height_offset = physical_tile->pin_height_offset[pin_id];
BasicPort pin_info =
@ -110,8 +112,10 @@ std::string generate_cb_module_grid_port_name(
/* Collect the attributes of the rr_node required to generate the port name */
int pin_id = rr_graph.node_pin_num(rr_node);
e_side pin_side = get_rr_graph_single_node_side(rr_graph, rr_node);
t_physical_tile_type_ptr physical_tile = vpr_device_grid.get_physical_type(t_physical_tile_loc(
rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), rr_graph.node_layer(rr_node)));
t_physical_tile_type_ptr physical_tile =
vpr_device_grid.get_physical_type(t_physical_tile_loc(
rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node),
rr_graph.node_layer(rr_node)));
int pin_width_offset = physical_tile->pin_width_offset[pin_id];
int pin_height_offset = physical_tile->pin_height_offset[pin_id];
BasicPort pin_info =

47
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -125,8 +125,8 @@ static int build_tile_module_port_and_nets_between_sb_and_pb(
size_t src_grid_pin_index = rr_graph.node_pin_num(
rr_gsb.get_opin_node(side_manager.get_side(), inode));
t_physical_tile_type_ptr grid_type_descriptor =
grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type(
t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
size_t src_grid_pin_width =
grid_type_descriptor->pin_width_offset[src_grid_pin_index];
size_t src_grid_pin_height =
@ -373,8 +373,8 @@ static int build_tile_module_port_and_nets_between_cb_and_pb(
VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module));
size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node);
t_physical_tile_type_ptr grid_type_descriptor =
grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type(
t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
size_t sink_grid_pin_width =
grid_type_descriptor->pin_width_offset[sink_grid_pin_index];
size_t sink_grid_pin_height =
@ -994,14 +994,13 @@ static int build_tile_module_ports_from_cb(
static int build_tile_port_and_nets_from_pb(
ModuleManager& module_manager, const ModuleId& tile_module,
const DeviceGrid& grids, const size_t& layer,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraphView& rr_graph, const vtr::Point<size_t>& pb_coord,
const std::vector<size_t>& pb_instances, const FabricTile& fabric_tile,
const FabricTileId& curr_fabric_tile_id, const size_t& ipb,
const bool& frame_view, const bool& verbose) {
const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph,
const vtr::Point<size_t>& pb_coord, const std::vector<size_t>& pb_instances,
const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id,
const size_t& ipb, const bool& frame_view, const bool& verbose) {
size_t pb_instance = pb_instances[ipb];
t_physical_tile_type_ptr phy_tile =
grids.get_physical_type(t_physical_tile_loc(pb_coord.x(), pb_coord.y(), layer));
t_physical_tile_type_ptr phy_tile = grids.get_physical_type(
t_physical_tile_loc(pb_coord.x(), pb_coord.y(), layer));
/* Empty type does not require a module */
if (is_empty_type(phy_tile)) {
return CMD_EXEC_SUCCESS;
@ -1123,8 +1122,8 @@ static int build_tile_port_and_nets_from_pb(
size_t num_fanout_in_tile =
module_manager.module_net_sinks(tile_module, curr_net).size();
RRNodeId rr_node = rr_graph.node_lookup().find_node(
layer, pb_coord.x() + iwidth, pb_coord.y() + iheight, OPIN, ipin,
side);
layer, pb_coord.x() + iwidth, pb_coord.y() + iheight, OPIN,
ipin, side);
size_t num_fanout_required =
rr_graph.node_out_edges(rr_node).size();
if (num_fanout_in_tile == num_fanout_required) {
@ -1200,9 +1199,9 @@ static int build_tile_module_ports_and_nets(
fabric_tile.sb_coordinates(fabric_tile_id)[isb];
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(sb_coord);
status_code = build_tile_module_port_and_nets_between_sb_and_pb(
module_manager, tile_module, grids, layer, vpr_device_annotation, device_rr_gsb,
rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id, pb_instances,
sb_instances, isb, true, frame_view, verbose);
module_manager, tile_module, grids, layer, vpr_device_annotation,
device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id,
pb_instances, sb_instances, isb, true, frame_view, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1248,9 +1247,9 @@ static int build_tile_module_ports_and_nets(
vtr::Point<size_t> pb_coord =
fabric_tile.pb_coordinates(fabric_tile_id)[ipb];
status_code = build_tile_port_and_nets_from_pb(
module_manager, tile_module, grids, layer, vpr_device_annotation, rr_graph_view,
pb_coord, pb_instances, fabric_tile, fabric_tile_id, ipb, frame_view,
verbose);
module_manager, tile_module, grids, layer, vpr_device_annotation,
rr_graph_view, pb_coord, pb_instances, fabric_tile, fabric_tile_id, ipb,
frame_view, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1308,8 +1307,8 @@ static int build_tile_module(
pb_instances; /* Keep tracking the instance id of each pb */
for (vtr::Point<size_t> grid_coord :
fabric_tile.pb_coordinates(fabric_tile_id)) {
t_physical_tile_type_ptr phy_tile =
grids.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
t_physical_tile_type_ptr phy_tile = grids.get_physical_type(
t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
VTR_LOGV(verbose, "Try to find pb at [%lu][%lu]\n", grid_coord.x(),
grid_coord.y());
/* Empty type does not require a module */
@ -1438,9 +1437,9 @@ static int build_tile_module(
/* Add module nets and ports */
status_code = build_tile_module_ports_and_nets(
module_manager, tile_module, grids, layer, vpr_device_annotation, device_rr_gsb,
rr_graph_view, fabric_tile, fabric_tile_id, pb_instances, cb_instances,
sb_instances, frame_view, verbose);
module_manager, tile_module, grids, layer, vpr_device_annotation,
device_rr_gsb, rr_graph_view, fabric_tile, fabric_tile_id, pb_instances,
cb_instances, sb_instances, frame_view, verbose);
/* Add global ports to the pb_module:
* This is a much easier job after adding sub modules (instances),

15
openfpga/src/fabric/build_top_module.cpp
View File

@ -76,17 +76,18 @@ int build_top_module(
if (fabric_tile.empty()) {
status = build_top_module_fine_grained_child_instances(
module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk,
rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph,
device_rr_gsb, tile_direct, arch_direct, config_protocol, sram_model,
frame_view, compact_routing_hierarchy, duplicate_grid_pin, fabric_key,
group_config_block);
rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation,
rr_graph, device_rr_gsb, tile_direct, arch_direct, config_protocol,
sram_model, frame_view, compact_routing_hierarchy, duplicate_grid_pin,
fabric_key, group_config_block);
} else {
/* TODO: Build the tile instances under the top module */
status = build_top_module_tile_child_instances(
module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk,
rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph,
device_rr_gsb, tile_direct, arch_direct, fabric_tile, config_protocol,
sram_model, fabric_key, group_config_block, frame_view, verbose);
rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation,
rr_graph, device_rr_gsb, tile_direct, arch_direct, fabric_tile,
config_protocol, sram_model, fabric_key, group_config_block, frame_view,
verbose);
}
if (status != CMD_EXEC_SUCCESS) {

43
openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp
View File

@ -109,7 +109,8 @@ static vtr::Matrix<size_t> add_top_module_grid_instances(
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(), layer);
t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(),
layer);
t_physical_tile_type_ptr phy_tile_type =
grids.get_physical_type(phy_tile_loc);
/* Bypass EMPTY grid */
@ -123,10 +124,8 @@ static vtr::Matrix<size_t> add_top_module_grid_instances(
* We just copy it here
*/
vtr::Point<size_t> root_grid_coord(
io_coordinate.x() -
grids.get_width_offset(phy_tile_loc),
io_coordinate.y() -
grids.get_height_offset(phy_tile_loc));
io_coordinate.x() - grids.get_width_offset(phy_tile_loc),
io_coordinate.y() - grids.get_height_offset(phy_tile_loc));
VTR_ASSERT(size_t(-1) !=
grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]);
grid_instance_ids[io_coordinate.x()][io_coordinate.y()] =
@ -150,7 +149,8 @@ static vtr::Matrix<size_t> add_top_module_grid_instances(
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
t_physical_tile_loc phy_tile_loc(ix, iy, layer);
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(phy_tile_loc);
t_physical_tile_type_ptr phy_tile_type =
grids.get_physical_type(phy_tile_loc);
/* Bypass EMPTY grid */
if (true == is_empty_type(phy_tile_type)) {
continue;
@ -400,8 +400,7 @@ static void add_top_module_io_children(
/* Now walk through the coordinates */
for (vtr::Point<size_t> coord : coords) {
t_physical_tile_loc phy_tile_loc(coord.x(), coord.y(), layer);
t_physical_tile_type_ptr grid_type =
grids.get_physical_type(phy_tile_loc);
t_physical_tile_type_ptr grid_type = grids.get_physical_type(phy_tile_loc);
/* Bypass EMPTY grid */
if (true == is_empty_type(grid_type)) {
continue;
@ -436,13 +435,13 @@ int build_top_module_fine_grained_child_instances(
const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const TileAnnotation& tile_annotation, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct,
const ArchDirect& arch_direct, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const bool& frame_view,
const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
const FabricKey& fabric_key, const bool& group_config_block) {
const size_t& layer, const TileAnnotation& tile_annotation,
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
const TileDirect& tile_direct, const ArchDirect& arch_direct,
const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
const bool& frame_view, const bool& compact_routing_hierarchy,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const bool& group_config_block) {
int status = CMD_EXEC_SUCCESS;
std::map<t_rr_type, vtr::Matrix<size_t>> cb_instance_ids;
@ -462,8 +461,8 @@ int build_top_module_fine_grained_child_instances(
compact_routing_hierarchy);
/* Update I/O children list */
add_top_module_io_children(module_manager, top_module, grids,
layer, grid_instance_ids);
add_top_module_io_children(module_manager, top_module, grids, layer,
grid_instance_ids);
/* Add nets when we need a complete fabric modeling,
* which is required by downstream functions
@ -486,9 +485,9 @@ int build_top_module_fine_grained_child_instances(
/* Add global ports from grid ports that are defined as global in tile
* annotation */
status = add_top_module_global_ports_from_grid_modules(
module_manager, top_module, tile_annotation, vpr_device_annotation, grids, layer,
rr_graph, device_rr_gsb, cb_instance_ids, grid_instance_ids, clk_ntwk,
rr_clock_lookup);
module_manager, top_module, tile_annotation, vpr_device_annotation, grids,
layer, rr_graph, device_rr_gsb, cb_instance_ids, grid_instance_ids,
clk_ntwk, rr_clock_lookup);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}
@ -506,8 +505,8 @@ int build_top_module_fine_grained_child_instances(
if (true == fabric_key.empty()) {
organize_top_module_memory_modules(
module_manager, top_module, circuit_lib, config_protocol, sram_model,
grids, layer, grid_instance_ids, device_rr_gsb, sb_instance_ids, cb_instance_ids,
compact_routing_hierarchy);
grids, layer, grid_instance_ids, device_rr_gsb, sb_instance_ids,
cb_instance_ids, compact_routing_hierarchy);
} else {
VTR_ASSERT_SAFE(false == fabric_key.empty());
/* Throw a fatal error when the fabric key has a mismatch in region

14
openfpga/src/fabric/build_top_module_child_fine_grained_instance.h
View File

@ -38,13 +38,13 @@ int build_top_module_fine_grained_child_instances(
const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const TileAnnotation& tile_annotation, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct,
const ArchDirect& arch_direct, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const bool& frame_view,
const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
const FabricKey& fabric_key, const bool& group_config_block);
const size_t& layer, const TileAnnotation& tile_annotation,
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
const TileDirect& tile_direct, const ArchDirect& arch_direct,
const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
const bool& frame_view, const bool& compact_routing_hierarchy,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const bool& group_config_block);
} /* end namespace openfpga */

60
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1272,9 +1272,9 @@ static int build_top_module_global_net_for_given_tile_module(
const TileGlobalPortId& tile_global_port,
const BasicPort& tile_port_to_connect,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Point<size_t>& grid_coordinate, const e_side& border_side,
const vtr::Matrix<size_t>& tile_instance_ids, const FabricTile& fabric_tile) {
const size_t& layer, const vtr::Point<size_t>& grid_coordinate,
const e_side& border_side, const vtr::Matrix<size_t>& tile_instance_ids,
const FabricTile& fabric_tile) {
/* Get the tile module and instance */
FabricTileId curr_fabric_tile_id =
fabric_tile.find_tile_by_pb_coordinate(grid_coordinate);
@ -1298,8 +1298,8 @@ static int build_top_module_global_net_for_given_tile_module(
fabric_tile.pb_coordinates(
unique_fabric_tile_id)[pb_idx_in_curr_fabric_tile];
t_physical_tile_type_ptr physical_tile =
grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
t_physical_tile_type_ptr physical_tile = grids.get_physical_type(
t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
/* Find the module name for this type of grid */
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
std::string grid_instance_name =
@ -1420,8 +1420,8 @@ static int build_top_module_global_net_from_tile_modules(
const ModulePortId& top_module_port, const TileAnnotation& tile_annotation,
const TileGlobalPortId& tile_global_port,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& tile_instance_ids, const FabricTile& fabric_tile) {
const size_t& layer, const vtr::Matrix<size_t>& tile_instance_ids,
const FabricTile& fabric_tile) {
int status = CMD_EXEC_SUCCESS;
std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates =
@ -1510,7 +1510,8 @@ static int build_top_module_global_net_from_tile_modules(
/* Walk through all the grids on the perimeter, which are I/O grids */
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(), layer);
t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(),
layer);
t_physical_tile_type_ptr phy_tile_type =
grids.get_physical_type(phy_tile_loc);
/* Bypass EMPTY grid */
@ -1519,10 +1520,8 @@ static int build_top_module_global_net_from_tile_modules(
}
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 <
grids.get_width_offset(phy_tile_loc)) ||
(0 <
grids.get_height_offset(phy_tile_loc))) {
if ((0 < grids.get_width_offset(phy_tile_loc)) ||
(0 < grids.get_height_offset(phy_tile_loc))) {
continue;
}
@ -1567,8 +1566,8 @@ static int add_top_module_global_ports_from_tile_modules(
ModuleManager& module_manager, const ModuleId& top_module,
const TileAnnotation& tile_annotation,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
const size_t& layer, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const vtr::Matrix<size_t>& tile_instance_ids, const FabricTile& fabric_tile,
const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup) {
int status = CMD_EXEC_SUCCESS;
@ -1626,8 +1625,8 @@ static int add_top_module_global_ports_from_tile_modules(
} else {
status = build_top_module_global_net_from_tile_modules(
module_manager, top_module, top_module_port, tile_annotation,
tile_global_port, vpr_device_annotation, grids, layer, tile_instance_ids,
fabric_tile);
tile_global_port, vpr_device_annotation, grids, layer,
tile_instance_ids, fabric_tile);
}
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
@ -1652,10 +1651,9 @@ static void add_module_nets_connect_tile_direct_connection(
ModuleManager& module_manager, const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& tile_instance_ids, const FabricTile& fabric_tile,
const TileDirect& tile_direct, const TileDirectId& tile_direct_id,
const ArchDirect& arch_direct) {
const size_t& layer, const vtr::Matrix<size_t>& tile_instance_ids,
const FabricTile& fabric_tile, const TileDirect& tile_direct,
const TileDirectId& tile_direct_id, const ArchDirect& arch_direct) {
vtr::Point<size_t> device_size(grids.width(), grids.height());
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
@ -1846,16 +1844,17 @@ static void add_top_module_nets_connect_tile_direct_connections(
ModuleManager& module_manager, const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& tile_instance_ids, const FabricTile& fabric_tile,
const TileDirect& tile_direct, const ArchDirect& arch_direct) {
const size_t& layer, const vtr::Matrix<size_t>& tile_instance_ids,
const FabricTile& fabric_tile, const TileDirect& tile_direct,
const ArchDirect& arch_direct) {
vtr::ScopedStartFinishTimer timer(
"Add module nets for inter-tile connections");
for (const TileDirectId& tile_direct_id : tile_direct.directs()) {
add_module_nets_connect_tile_direct_connection(
module_manager, top_module, circuit_lib, vpr_device_annotation, grids,
layer, tile_instance_ids, fabric_tile, tile_direct, tile_direct_id, arch_direct);
layer, tile_instance_ids, fabric_tile, tile_direct, tile_direct_id,
arch_direct);
}
}
@ -1869,13 +1868,12 @@ int build_top_module_tile_child_instances(
const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const TileAnnotation& tile_annotation, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct,
const ArchDirect& arch_direct, const FabricTile& fabric_tile,
const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
const FabricKey& fabric_key, const bool& group_config_block,
const bool& frame_view, const bool& verbose) {
const size_t& layer, const TileAnnotation& tile_annotation,
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
const TileDirect& tile_direct, const ArchDirect& arch_direct,
const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const FabricKey& fabric_key,
const bool& group_config_block, const bool& frame_view, const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
vtr::Matrix<size_t> tile_instance_ids;
status = add_top_module_tile_instances(module_manager, top_module,

13
openfpga/src/fabric/build_top_module_child_tile_instance.h
View File

@ -38,13 +38,12 @@ int build_top_module_tile_child_instances(
const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const TileAnnotation& tile_annotation, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct,
const ArchDirect& arch_direct, const FabricTile& fabric_tile,
const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
const FabricKey& fabric_key, const bool& group_config_block,
const bool& frame_view, const bool& verbose);
const size_t& layer, const TileAnnotation& tile_annotation,
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
const TileDirect& tile_direct, const ArchDirect& arch_direct,
const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const FabricKey& fabric_key,
const bool& group_config_block, const bool& frame_view, const bool& verbose);
} /* end namespace openfpga */

91
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -64,10 +64,9 @@ namespace openfpga {
static void add_top_module_nets_connect_grids_and_sb(
ModuleManager& module_manager, const ModuleId& top_module,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& grid_instance_ids, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const RRGSB& rr_gsb,
const vtr::Matrix<size_t>& sb_instance_ids,
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
const RRGSB& rr_gsb, const vtr::Matrix<size_t>& sb_instance_ids,
const bool& compact_routing_hierarchy) {
/* Skip those Switch blocks that do not exist */
if (false == rr_gsb.is_sb_exist()) {
@ -127,8 +126,8 @@ static void add_top_module_nets_connect_grids_and_sb(
size_t src_grid_pin_index = rr_graph.node_pin_num(
rr_gsb.get_opin_node(side_manager.get_side(), inode));
t_physical_tile_type_ptr grid_type_descriptor =
grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type(
t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
size_t src_grid_pin_width =
grid_type_descriptor->pin_width_offset[src_grid_pin_index];
size_t src_grid_pin_height =
@ -228,10 +227,9 @@ static void add_top_module_nets_connect_grids_and_sb(
static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(
ModuleManager& module_manager, const ModuleId& top_module,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& grid_instance_ids, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const RRGSB& rr_gsb,
const vtr::Matrix<size_t>& sb_instance_ids,
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
const RRGSB& rr_gsb, const vtr::Matrix<size_t>& sb_instance_ids,
const bool& compact_routing_hierarchy) {
/* Skip those Switch blocks that do not exist */
if (false == rr_gsb.is_sb_exist()) {
@ -302,7 +300,8 @@ static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(
size_t src_grid_pin_index = rr_graph.node_pin_num(
rr_gsb.get_opin_node(side_manager.get_side(), inode));
t_physical_tile_loc phy_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer);
t_physical_tile_loc phy_tile_loc(grid_coordinate.x(), grid_coordinate.y(),
layer);
t_physical_tile_type_ptr grid_type_descriptor =
grids.get_physical_type(phy_tile_loc);
size_t src_grid_pin_width =
@ -440,10 +439,10 @@ static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(
static void add_top_module_nets_connect_grids_and_cb(
ModuleManager& module_manager, const ModuleId& top_module,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& grid_instance_ids, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const RRGSB& rr_gsb,
const t_rr_type& cb_type, const vtr::Matrix<size_t>& cb_instance_ids,
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
const RRGSB& rr_gsb, const t_rr_type& cb_type,
const vtr::Matrix<size_t>& cb_instance_ids,
const bool& compact_routing_hierarchy) {
/* We could have two different coordinators, one is the instance, the other is
* the module */
@ -523,8 +522,8 @@ static void add_top_module_nets_connect_grids_and_cb(
grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()];
size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node);
t_physical_tile_type_ptr grid_type_descriptor =
grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type(
t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
size_t sink_grid_pin_width =
grid_type_descriptor->pin_width_offset[sink_grid_pin_index];
size_t sink_grid_pin_height =
@ -806,9 +805,9 @@ static void add_top_module_nets_connect_sb_and_cb(
void add_top_module_nets_connect_grids_and_gsbs(
ModuleManager& module_manager, const ModuleId& top_module,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& grid_instance_ids, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const vtr::Matrix<size_t>& sb_instance_ids,
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
const vtr::Matrix<size_t>& sb_instance_ids,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin) {
vtr::ScopedStartFinishTimer timer("Add module nets between grids and GSBs");
@ -823,25 +822,25 @@ void add_top_module_nets_connect_grids_and_gsbs(
/* Connect the grid pins of the GSB to adjacent grids */
if (false == duplicate_grid_pin) {
add_top_module_nets_connect_grids_and_sb(
module_manager, top_module, vpr_device_annotation, grids,
layer, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids,
module_manager, top_module, vpr_device_annotation, grids, layer,
grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids,
compact_routing_hierarchy);
} else {
VTR_ASSERT_SAFE(true == duplicate_grid_pin);
add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(
module_manager, top_module, vpr_device_annotation, grids,
layer, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids,
module_manager, top_module, vpr_device_annotation, grids, layer,
grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids,
compact_routing_hierarchy);
}
add_top_module_nets_connect_grids_and_cb(
module_manager, top_module, vpr_device_annotation, grids,
layer, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANX,
module_manager, top_module, vpr_device_annotation, grids, layer,
grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANX,
cb_instance_ids.at(CHANX), compact_routing_hierarchy);
add_top_module_nets_connect_grids_and_cb(
module_manager, top_module, vpr_device_annotation, grids,
layer, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANY,
module_manager, top_module, vpr_device_annotation, grids, layer,
grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANY,
cb_instance_ids.at(CHANY), compact_routing_hierarchy);
add_top_module_nets_connect_sb_and_cb(
@ -861,11 +860,10 @@ static int build_top_module_global_net_for_given_grid_module(
const TileGlobalPortId& tile_global_port,
const BasicPort& tile_port_to_connect,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Point<size_t>& grid_coordinate, const e_side& border_side,
const vtr::Matrix<size_t>& grid_instance_ids) {
t_physical_tile_type_ptr physical_tile =
grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
const size_t& layer, const vtr::Point<size_t>& grid_coordinate,
const e_side& border_side, const vtr::Matrix<size_t>& grid_instance_ids) {
t_physical_tile_type_ptr physical_tile = grids.get_physical_type(
t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
/* Find the module name for this type of grid */
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
std::string grid_module_name = generate_grid_block_module_name(
@ -988,8 +986,7 @@ static int build_top_module_global_net_from_grid_modules(
const ModulePortId& top_module_port, const TileAnnotation& tile_annotation,
const TileGlobalPortId& tile_global_port,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& grid_instance_ids) {
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids) {
int status = CMD_EXEC_SUCCESS;
std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates =
@ -1066,8 +1063,8 @@ static int build_top_module_global_net_from_grid_modules(
/* Create nets and finish connection build-up */
status = build_top_module_global_net_for_given_grid_module(
module_manager, top_module, top_module_port, tile_annotation,
tile_global_port, tile_port, vpr_device_annotation, grids,
layer, vtr::Point<size_t>(ix, iy), NUM_SIDES, grid_instance_ids);
tile_global_port, tile_port, vpr_device_annotation, grids, layer,
vtr::Point<size_t>(ix, iy), NUM_SIDES, grid_instance_ids);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}
@ -1077,7 +1074,8 @@ static int build_top_module_global_net_from_grid_modules(
/* Walk through all the grids on the perimeter, which are I/O grids */
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
t_physical_tile_loc tile_loc(io_coordinate.x(), io_coordinate.y(), layer);
t_physical_tile_loc tile_loc(io_coordinate.x(), io_coordinate.y(),
layer);
t_physical_tile_type_ptr phy_tile_type =
grids.get_physical_type(tile_loc);
/* Bypass EMPTY grid */
@ -1086,10 +1084,8 @@ static int build_top_module_global_net_from_grid_modules(
}
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 <
grids.get_width_offset(tile_loc)) ||
(0 <
grids.get_height_offset(tile_loc))) {
if ((0 < grids.get_width_offset(tile_loc)) ||
(0 < grids.get_height_offset(tile_loc))) {
continue;
}
@ -1114,8 +1110,8 @@ static int build_top_module_global_net_from_grid_modules(
/* Create nets and finish connection build-up */
status = build_top_module_global_net_for_given_grid_module(
module_manager, top_module, top_module_port, tile_annotation,
tile_global_port, tile_port, vpr_device_annotation, grids,
layer, io_coordinate, io_side, grid_instance_ids);
tile_global_port, tile_port, vpr_device_annotation, grids, layer,
io_coordinate, io_side, grid_instance_ids);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}
@ -1212,8 +1208,8 @@ int add_top_module_global_ports_from_grid_modules(
ModuleManager& module_manager, const ModuleId& top_module,
const TileAnnotation& tile_annotation,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
const size_t& layer, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const vtr::Matrix<size_t>& grid_instance_ids, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup) {
@ -1272,7 +1268,8 @@ int add_top_module_global_ports_from_grid_modules(
} else {
status = build_top_module_global_net_from_grid_modules(
module_manager, top_module, top_module_port, tile_annotation,
tile_global_port, vpr_device_annotation, grids, layer, grid_instance_ids);
tile_global_port, vpr_device_annotation, grids, layer,
grid_instance_ids);
}
if (status == CMD_EXEC_FATAL_ERROR) {
return status;

10
openfpga/src/fabric/build_top_module_connection.h
View File

@ -28,9 +28,9 @@ namespace openfpga {
void add_top_module_nets_connect_grids_and_gsbs(
ModuleManager& module_manager, const ModuleId& top_module,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& grid_instance_ids, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const vtr::Matrix<size_t>& sb_instance_ids,
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
const vtr::Matrix<size_t>& sb_instance_ids,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin);
@ -38,8 +38,8 @@ int add_top_module_global_ports_from_grid_modules(
ModuleManager& module_manager, const ModuleId& top_module,
const TileAnnotation& tile_annotation,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
const size_t& layer, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const vtr::Matrix<size_t>& grid_instance_ids, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup);

14
openfpga/src/fabric/build_top_module_directs.cpp
View File

@ -39,9 +39,9 @@ static void add_module_nets_tile_direct_connection(
ModuleManager& module_manager, const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& grid_instance_ids, const TileDirect& tile_direct,
const TileDirectId& tile_direct_id, const ArchDirect& arch_direct) {
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
const TileDirect& tile_direct, const TileDirectId& tile_direct_id,
const ArchDirect& arch_direct) {
vtr::Point<size_t> device_size(grids.width(), grids.height());
/* Find the module name of source clb */
@ -65,7 +65,8 @@ static void add_module_nets_tile_direct_connection(
/* Find the module name of sink clb */
vtr::Point<size_t> des_clb_coord =
tile_direct.to_tile_coordinate(tile_direct_id);
t_physical_tile_loc sink_grid_loc(des_clb_coord.x(), des_clb_coord.y(), layer);
t_physical_tile_loc sink_grid_loc(des_clb_coord.x(), des_clb_coord.y(),
layer);
t_physical_tile_type_ptr sink_grid_type =
grids.get_physical_type(sink_grid_loc);
e_side sink_grid_border_side =
@ -212,9 +213,8 @@ void add_top_module_nets_tile_direct_connections(
ModuleManager& module_manager, const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& grid_instance_ids, const TileDirect& tile_direct,
const ArchDirect& arch_direct) {
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
const TileDirect& tile_direct, const ArchDirect& arch_direct) {
vtr::ScopedStartFinishTimer timer(
"Add module nets for inter-tile connections");

5
openfpga/src/fabric/build_top_module_directs.h
View File

@ -26,9 +26,8 @@ void add_top_module_nets_tile_direct_connections(
ModuleManager& module_manager, const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& grid_instance_ids, const TileDirect& tile_direct,
const ArchDirect& arch_direct);
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
const TileDirect& tile_direct, const ArchDirect& arch_direct);
} /* end namespace openfpga */

12
openfpga/src/fabric/build_top_module_memory.cpp
View File

@ -136,10 +136,8 @@ static void organize_top_module_tile_memory_modules(
const vtr::Matrix<size_t>& grid_instance_ids,
const DeviceRRGSB& device_rr_gsb, const vtr::Matrix<size_t>& sb_instance_ids,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const bool& compact_routing_hierarchy,
const size_t& layer,
const vtr::Point<size_t>& tile_coord,
const e_side& tile_border_side) {
const bool& compact_routing_hierarchy, const size_t& layer,
const vtr::Point<size_t>& tile_coord, const e_side& tile_border_side) {
vtr::Point<size_t> gsb_coord_range = device_rr_gsb.get_gsb_range();
vtr::Point<size_t> gsb_coord(tile_coord.x(), tile_coord.y() - 1);
@ -194,8 +192,7 @@ static void organize_top_module_tile_memory_modules(
/* Find the module name for this type of grid */
t_physical_tile_loc phy_tile_loc(tile_coord.x(), tile_coord.y(), layer);
t_physical_tile_type_ptr grid_type =
grids.get_physical_type(phy_tile_loc);
t_physical_tile_type_ptr grid_type = grids.get_physical_type(phy_tile_loc);
/* Skip EMPTY Grid */
if (true == is_empty_type(grid_type)) {
@ -440,8 +437,7 @@ void organize_top_module_memory_modules(
ModuleManager& module_manager, const ModuleId& top_module,
const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& grid_instance_ids,
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
const DeviceRRGSB& device_rr_gsb, const vtr::Matrix<size_t>& sb_instance_ids,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const bool& compact_routing_hierarchy) {

3
openfpga/src/fabric/build_top_module_memory.h
View File

@ -32,8 +32,7 @@ void organize_top_module_memory_modules(
ModuleManager& module_manager, const ModuleId& top_module,
const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const DeviceGrid& grids,
const size_t& layer,
const vtr::Matrix<size_t>& grid_instance_ids,
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
const DeviceRRGSB& device_rr_gsb, const vtr::Matrix<size_t>& sb_instance_ids,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const bool& compact_routing_hierarchy);

8
openfpga/src/fabric/build_top_module_utils.cpp
View File

@ -29,8 +29,8 @@ std::string generate_grid_block_module_name_in_top_module(
/* Determine if the grid locates at the border */
vtr::Point<size_t> device_size(grids.width(), grids.height());
e_side border_side = find_grid_border_side(device_size, grid_coord);
t_physical_tile_type_ptr phy_tile_type =
grids.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), 0));
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(
t_physical_tile_loc(grid_coord.x(), grid_coord.y(), 0));
return generate_grid_block_module_name(
prefix, std::string(phy_tile_type->name), is_io_type(phy_tile_type),
@ -51,8 +51,8 @@ std::string generate_grid_module_port_name_in_top_module(
const size_t& sink_grid_pin_index,
const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph,
const RRNodeId& inode) {
t_physical_tile_type_ptr grid_type_descriptor =
grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), 0));
t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type(
t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), 0));
size_t sink_grid_pin_width =
grid_type_descriptor->pin_width_offset[sink_grid_pin_index];
size_t sink_grid_pin_height =

23
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -824,12 +824,11 @@ static void build_physical_block_bitstream(
const VprClusteringAnnotation& cluster_annotation,
const VprPlacementAnnotation& place_annotation,
const VprBitstreamAnnotation& bitstream_annotation, const DeviceGrid& grids,
const size_t& layer,
const vtr::Point<size_t>& grid_coord, const e_side& border_side,
const bool& verbose) {
const size_t& layer, const vtr::Point<size_t>& grid_coord,
const e_side& border_side, const bool& verbose) {
/* Create a block for the grid in bitstream manager */
t_physical_tile_type_ptr grid_type =
grids.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
t_physical_tile_type_ptr grid_type = grids.get_physical_type(
t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
/* Early exit if this parent module has no configurable child modules */
@ -951,8 +950,7 @@ void build_grid_bitstream(
BitstreamManager& bitstream_manager, const ConfigBlockId& top_block,
const ModuleManager& module_manager, const FabricTile& fabric_tile,
const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
const DeviceGrid& grids, const size_t& layer,
const AtomContext& atom_ctx,
const DeviceGrid& grids, const size_t& layer, const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprClusteringAnnotation& cluster_annotation,
const VprPlacementAnnotation& place_annotation,
@ -996,8 +994,8 @@ void build_grid_bitstream(
build_physical_block_bitstream(
bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile,
circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation,
place_annotation, bitstream_annotation, grids, layer, grid_coord, NUM_SIDES,
verbose);
place_annotation, bitstream_annotation, grids, layer, grid_coord,
NUM_SIDES, verbose);
}
}
VTR_LOGV(verbose, "Done\n");
@ -1011,7 +1009,8 @@ void build_grid_bitstream(
/* Add instances of I/O grids to top_module */
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(), layer);
t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(),
layer);
/* Bypass EMPTY grid */
if (true == is_empty_type(grids.get_physical_type(phy_tile_loc))) {
continue;
@ -1043,8 +1042,8 @@ void build_grid_bitstream(
build_physical_block_bitstream(
bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile,
circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation,
place_annotation, bitstream_annotation, grids, layer, io_coordinate, io_side,
verbose);
place_annotation, bitstream_annotation, grids, layer, io_coordinate,
io_side, verbose);
}
}
VTR_LOGV(verbose, "Done\n");

3
openfpga/src/fpga_bitstream/build_grid_bitstream.h
View File

@ -29,8 +29,7 @@ void build_grid_bitstream(
BitstreamManager& bitstream_manager, const ConfigBlockId& top_block,
const ModuleManager& module_manager, const FabricTile& fabric_tile,
const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
const DeviceGrid& grids, const size_t& layer,
const AtomContext& atom_ctx,
const DeviceGrid& grids, const size_t& layer, const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprClusteringAnnotation& cluster_annotation,
const VprPlacementAnnotation& place_annotation,

5
openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
View File

@ -602,10 +602,9 @@ static void print_analysis_sdc_disable_unused_grid(
const ModuleManager& module_manager, const e_side& border_side) {
/* Validate file stream */
valid_file_stream(fp);
t_physical_tile_loc phy_tile_loc(grid_coordinate.x(), grid_coordinate.y(), 0);
t_physical_tile_type_ptr grid_type =
grids.get_physical_type(phy_tile_loc);
t_physical_tile_type_ptr grid_type = grids.get_physical_type(phy_tile_loc);
/* Bypass conditions for grids :
* 1. EMPTY type, which is by nature unused
* 2. Offset > 0, which has already been processed when offset = 0

88
openfpga/src/tile_direct/build_tile_direct.cpp
View File

@ -168,7 +168,9 @@ static vtr::Point<size_t> find_grid_coordinate_given_type(
continue;
}
if (wanted_grid_type_name ==
std::string(grids.get_physical_type(t_physical_tile_loc(coord.x(), coord.y(), 0))->name)) {
std::string(
grids.get_physical_type(t_physical_tile_loc(coord.x(), coord.y(), 0))
->name)) {
return coord;
}
}
@ -421,8 +423,10 @@ static void build_inner_column_row_tile_direct(
for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> from_pins = find_physical_tile_pin_id(
from_phy_tile_type, device_ctx.grid.get_width_offset(from_phy_tile_loc),
device_ctx.grid.get_height_offset(from_phy_tile_loc), from_tile_port, from_side);
from_phy_tile_type,
device_ctx.grid.get_width_offset(from_phy_tile_loc),
device_ctx.grid.get_height_offset(from_phy_tile_loc), from_tile_port,
from_side);
/* If nothing found, we can continue */
if (0 == from_pins.size()) {
continue;
@ -438,7 +442,8 @@ static void build_inner_column_row_tile_direct(
continue;
}
t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(), to_grid_coord.y(), 0);
t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(),
to_grid_coord.y(), 0);
t_physical_tile_type_ptr to_phy_tile_type =
device_ctx.grid.get_physical_type(to_phy_tile_loc);
/* Bypass the grid that does not fit the from_tile name */
@ -452,13 +457,10 @@ static void build_inner_column_row_tile_direct(
*/
for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> to_pins =
find_physical_tile_pin_id(to_phy_tile_type,
device_ctx.grid.get_width_offset(
to_phy_tile_loc),
device_ctx.grid.get_height_offset(
to_phy_tile_loc),
to_tile_port, to_side);
std::vector<size_t> to_pins = find_physical_tile_pin_id(
to_phy_tile_type, device_ctx.grid.get_width_offset(to_phy_tile_loc),
device_ctx.grid.get_height_offset(to_phy_tile_loc), to_tile_port,
to_side);
/* If nothing found, we can continue */
if (0 == to_pins.size()) {
continue;
@ -595,15 +597,13 @@ static void build_inter_column_row_tile_direct(
*/
for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
t_physical_tile_loc from_phy_tile_loc(from_grid_coord.x(), from_grid_coord.y(), 0);
std::vector<size_t> from_pins =
find_physical_tile_pin_id(device_ctx.grid.get_physical_type(
from_phy_tile_loc),
device_ctx.grid.get_width_offset(
from_phy_tile_loc),
device_ctx.grid.get_height_offset(
from_phy_tile_loc),
from_tile_port, from_side);
t_physical_tile_loc from_phy_tile_loc(from_grid_coord.x(),
from_grid_coord.y(), 0);
std::vector<size_t> from_pins = find_physical_tile_pin_id(
device_ctx.grid.get_physical_type(from_phy_tile_loc),
device_ctx.grid.get_width_offset(from_phy_tile_loc),
device_ctx.grid.get_height_offset(from_phy_tile_loc), from_tile_port,
from_side);
/* If nothing found, we can continue */
if (0 == from_pins.size()) {
continue;
@ -627,15 +627,13 @@ static void build_inter_column_row_tile_direct(
*/
for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(), to_grid_coord.y(), 0);
std::vector<size_t> to_pins =
find_physical_tile_pin_id(device_ctx.grid.get_physical_type(
to_phy_tile_loc),
device_ctx.grid.get_width_offset(
to_phy_tile_loc),
device_ctx.grid.get_height_offset(
to_phy_tile_loc),
to_tile_port, to_side);
t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(),
to_grid_coord.y(), 0);
std::vector<size_t> to_pins = find_physical_tile_pin_id(
device_ctx.grid.get_physical_type(to_phy_tile_loc),
device_ctx.grid.get_width_offset(to_phy_tile_loc),
device_ctx.grid.get_height_offset(to_phy_tile_loc), to_tile_port,
to_side);
/* If nothing found, we can continue */
if (0 == to_pins.size()) {
continue;
@ -710,15 +708,13 @@ static void build_inter_column_row_tile_direct(
*/
for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
t_physical_tile_loc from_phy_tile_loc(from_grid_coord.x(), from_grid_coord.y(), 0);
std::vector<size_t> from_pins =
find_physical_tile_pin_id(device_ctx.grid.get_physical_type(
from_phy_tile_loc),
device_ctx.grid.get_width_offset(
from_phy_tile_loc),
device_ctx.grid.get_height_offset(
from_phy_tile_loc),
from_tile_port, from_side);
t_physical_tile_loc from_phy_tile_loc(from_grid_coord.x(),
from_grid_coord.y(), 0);
std::vector<size_t> from_pins = find_physical_tile_pin_id(
device_ctx.grid.get_physical_type(from_phy_tile_loc),
device_ctx.grid.get_width_offset(from_phy_tile_loc),
device_ctx.grid.get_height_offset(from_phy_tile_loc), from_tile_port,
from_side);
/* If nothing found, we can continue */
if (0 == from_pins.size()) {
continue;
@ -742,15 +738,13 @@ static void build_inter_column_row_tile_direct(
*/
for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(), to_grid_coord.y(), 0);
std::vector<size_t> to_pins =
find_physical_tile_pin_id(device_ctx.grid.get_physical_type(
to_phy_tile_loc),
device_ctx.grid.get_width_offset(
to_phy_tile_loc),
device_ctx.grid.get_height_offset(
to_phy_tile_loc),
to_tile_port, to_side);
t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(),
to_grid_coord.y(), 0);
std::vector<size_t> to_pins = find_physical_tile_pin_id(
device_ctx.grid.get_physical_type(to_phy_tile_loc),
device_ctx.grid.get_width_offset(to_phy_tile_loc),
device_ctx.grid.get_height_offset(to_phy_tile_loc), to_tile_port,
to_side);
/* If nothing found, we can continue */
if (0 == to_pins.size()) {
continue;

7
openfpga/src/utils/openfpga_physical_tile_utils.cpp
View File

@ -89,7 +89,8 @@ std::set<e_side> find_physical_io_tile_located_sides(
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
/* If located in center, we add a NUM_SIDES and finish */
if (physical_tile == grids.get_physical_type(t_physical_tile_loc(ix, iy, 0))) {
if (physical_tile ==
grids.get_physical_type(t_physical_tile_loc(ix, iy, 0))) {
io_sides.insert(NUM_SIDES);
center_io = true;
break;
@ -108,8 +109,8 @@ std::set<e_side> find_physical_io_tile_located_sides(
for (const e_side& fpga_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[fpga_side]) {
/* If located in center, we add a NUM_SIDES and finish */
if (physical_tile ==
grids.get_physical_type(t_physical_tile_loc(io_coordinate.x(), io_coordinate.y(), 0))) {
if (physical_tile == grids.get_physical_type(t_physical_tile_loc(
io_coordinate.x(), io_coordinate.y(), 0))) {
io_sides.insert(fpga_side);
break;
}