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[core] trying to fix the bug on instance naming so that bitstream generation can work

This commit is contained in:
tangxifan 2023-08-05 13:38:51 -07:00
parent 9a23dc7bff
commit f4d7ad2bd1
9 changed files with 158 additions and 173 deletions
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7
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -380,6 +380,8 @@ static void build_primitive_block_module(
VTR_ASSERT(module_manager.valid_module_id(physical_memory_module));
module_manager.set_logical2physical_configurable_child(
primitive_module, config_child_id, physical_memory_module);
module_manager.set_logical2physical_configurable_child_instance_name(
primitive_module, config_child_id, physical_memory_module_name);
}
}
@ -693,6 +695,11 @@ static void add_module_pb_graph_pin_interc(
mux_mem_module_name.c_str(), phy_mem_module_name.c_str());
module_manager.set_logical2physical_configurable_child(
pb_module, config_child_id, phy_mem_module);
std::string phy_mux_mem_instance_name = generate_pb_memory_instance_name(
GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string(""),
false);
module_manager.set_logical2physical_configurable_child_instance_name(
pb_module, config_child_id, phy_mux_mem_instance_name);
VTR_LOGV(verbose, "Now use a feedthrough memory for '%s'\n",
phy_mem_module_name.c_str());
}

55
openfpga/src/fabric/build_memory_modules.cpp
View File

@ -8,6 +8,7 @@
#include <algorithm>
#include <ctime>
#include <string>
#include <map>
#include "build_decoder_modules.h"
#include "circuit_library_utils.h"
@ -1310,6 +1311,7 @@ int build_memory_group_module(ModuleManager& module_manager,
const std::string& module_name,
const CircuitModelId& sram_model,
const std::vector<ModuleId>& child_modules,
const std::vector<std::string>& child_instance_names,
const size_t& num_mems, const bool& verbose) {
VTR_LOGV(verbose, "Building memory group module '%s'...\n",
module_name.c_str());
@ -1334,6 +1336,28 @@ int build_memory_group_module(ModuleManager& module_manager,
module_manager.add_port(mem_module, outb_port,
ModuleManager::MODULE_OUTPUT_PORT);
/* Identify the duplicated instance name: This mainly comes from the grid modules, which contains multi-instanced blocks. Therefore, we just count the duplicated instance names and name each of them with a unique index, e.g., mem_lut -> mem_lut_0, mem_lut_1 etc. The only exception is for the uinque instance name, we keep the original instance name */
std::vector<std::string> unique_child_instance_names;
unique_child_instance_names.reserve(child_instance_names.size());
std::map<std::string, size_t> unique_child_instance_name_count;
for (std::string curr_inst_name : child_instance_names) {
unique_child_instance_name_count[curr_inst_name]++;
}
std::map<std::string, size_t> unique_child_instance_name_scoreboard;
for (std::string curr_inst_name : child_instance_names) {
if (1 == unique_child_instance_name_count[curr_inst_name]) {
unique_child_instance_names.push_back(curr_inst_name);
unique_child_instance_name_scoreboard[curr_inst_name] = 1;
continue;
}
auto result = unique_child_instance_name_scoreboard.find(curr_inst_name);
if (result == unique_child_instance_name_scoreboard.end()) {
unique_child_instance_names.push_back(generate_instance_name(curr_inst_name, result->second));
unique_child_instance_name_scoreboard[curr_inst_name]++;
}
}
VTR_ASSERT(unique_child_instance_names.size() == child_instance_names.size());
/* Add nets between child module outputs and memory modules */
size_t mem_out_pin_start_index = 0;
size_t mem_outb_pin_start_index = 0;
@ -1342,6 +1366,7 @@ int build_memory_group_module(ModuleManager& module_manager,
size_t child_instance =
module_manager.num_instance(mem_module, child_module);
module_manager.add_child_module(mem_module, child_module, false);
module_manager.set_child_instance_name(mem_module, child_module, child_instance, unique_child_instance_names[ichild]);
module_manager.add_configurable_child(
mem_module, child_module, child_instance,
ModuleManager::e_config_child_type::UNIFIED);
@ -1453,9 +1478,10 @@ int add_physical_memory_module(ModuleManager& module_manager,
int status = CMD_EXEC_SUCCESS;
std::vector<ModuleId> required_phy_mem_modules;
std::vector<std::string> required_phy_mem_instance_names;
status = rec_find_physical_memory_children(
static_cast<const ModuleManager&>(module_manager), curr_module,
required_phy_mem_modules, verbose);
required_phy_mem_modules, required_phy_mem_instance_names, verbose);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1478,6 +1504,7 @@ int add_physical_memory_module(ModuleManager& module_manager,
status = build_memory_group_module(module_manager, decoder_lib, circuit_lib,
sram_orgz_type, phy_mem_module_name,
sram_model, required_phy_mem_modules,
required_phy_mem_instance_names,
module_num_config_bits, verbose);
}
if (status != CMD_EXEC_SUCCESS) {
@ -1573,32 +1600,6 @@ int add_physical_memory_module(ModuleManager& module_manager,
VTR_ASSERT(curr_mem_pin_index[CIRCUIT_MODEL_PORT_BLB] ==
module_num_config_bits);
/* TODO: Recursively update the logical configurable child with the physical
* memory module parent and its instance id */
std::map<ModuleId, size_t> logical_mem_child_inst_count;
status = rec_update_logical_memory_children_with_physical_mapping(
module_manager, curr_module, phy_mem_module, logical_mem_child_inst_count);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
/* Sanity check */
std::map<ModuleId, size_t> required_mem_child_inst_count;
for (ModuleId curr_child_module :
module_manager.child_modules(phy_mem_module)) {
if (logical_mem_child_inst_count[curr_child_module] !=
module_manager.num_instance(phy_mem_module, curr_child_module)) {
VTR_LOG_ERROR(
"Expect the %lu instances of module '%s' under its parent '%s' while "
"only updated %lu during logical-to-physical configurable child "
"mapping sync-up!\n",
module_manager.num_instance(phy_mem_module, curr_child_module),
module_manager.module_name(curr_child_module).c_str(),
module_manager.module_name(phy_mem_module).c_str(),
logical_mem_child_inst_count[curr_child_module]);
return CMD_EXEC_FATAL_ERROR;
}
}
return status;
}

1
openfpga/src/fabric/build_memory_modules.h
View File

@ -37,6 +37,7 @@ int build_memory_group_module(ModuleManager& module_manager,
const std::string& module_name,
const CircuitModelId& sram_model,
const std::vector<ModuleId>& child_modules,
const std::vector<std::string>& child_instance_names,
const size_t& num_mems, const bool& verbose);
int add_physical_memory_module(ModuleManager& module_manager,

12
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -258,6 +258,11 @@ static void build_switch_block_mux_module(
VTR_ASSERT(true == module_manager.valid_module_id(physical_mem_module));
module_manager.set_logical2physical_configurable_child(
sb_module, config_child_id, physical_mem_module);
std::string physical_mem_instance_name = generate_sb_memory_instance_name(
SWITCH_BLOCK_MEM_INSTANCE_PREFIX, chan_side, chan_node_id, std::string(""),
false);
module_manager.set_logical2physical_configurable_child_instance_name(
sb_module, config_child_id, physical_mem_instance_name);
}
}
@ -781,6 +786,13 @@ static void build_connection_block_mux_module(
VTR_ASSERT(true == module_manager.valid_module_id(physical_mem_module));
module_manager.set_logical2physical_configurable_child(
cb_module, config_child_id, physical_mem_module);
std::string physical_mem_instance_name = generate_cb_memory_instance_name(
CONNECTION_BLOCK_MEM_INSTANCE_PREFIX,
get_rr_graph_single_node_side(
rr_graph, rr_gsb.get_ipin_node(cb_ipin_side, ipin_index)),
ipin_index, std::string(""), false);
module_manager.set_logical2physical_configurable_child_instance_name(
cb_module, config_child_id, physical_mem_instance_name);
}
}

61
openfpga/src/fabric/module_manager.cpp
View File

@ -132,23 +132,13 @@ std::vector<ModuleId> ModuleManager::logical2physical_configurable_children(
}
/* Find all the instances of configurable child modules under a parent module */
std::vector<size_t>
ModuleManager::logical2physical_configurable_child_instances(
std::vector<std::string>
ModuleManager::logical2physical_configurable_child_instance_names(
const ModuleId& parent_module) const {
/* Validate the module_id */
VTR_ASSERT(valid_module_id(parent_module));
return logical2physical_configurable_child_instances_[parent_module];
}
/* Find all the instances of configurable child modules under a parent module */
std::vector<ModuleId>
ModuleManager::logical2physical_configurable_child_parents(
const ModuleId& parent_module) const {
/* Validate the module_id */
VTR_ASSERT(valid_module_id(parent_module));
return logical2physical_configurable_child_parents_[parent_module];
return logical2physical_configurable_child_instance_names_[parent_module];
}
/* Find all the configurable child modules under a parent module */
@ -741,8 +731,7 @@ ModuleId ModuleManager::add_module(const std::string& name) {
physical_configurable_child_coordinates_.emplace_back();
logical2physical_configurable_children_.emplace_back();
logical2physical_configurable_child_instances_.emplace_back();
logical2physical_configurable_child_parents_.emplace_back();
logical2physical_configurable_child_instance_names_.emplace_back();
config_region_ids_.emplace_back();
config_region_children_.emplace_back();
@ -1015,15 +1004,11 @@ void ModuleManager::add_configurable_child(const ModuleId& parent_module,
if (type == ModuleManager::e_config_child_type::UNIFIED) {
logical2physical_configurable_children_[parent_module].push_back(
child_module);
logical2physical_configurable_child_instances_[parent_module].push_back(
child_instance);
logical2physical_configurable_child_parents_[parent_module].push_back(
parent_module);
logical2physical_configurable_child_instance_names_[parent_module].emplace_back();
} else if (type == ModuleManager::e_config_child_type::LOGICAL) {
logical2physical_configurable_children_[parent_module].emplace_back();
logical2physical_configurable_child_instances_[parent_module]
logical2physical_configurable_child_instance_names_[parent_module]
.emplace_back();
logical2physical_configurable_child_parents_[parent_module].emplace_back();
}
}
@ -1040,32 +1025,18 @@ void ModuleManager::set_logical2physical_configurable_child(
physical_child_module;
}
void ModuleManager::set_logical2physical_configurable_child_instance(
void ModuleManager::set_logical2physical_configurable_child_instance_name(
const ModuleId& parent_module, const size_t& logical_child_id,
const size_t& physical_child_instance) {
const std::string& physical_child_instance_name) {
/* Sanity checks */
VTR_ASSERT(valid_module_id(parent_module));
VTR_ASSERT(logical_child_id <
num_configurable_children(
parent_module, ModuleManager::e_config_child_type::LOGICAL));
/* Create the pair */
logical2physical_configurable_child_instances_[parent_module]
logical2physical_configurable_child_instance_names_[parent_module]
[logical_child_id] =
physical_child_instance;
}
void ModuleManager::set_logical2physical_configurable_child_parent_module(
const ModuleId& parent_module, const size_t& logical_child_id,
const ModuleId& physical_child_parent_module) {
/* Sanity checks */
VTR_ASSERT(valid_module_id(parent_module));
VTR_ASSERT(logical_child_id <
num_configurable_children(
parent_module, ModuleManager::e_config_child_type::LOGICAL));
/* Create the pair */
logical2physical_configurable_child_parents_[parent_module]
[logical_child_id] =
physical_child_parent_module;
physical_child_instance_name;
}
void ModuleManager::reserve_configurable_child(
@ -1091,13 +1062,8 @@ void ModuleManager::reserve_configurable_child(
num_children);
}
if (num_children >
logical2physical_configurable_child_instances_[parent_module].size()) {
logical2physical_configurable_child_instances_[parent_module].reserve(
num_children);
}
if (num_children >
logical2physical_configurable_child_parents_[parent_module].size()) {
logical2physical_configurable_child_parents_[parent_module].reserve(
logical2physical_configurable_child_instance_names_[parent_module].size()) {
logical2physical_configurable_child_instance_names_[parent_module].reserve(
num_children);
}
}
@ -1499,8 +1465,7 @@ void ModuleManager::clear_configurable_children(const ModuleId& parent_module) {
physical_configurable_child_coordinates_[parent_module].clear();
logical2physical_configurable_children_[parent_module].clear();
logical2physical_configurable_child_instances_[parent_module].clear();
logical2physical_configurable_child_parents_[parent_module].clear();
logical2physical_configurable_child_instance_names_[parent_module].clear();
}
void ModuleManager::clear_config_region(const ModuleId& parent_module) {

32
openfpga/src/fabric/module_manager.h
View File

@ -192,19 +192,16 @@ class ModuleManager {
std::vector<vtr::Point<int>> configurable_child_coordinates(
const ModuleId& parent_module, const e_config_child_type& type) const;
/* Find all the configurable child modules under a parent module */
std::vector<ModuleId> logical2physical_configurable_children(
const ModuleId& parent_module) const;
/* Find all the instances of configurable child modules under a parent module
*/
std::vector<size_t> logical2physical_configurable_child_instances(
const ModuleId& parent_module) const;
/* Find all the parent modules of physical configurable child modules under a
* parent module Note that a physical configurable child module may be at
/* Find all the configurable child modules under a parent module
* Note that a physical configurable child module may be at
* another module; Only the logical child module is under the current parent
* module
*/
std::vector<ModuleId> logical2physical_configurable_child_parents(
std::vector<ModuleId> logical2physical_configurable_children(
const ModuleId& parent_module) const;
/* Find all the instance names of configurable child modules under a parent module
*/
std::vector<std::string> logical2physical_configurable_child_instance_names(
const ModuleId& parent_module) const;
/* Find all the I/O child modules under a parent module */
@ -405,12 +402,9 @@ class ModuleManager {
const ModuleId& physical_child_module);
/** @brief Create a pair of mapping from a logical configurable child to a
* physical configurable child */
void set_logical2physical_configurable_child_instance(
void set_logical2physical_configurable_child_instance_name(
const ModuleId& parent_module, const size_t& logical_child_id,
const size_t& physical_child_instance);
void set_logical2physical_configurable_child_parent_module(
const ModuleId& parent_module, const size_t& logical_child_id,
const ModuleId& physical_child_parent_module);
const std::string& physical_child_instance_name);
/* Reserved a number of configurable children for memory efficiency */
void reserve_configurable_child(const ModuleId& module,
const size_t& num_children,
@ -584,14 +578,10 @@ class ModuleManager {
vtr::vector<ModuleId, std::vector<ModuleId>>
logical2physical_configurable_children_; /* Child modules with configurable
memory bits that this module contain */
vtr::vector<ModuleId, std::vector<size_t>>
logical2physical_configurable_child_instances_; /* Instances of child
vtr::vector<ModuleId, std::vector<std::string>>
logical2physical_configurable_child_instance_names_; /* Instances of child
modules with configurable memory bits that
this module contain */
vtr::vector<ModuleId, std::vector<ModuleId>>
logical2physical_configurable_child_parents_; /* Parent modules with
configurable memory bits that this module contain
*/
vtr::vector<ModuleId, std::vector<ModuleId>>
physical_configurable_children_; /* Child modules with configurable memory

82
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -50,6 +50,7 @@ static std::vector<bool> generate_mode_select_bitstream(
*******************************************************************/
static void build_primitive_bitstream(
BitstreamManager& bitstream_manager,
std::map<std::string, size_t>& grouped_mem_inst_scoreboard,
const ConfigBlockId& parent_configurable_block,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& device_annotation, const PhysicalPb& physical_pb,
@ -132,6 +133,21 @@ static void build_primitive_bitstream(
mode_select_bitstream.size() ==
module_manager.module_port(mem_module, mem_out_port_id).get_width());
/* If there is a feedthrough module, we should consider the scoreboard */
std::string feedthru_mem_block_name = generate_memory_module_name(
circuit_lib, primitive_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX), true);
ModuleId feedthru_mem_module = module_manager.find_module(feedthru_mem_block_name);
if (module_manager.valid_module_id(feedthru_mem_module)) {
auto result = grouped_mem_inst_scoreboard.find(mem_block_name);
if (result == grouped_mem_inst_scoreboard.end()) {
/* Update scoreboard */
grouped_mem_inst_scoreboard[mem_block_name] = 1;
} else {
mem_block_name = generate_instance_name(mem_block_name, result->second);
grouped_mem_inst_scoreboard[mem_block_name]++;
}
}
/* Create a block for the bitstream which corresponds to the memory module
* associated to the LUT */
ConfigBlockId mem_block = bitstream_manager.add_block(mem_block_name);
@ -159,6 +175,7 @@ static void build_primitive_bitstream(
*******************************************************************/
static void build_physical_block_pin_interc_bitstream(
BitstreamManager& bitstream_manager,
std::map<std::string, size_t>& grouped_mem_inst_scoreboard,
const ConfigBlockId& parent_configurable_block,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
@ -264,9 +281,6 @@ static void build_physical_block_pin_interc_bitstream(
* physical_block */
std::string mem_block_name = generate_pb_memory_instance_name(
GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string(""));
ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name);
bitstream_manager.add_child_block(parent_configurable_block,
mux_mem_block);
/* Find the module in module manager and ensure the bitstream size
* matches! */
@ -281,6 +295,24 @@ static void build_physical_block_pin_interc_bitstream(
module_manager.module_port(mux_mem_module, mux_mem_out_port_id)
.get_width());
/* If there is a feedthrough module, we should consider the scoreboard */
std::string feedthru_mem_block_name = generate_pb_memory_instance_name(
GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string(""), true);
ModuleId feedthru_mem_module = module_manager.find_module(feedthru_mem_block_name);
if (module_manager.valid_module_id(feedthru_mem_module)) {
auto result = grouped_mem_inst_scoreboard.find(mem_block_name);
if (result == grouped_mem_inst_scoreboard.end()) {
/* Update scoreboard */
grouped_mem_inst_scoreboard[mem_block_name] = 1;
} else {
mem_block_name = generate_instance_name(mem_block_name, result->second);
grouped_mem_inst_scoreboard[mem_block_name]++;
}
}
ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name);
bitstream_manager.add_child_block(parent_configurable_block,
mux_mem_block);
VTR_LOGV(verbose, "Added %lu bits to '%s' under '%s'\n",
mux_bitstream.size(),
bitstream_manager.block_name(mux_mem_block).c_str(),
@ -335,6 +367,7 @@ static void build_physical_block_pin_interc_bitstream(
*******************************************************************/
static void build_physical_block_interc_port_bitstream(
BitstreamManager& bitstream_manager,
std::map<std::string, size_t>& grouped_mem_inst_scoreboard,
const ConfigBlockId& parent_configurable_block,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
@ -350,7 +383,7 @@ static void build_physical_block_interc_port_bitstream(
for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport];
++ipin) {
build_physical_block_pin_interc_bitstream(
bitstream_manager, parent_configurable_block, module_manager,
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, physical_pb,
&(physical_pb_graph_node->input_pins[iport][ipin]), physical_mode,
@ -364,7 +397,7 @@ static void build_physical_block_interc_port_bitstream(
for (int ipin = 0;
ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) {
build_physical_block_pin_interc_bitstream(
bitstream_manager, parent_configurable_block, module_manager,
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, physical_pb,
&(physical_pb_graph_node->output_pins[iport][ipin]), physical_mode,
@ -378,7 +411,7 @@ static void build_physical_block_interc_port_bitstream(
for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport];
++ipin) {
build_physical_block_pin_interc_bitstream(
bitstream_manager, parent_configurable_block, module_manager,
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, physical_pb,
&(physical_pb_graph_node->clock_pins[iport][ipin]), physical_mode,
@ -398,6 +431,7 @@ static void build_physical_block_interc_port_bitstream(
*******************************************************************/
static void build_physical_block_interc_bitstream(
BitstreamManager& bitstream_manager,
std::map<std::string, size_t>& grouped_mem_inst_scoreboard,
const ConfigBlockId& parent_configurable_block,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
@ -422,7 +456,7 @@ static void build_physical_block_interc_bitstream(
* Note: it is not applied to primitive pb_type!
*/
build_physical_block_interc_port_bitstream(
bitstream_manager, parent_configurable_block, module_manager, circuit_lib,
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, module_manager, circuit_lib,
mux_lib, atom_ctx, device_annotation, bitstream_annotation,
physical_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_OUTPUT, physical_mode,
verbose);
@ -445,13 +479,13 @@ static void build_physical_block_interc_bitstream(
/* For each child_pb_graph_node input pins*/
build_physical_block_interc_port_bitstream(
bitstream_manager, parent_configurable_block, module_manager,
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation,
child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_INPUT, physical_mode,
verbose);
/* For clock pins, we should do the same work */
build_physical_block_interc_port_bitstream(
bitstream_manager, parent_configurable_block, module_manager,
bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation,
child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_CLOCK, physical_mode,
verbose);
@ -464,6 +498,7 @@ static void build_physical_block_interc_bitstream(
* This function supports both single-output and fracturable LUTs
*******************************************************************/
static void build_lut_bitstream(BitstreamManager& bitstream_manager,
std::map<std::string, size_t>& grouped_mem_inst_scoreboard,
const ConfigBlockId& parent_configurable_block,
const VprDeviceAnnotation& device_annotation,
const ModuleManager& module_manager,
@ -612,6 +647,21 @@ static void build_lut_bitstream(BitstreamManager& bitstream_manager,
lut_bitstream.size() ==
module_manager.module_port(mem_module, mem_out_port_id).get_width());
/* If there is a feedthrough module, we should consider the scoreboard */
std::string feedthru_mem_block_name = generate_memory_module_name(
circuit_lib, lut_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX), true);
ModuleId feedthru_mem_module = module_manager.find_module(feedthru_mem_block_name);
if (module_manager.valid_module_id(feedthru_mem_module)) {
auto result = grouped_mem_inst_scoreboard.find(mem_block_name);
if (result == grouped_mem_inst_scoreboard.end()) {
/* Update scoreboard */
grouped_mem_inst_scoreboard[mem_block_name] = 1;
} else {
mem_block_name = generate_instance_name(mem_block_name, result->second);
grouped_mem_inst_scoreboard[mem_block_name]++;
}
}
/* Create a block for the bitstream which corresponds to the memory module
* associated to the LUT */
ConfigBlockId mem_block = bitstream_manager.add_block(mem_block_name);
@ -638,6 +688,7 @@ static void build_lut_bitstream(BitstreamManager& bitstream_manager,
*******************************************************************/
static void rec_build_physical_block_bitstream(
BitstreamManager& bitstream_manager,
std::map<std::string, size_t>& grouped_mem_inst_scoreboard,
const ConfigBlockId& parent_configurable_block,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
@ -699,7 +750,7 @@ static void rec_build_physical_block_bitstream(
}
/* Go recursively */
rec_build_physical_block_bitstream(
bitstream_manager, pb_configurable_block, module_manager, circuit_lib,
bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block, module_manager, circuit_lib,
mux_lib, atom_ctx, device_annotation, bitstream_annotation,
border_side, physical_pb, child_pb,
&(physical_pb_graph_node
@ -719,7 +770,7 @@ static void rec_build_physical_block_bitstream(
/* Special case for LUT !!!
* Mapped logical block information is stored in child_pbs of this pb!!!
*/
build_lut_bitstream(bitstream_manager, pb_configurable_block,
build_lut_bitstream(bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block,
device_annotation, module_manager, circuit_lib,
mux_lib, physical_pb, pb_id, physical_pb_type,
verbose);
@ -729,7 +780,7 @@ static void rec_build_physical_block_bitstream(
case CIRCUIT_MODEL_IOPAD:
/* For other types of blocks, we can apply a generic therapy */
build_primitive_bitstream(
bitstream_manager, pb_configurable_block, module_manager, circuit_lib,
bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block, module_manager, circuit_lib,
device_annotation, physical_pb, pb_id, physical_pb_type, verbose);
break;
default:
@ -744,7 +795,7 @@ static void rec_build_physical_block_bitstream(
/* Generate the bitstream for the interconnection in this physical block */
build_physical_block_interc_bitstream(
bitstream_manager, pb_configurable_block, module_manager, circuit_lib,
bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block, module_manager, circuit_lib,
mux_lib, atom_ctx, device_annotation, bitstream_annotation,
physical_pb_graph_node, physical_pb, physical_mode, verbose);
}
@ -838,6 +889,7 @@ static void build_physical_block_bitstream(
* If you need different equivalent sites, you can always define
* it as a mode under a <pb_type>
*/
std::map<std::string, size_t> grouped_mem_inst_scoreboard;
for (size_t z = 0; z < place_annotation.grid_blocks(grid_coord).size(); ++z) {
int sub_tile_index =
device_annotation.physical_tile_z_to_subtile_index(grid_type, z);
@ -854,7 +906,7 @@ static void build_physical_block_bitstream(
place_annotation.grid_blocks(grid_coord)[z]) {
/* Recursively traverse the pb_graph and generate bitstream */
rec_build_physical_block_bitstream(
bitstream_manager, grid_configurable_block, module_manager,
bitstream_manager, grouped_mem_inst_scoreboard, grid_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, border_side, PhysicalPb(),
PhysicalPbId::INVALID(), lb_type->pb_graph_head, z, verbose);
@ -869,7 +921,7 @@ static void build_physical_block_bitstream(
/* Recursively traverse the pb_graph and generate bitstream */
rec_build_physical_block_bitstream(
bitstream_manager, grid_configurable_block, module_manager,
bitstream_manager, grouped_mem_inst_scoreboard, grid_configurable_block, module_manager,
circuit_lib, mux_lib, atom_ctx, device_annotation,
bitstream_annotation, border_side, phy_pb, top_pb_id, pb_graph_head,
z, verbose);

62
openfpga/src/utils/memory_utils.cpp
View File

@ -499,7 +499,9 @@ size_t estimate_num_configurable_children_to_skip_by_config_protocol(
int rec_find_physical_memory_children(
const ModuleManager& module_manager, const ModuleId& curr_module,
std::vector<ModuleId>& physical_memory_children, const bool& verbose) {
std::vector<ModuleId>& physical_memory_children,
std::vector<std::string>& physical_memory_instance_names,
const bool& verbose) {
if (module_manager
.configurable_children(curr_module,
ModuleManager::e_config_child_type::LOGICAL)
@ -522,59 +524,23 @@ int rec_find_physical_memory_children(
physical_memory_children.push_back(
module_manager.logical2physical_configurable_children(
curr_module)[ichild]);
physical_memory_instance_names.push_back(
module_manager.logical2physical_configurable_instance_names(
curr_module)[ichild]);
VTR_LOGV(
verbose, "Collecting physical memory module '%s'...\n",
verbose, "Collecting physical memory module '%s' with an instance name '%s'...\n",
module_manager
.module_name(module_manager.logical2physical_configurable_children(
curr_module)[ichild])
.c_str());
.c_str(),
module_manager
.module_name(module_manager.logical2physical_configurable_instance_names(
curr_module)[ichild])
.c_str(),
);
} else {
rec_find_physical_memory_children(module_manager, logical_child,
physical_memory_children, verbose);
}
}
return CMD_EXEC_SUCCESS;
}
int rec_update_logical_memory_children_with_physical_mapping(
ModuleManager& module_manager, const ModuleId& curr_module,
const ModuleId& phy_mem_module,
std::map<ModuleId, size_t>& logical_mem_child_inst_count) {
if (module_manager
.configurable_children(curr_module,
ModuleManager::e_config_child_type::LOGICAL)
.empty()) {
return CMD_EXEC_SUCCESS;
}
for (size_t ichild = 0;
ichild < module_manager
.configurable_children(
curr_module, ModuleManager::e_config_child_type::LOGICAL)
.size();
++ichild) {
ModuleId logical_child = module_manager.configurable_children(
curr_module, ModuleManager::e_config_child_type::LOGICAL)[ichild];
if (module_manager
.configurable_children(logical_child,
ModuleManager::e_config_child_type::LOGICAL)
.empty()) {
/* This is a leaf node, update its physical information */
ModuleId phy_mem_submodule =
module_manager.logical2physical_configurable_children(
curr_module)[ichild];
auto result = logical_mem_child_inst_count.find(phy_mem_submodule);
if (result == logical_mem_child_inst_count.end()) {
logical_mem_child_inst_count[phy_mem_submodule] = 0;
}
module_manager.set_logical2physical_configurable_child_instance(
curr_module, ichild, logical_mem_child_inst_count[phy_mem_submodule]);
module_manager.set_logical2physical_configurable_child_parent_module(
curr_module, ichild, phy_mem_module);
logical_mem_child_inst_count[phy_mem_submodule]++;
} else {
rec_update_logical_memory_children_with_physical_mapping(
module_manager, logical_child, phy_mem_module,
logical_mem_child_inst_count);
physical_memory_children, physical_memory_instance_names, verbose);
}
}
return CMD_EXEC_SUCCESS;

19
openfpga/src/utils/memory_utils.h
View File

@ -5,6 +5,7 @@
* Include header files that are required by function declaration
*******************************************************************/
#include <vector>
#include <string>
#include "circuit_types.h"
#include "config_protocol.h"
@ -61,20 +62,10 @@ size_t estimate_num_configurable_children_to_skip_by_config_protocol(
*/
int rec_find_physical_memory_children(
const ModuleManager& module_manager, const ModuleId& curr_module,
std::vector<ModuleId>& physical_memory_children, const bool& verbose);
std::vector<ModuleId>& physical_memory_children,
std::vector<std::string>& physical_memory_instance_names,
const bool& verbose);
/**
* @brief Update all the mappings between logical-to-physical memory children
* with a given root module This function will walk through the module tree in a
* recursive way until reaching the leaf node (which require configurable
* memories) Keep a scoreboard of instance number for checking. Note that when
* calling this the function, use an empty scoreboard!
*/
int rec_update_logical_memory_children_with_physical_mapping(
ModuleManager& module_manager, const ModuleId& curr_module,
const ModuleId& phy_mem_module,
std::map<ModuleId, size_t>& logical_mem_child_inst_count);
} /* end namespace openfpga */
/* end namespace openfpga */
#endif