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[core] code format

This commit is contained in:
tangxifan 2023-09-20 20:37:27 -07:00
parent 1ef38b6a64
commit ca3617a029
2 changed files with 8 additions and 8 deletions
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12
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -203,7 +203,8 @@ static int build_tile_module_port_and_nets_between_sb_and_pb(
std::string temp_sb_module_name = generate_switch_block_module_name(
fabric_tile.sb_coordinates(fabric_tile_id)[isb]);
if (name_module_using_index) {
temp_sb_module_name = generate_switch_block_module_name_using_index(isb);
temp_sb_module_name =
generate_switch_block_module_name_using_index(isb);
}
src_grid_port.set_name(generate_tile_module_port_name(
temp_sb_module_name, sink_sb_port.get_name()));
@ -434,8 +435,7 @@ static int build_tile_module_port_and_nets_between_cb_and_pb(
cb_type, cb_inst_rr_gsb.get_cb_coordinate(cb_type));
if (name_module_using_index) {
cb_instance_name_in_tile =
generate_connection_block_module_name_using_index(
cb_type, icb);
generate_connection_block_module_name_using_index(cb_type, icb);
}
src_cb_port.set_name(generate_tile_module_port_name(
cb_instance_name_in_tile, src_cb_port.get_name()));
@ -700,7 +700,8 @@ static int build_tile_module_port_and_nets_between_sb_and_cb(
std::string temp_sb_module_name = generate_switch_block_module_name(
fabric_tile.sb_coordinates(fabric_tile_id)[isb]);
if (name_module_using_index) {
temp_sb_module_name = generate_switch_block_module_name_using_index(isb);
temp_sb_module_name =
generate_switch_block_module_name_using_index(isb);
}
chan_input_port.set_name(generate_tile_module_port_name(
temp_sb_module_name, chan_input_port.get_name()));
@ -920,8 +921,7 @@ static int build_tile_module_ports_from_cb(
cb_type, unique_rr_gsb.get_cb_coordinate(cb_type));
if (name_module_using_index) {
cb_instance_name_in_tile =
generate_connection_block_module_name_using_index(
cb_type, icb);
generate_connection_block_module_name_using_index(cb_type, icb);
}
vtr::Point<size_t> tile_coord =
fabric_tile.tile_coordinate(curr_fabric_tile_id);

4
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -853,8 +853,8 @@ static int build_top_module_tile_nets_between_sb_and_cb(
cb_type, unique_cb_rr_gsb.get_cb_coordinate(cb_type));
if (name_module_using_index) {
cb_instance_name_in_unique_tile =
generate_connection_block_module_name_using_index(
cb_type, cb_idx_in_cb_tile);
generate_connection_block_module_name_using_index(cb_type,
cb_idx_in_cb_tile);
}
std::string cb_tile_module_name =
generate_tile_module_name(cb_unique_tile_coord);