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[core] code format

This commit is contained in:
tangxifan 2023-08-03 17:34:25 -07:00
parent f4cbc95053
commit d3895c3dc0
31 changed files with 1052 additions and 591 deletions
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6
libs/libarchopenfpga/src/circuit_types.h
View File

@ -134,7 +134,8 @@ constexpr std::array<const char*, NUM_CIRCUIT_MODEL_DELAY_TYPES>
* - configurable memories are organized and accessed by quicklogic memory bank
* - configurable memories are organized and accessed by memory bank
* - configurable memories are organized and accessed by frames
* - configurable memories are organized and accessed by feedthrough. Currently, this is only for internal use only
* - configurable memories are organized and accessed by feedthrough. Currently,
* this is only for internal use only
*/
enum e_config_protocol_type {
CONFIG_MEM_STANDALONE,
@ -148,6 +149,7 @@ enum e_config_protocol_type {
constexpr std::array<const char*, NUM_CONFIG_PROTOCOL_TYPES>
CONFIG_PROTOCOL_TYPE_STRING = {{"standalone", "scan_chain", "memory_bank",
"ql_memory_bank", "frame_based", "feedthrough"}};
"ql_memory_bank", "frame_based",
"feedthrough"}};
#endif

6
libs/libopenfpgautil/src/openfpga_reserved_words.h
View File

@ -42,8 +42,10 @@ constexpr const char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_";
constexpr const char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_";
constexpr const char* MEMORY_MODULE_POSTFIX = "_mem";
constexpr const char* MEMORY_FEEDTHROUGH_MODULE_POSTFIX = "_feedthrough_mem";
constexpr const char* MEMORY_FEEDTHROUGH_DATA_IN_PORT_NAME = "feedthrough_mem_in";
constexpr const char* MEMORY_FEEDTHROUGH_DATA_IN_INV_PORT_NAME = "feedthrough_mem_inb";
constexpr const char* MEMORY_FEEDTHROUGH_DATA_IN_PORT_NAME =
"feedthrough_mem_in";
constexpr const char* MEMORY_FEEDTHROUGH_DATA_IN_INV_PORT_NAME =
"feedthrough_mem_inb";
constexpr const char* MEMORY_BL_PORT_NAME = "bl";
constexpr const char* MEMORY_WL_PORT_NAME = "wl";
constexpr const char* MEMORY_WLR_PORT_NAME = "wlr";

26
openfpga/src/base/openfpga_naming.cpp
View File

@ -234,7 +234,7 @@ std::string generate_memory_module_name(const CircuitLibrary& circuit_lib,
const bool& feedthrough_memory) {
std::string mid_name;
if (feedthrough_memory) {
mid_name = "feedthrough_";
mid_name = "feedthrough_";
}
return std::string(circuit_lib.model_name(circuit_model) + "_" + mid_name +
circuit_lib.model_name(sram_model) + postfix);
@ -531,8 +531,10 @@ std::string generate_tile_module_netlist_name(const std::string& block_name,
/*********************************************************************
* Generate the module name of a physical memory module
**********************************************************************/
std::string generate_physical_memory_module_name(const std::string& prefix, const size_t& mem_size) {
return prefix + std::string("_config_group_mem_size") + std::to_string(mem_size);
std::string generate_physical_memory_module_name(const std::string& prefix,
const size_t& mem_size) {
return prefix + std::string("_config_group_mem_size") +
std::to_string(mem_size);
}
/*********************************************************************
@ -748,17 +750,17 @@ std::string generate_sram_port_name(
switch (sram_orgz_type) {
case CONFIG_MEM_FEEDTHROUGH:
/* Two types of ports are available:
/* Two types of ports are available:
* (1) BL indicates the mem port
* (2) BLB indicates the inverted mem port
*
* mem mem_inv
* [0] [0]
* | |
* v v
* +----------------+
* | Virtual Mem |
* +----------------+
* mem mem_inv
* [0] [0]
* | |
* v v
* +----------------+
* | Virtual Mem |
* +----------------+
*/
if (CIRCUIT_MODEL_PORT_BL == port_type) {
port_name = std::string(MEMORY_FEEDTHROUGH_DATA_IN_PORT_NAME);
@ -1202,7 +1204,7 @@ std::string generate_pb_memory_instance_name(const std::string& prefix,
t_pb_graph_pin* pb_graph_pin,
const std::string& postfix,
const bool& feedthrough_memory) {
std::string mid_name = feedthrough_memory ? "virtual_" : "";
std::string mid_name = feedthrough_memory ? "virtual_" : "";
std::string instance_name(mid_name + prefix);
instance_name += std::string(pb_graph_pin->parent_node->pb_type->name);

26
openfpga/src/base/openfpga_naming.h
View File

@ -119,38 +119,34 @@ std::string generate_tile_module_port_name(const std::string& prefix,
std::string generate_tile_module_netlist_name(const std::string& block_name,
const std::string& postfix);
std::string generate_physical_memory_module_name(const std::string& prefix, const size_t& mem_size);
std::string generate_physical_memory_module_name(const std::string& prefix,
const size_t& mem_size);
std::string generate_sb_mux_instance_name(const std::string& prefix,
const e_side& sb_side,
const size_t& track_id,
const std::string& postfix);
std::string generate_sb_memory_instance_name(const std::string& prefix,
const e_side& sb_side,
const size_t& track_id,
const std::string& postfix,
const bool& feedthrough_memory = false);
std::string generate_sb_memory_instance_name(
const std::string& prefix, const e_side& sb_side, const size_t& track_id,
const std::string& postfix, const bool& feedthrough_memory = false);
std::string generate_cb_mux_instance_name(const std::string& prefix,
const e_side& cb_side,
const size_t& pin_id,
const std::string& postfix);
std::string generate_cb_memory_instance_name(const std::string& prefix,
const e_side& cb_side,
const size_t& pin_id,
const std::string& postfix,
const bool& feedthrough_memory = false);
std::string generate_cb_memory_instance_name(
const std::string& prefix, const e_side& cb_side, const size_t& pin_id,
const std::string& postfix, const bool& feedthrough_memory = false);
std::string generate_pb_mux_instance_name(const std::string& prefix,
t_pb_graph_pin* pb_graph_pin,
const std::string& postfix);
std::string generate_pb_memory_instance_name(const std::string& prefix,
t_pb_graph_pin* pb_graph_pin,
const std::string& postfix,
const bool& feedthrough_memory = false);
std::string generate_pb_memory_instance_name(
const std::string& prefix, t_pb_graph_pin* pb_graph_pin,
const std::string& postfix, const bool& feedthrough_memory = false);
std::string generate_grid_port_name(const size_t& width, const size_t& height,
const int& subtile_index,

25
openfpga/src/fabric/build_device_module.cpp
View File

@ -78,7 +78,8 @@ int build_device_module_graph(
/* Build memory modules */
build_memory_modules(module_manager, decoder_lib, openfpga_ctx.mux_lib(),
openfpga_ctx.arch().circuit_lib,
openfpga_ctx.arch().config_protocol.type(), group_config_block);
openfpga_ctx.arch().config_protocol.type(),
group_config_block);
/* Build grid and programmable block modules */
build_grid_modules(module_manager, decoder_lib, vpr_device_ctx,
@ -88,18 +89,20 @@ int build_device_module_graph(
duplicate_grid_pin, group_config_block, verbose);
if (true == compress_routing) {
build_unique_routing_modules(
module_manager, decoder_lib, vpr_device_ctx,
openfpga_ctx.vpr_device_annotation(), openfpga_ctx.device_rr_gsb(),
openfpga_ctx.arch().circuit_lib,
openfpga_ctx.arch().config_protocol.type(), sram_model, group_config_block, verbose);
build_unique_routing_modules(module_manager, decoder_lib, vpr_device_ctx,
openfpga_ctx.vpr_device_annotation(),
openfpga_ctx.device_rr_gsb(),
openfpga_ctx.arch().circuit_lib,
openfpga_ctx.arch().config_protocol.type(),
sram_model, group_config_block, verbose);
} else {
VTR_ASSERT_SAFE(false == compress_routing);
build_flatten_routing_modules(
module_manager, decoder_lib, vpr_device_ctx,
openfpga_ctx.vpr_device_annotation(), openfpga_ctx.device_rr_gsb(),
openfpga_ctx.arch().circuit_lib,
openfpga_ctx.arch().config_protocol.type(), sram_model, group_config_block, verbose);
build_flatten_routing_modules(module_manager, decoder_lib, vpr_device_ctx,
openfpga_ctx.vpr_device_annotation(),
openfpga_ctx.device_rr_gsb(),
openfpga_ctx.arch().circuit_lib,
openfpga_ctx.arch().config_protocol.type(),
sram_model, group_config_block, verbose);
}
/* Build tile modules if defined */

3
openfpga/src/fabric/build_fpga_core_wrapper_module.cpp
View File

@ -381,7 +381,8 @@ int add_fpga_core_to_device_module_graph(ModuleManager& module_manager,
/* Now fpga_core should be the only configurable child under the top-level
* module */
module_manager.add_configurable_child(new_top_module, top_module, 0, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
new_top_module, top_module, 0, ModuleManager::e_config_child_type::UNIFIED);
return status;
}

130
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -311,7 +311,8 @@ static void build_primitive_block_module(
}
/* Regular (independent) SRAM ports */
e_config_protocol_type mem_module_type = group_config_block ? CONFIG_MEM_FEEDTHROUGH : sram_orgz_type;
e_config_protocol_type mem_module_type =
group_config_block ? CONFIG_MEM_FEEDTHROUGH : sram_orgz_type;
size_t num_config_bits =
find_circuit_num_config_bits(mem_module_type, circuit_lib, primitive_model);
if (0 < num_config_bits) {
@ -335,9 +336,9 @@ static void build_primitive_block_module(
circuit_lib, primitive_pb_graph_node->pb_type, device_annotation);
/* Add the associated memory module as a child of primitive module */
std::string memory_module_name =
generate_memory_module_name(circuit_lib, primitive_model, sram_model,
std::string(MEMORY_MODULE_POSTFIX), group_config_block);
std::string memory_module_name = generate_memory_module_name(
circuit_lib, primitive_model, sram_model,
std::string(MEMORY_MODULE_POSTFIX), group_config_block);
ModuleId memory_module = module_manager.find_module(memory_module_name);
/* If there is no memory module required, we can skip the assocated net
@ -357,17 +358,21 @@ static void build_primitive_block_module(
module_manager, primitive_module, logic_module, logic_instance_id,
memory_module, memory_instance_id, circuit_lib, primitive_model);
/* Record memory-related information */
size_t config_child_id = module_manager.num_configurable_children(primitive_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(primitive_module, memory_module,
memory_instance_id,
group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
size_t config_child_id = module_manager.num_configurable_children(
primitive_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(
primitive_module, memory_module, memory_instance_id,
group_config_block ? ModuleManager::e_config_child_type::LOGICAL
: ModuleManager::e_config_child_type::UNIFIED);
/* For logical memory, define the physical memory here */
if (group_config_block) {
std::string physical_memory_module_name =
generate_memory_module_name(circuit_lib, primitive_model, sram_model,
std::string(MEMORY_MODULE_POSTFIX), false);
ModuleId physical_memory_module = module_manager.find_module(physical_memory_module_name);
module_manager.set_logical2physical_configurable_child(primitive_module, config_child_id, physical_memory_module);
ModuleId physical_memory_module =
module_manager.find_module(physical_memory_module_name);
module_manager.set_logical2physical_configurable_child(
primitive_module, config_child_id, physical_memory_module);
}
}
@ -375,11 +380,12 @@ static void build_primitive_block_module(
* primitive modules This is a one-shot addition that covers all the memory
* modules in this primitive module!
*/
if (0 < module_manager.num_configurable_children(primitive_module, ModuleManager::e_config_child_type::LOGICAL)) {
add_module_nets_memory_config_bus(module_manager, decoder_lib,
primitive_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model),
ModuleManager::e_config_child_type::LOGICAL);
if (0 < module_manager.num_configurable_children(
primitive_module, ModuleManager::e_config_child_type::LOGICAL)) {
add_module_nets_memory_config_bus(
module_manager, decoder_lib, primitive_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model),
ModuleManager::e_config_child_type::LOGICAL);
}
/* Add global ports to the pb_module:
@ -642,9 +648,9 @@ static void add_module_pb_graph_pin_interc(
generate_mux_subckt_name(circuit_lib, interc_circuit_model, fan_in,
std::string(MEMORY_MODULE_POSTFIX));
if (group_config_block) {
mux_mem_module_name =
generate_mux_subckt_name(circuit_lib, interc_circuit_model, fan_in,
std::string(MEMORY_FEEDTHROUGH_MODULE_POSTFIX));
mux_mem_module_name = generate_mux_subckt_name(
circuit_lib, interc_circuit_model, fan_in,
std::string(MEMORY_FEEDTHROUGH_MODULE_POSTFIX));
}
ModuleId mux_mem_module = module_manager.find_module(mux_mem_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module));
@ -656,22 +662,28 @@ static void add_module_pb_graph_pin_interc(
* generation to modules
*/
std::string mux_mem_instance_name = generate_pb_memory_instance_name(
GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string(""), group_config_block);
GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string(""),
group_config_block);
module_manager.set_child_instance_name(
pb_module, mux_mem_module, mux_mem_instance, mux_mem_instance_name);
/* Add this MUX as a configurable child to the pb_module */
size_t config_child_id = module_manager.num_configurable_children(pb_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(pb_module, mux_mem_module,
mux_mem_instance, group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
size_t config_child_id = module_manager.num_configurable_children(
pb_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(
pb_module, mux_mem_module, mux_mem_instance,
group_config_block ? ModuleManager::e_config_child_type::LOGICAL
: ModuleManager::e_config_child_type::UNIFIED);
if (group_config_block) {
std::string phy_mem_module_name =
generate_mux_subckt_name(circuit_lib, interc_circuit_model, fan_in,
std::string(MEMORY_MODULE_POSTFIX));
ModuleId phy_mem_module = module_manager.find_module(phy_mem_module_name);
ModuleId phy_mem_module =
module_manager.find_module(phy_mem_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(phy_mem_module));
module_manager.set_logical2physical_configurable_child(pb_module, config_child_id,
phy_mem_module);
VTR_LOGV(verbose, "Now use a feedthrough memory for '%s'\n", phy_mem_module_name.c_str());
module_manager.set_logical2physical_configurable_child(
pb_module, config_child_id, phy_mem_module);
VTR_LOGV(verbose, "Now use a feedthrough memory for '%s'\n",
phy_mem_module_name.c_str());
}
/* Add nets to connect SRAM ports of the MUX to the SRAM port of memory
@ -984,7 +996,8 @@ static void rec_build_logical_tile_modules(
std::vector<ModuleId> memory_modules;
std::vector<size_t> memory_instances;
e_config_protocol_type mem_module_type = group_config_block ? CONFIG_MEM_FEEDTHROUGH : sram_orgz_type;
e_config_protocol_type mem_module_type =
group_config_block ? CONFIG_MEM_FEEDTHROUGH : sram_orgz_type;
/* Add all the child Verilog modules as instances */
for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) {
@ -1029,8 +1042,10 @@ static void rec_build_logical_tile_modules(
if (0 < find_module_num_config_bits(module_manager, child_pb_module,
circuit_lib, sram_model,
mem_module_type)) {
module_manager.add_configurable_child(pb_module, child_pb_module,
child_instance_id, group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
pb_module, child_pb_module, child_instance_id,
group_config_block ? ModuleManager::e_config_child_type::LOGICAL
: ModuleManager::e_config_child_type::UNIFIED);
}
}
}
@ -1077,7 +1092,8 @@ static void rec_build_logical_tile_modules(
*/
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, pb_module, circuit_lib, sram_model, mem_module_type, ModuleManager::e_config_child_type::LOGICAL);
module_manager, pb_module, circuit_lib, sram_model, mem_module_type,
ModuleManager::e_config_child_type::LOGICAL);
if (0 < module_num_config_bits) {
add_sram_ports_to_module_manager(module_manager, pb_module, circuit_lib,
sram_model, mem_module_type,
@ -1088,11 +1104,12 @@ static void rec_build_logical_tile_modules(
* This is a one-shot addition that covers all the memory modules in this pb
* module!
*/
if (0 < module_manager.num_configurable_children(pb_module, ModuleManager::e_config_child_type::LOGICAL)) {
add_module_nets_memory_config_bus(module_manager, decoder_lib, pb_module,
mem_module_type,
circuit_lib.design_tech_type(sram_model),
ModuleManager::e_config_child_type::LOGICAL);
if (0 < module_manager.num_configurable_children(
pb_module, ModuleManager::e_config_child_type::LOGICAL)) {
add_module_nets_memory_config_bus(
module_manager, decoder_lib, pb_module, mem_module_type,
circuit_lib.design_tech_type(sram_model),
ModuleManager::e_config_child_type::LOGICAL);
}
VTR_LOGV(verbose, "Done\n");
@ -1113,8 +1130,7 @@ static void build_physical_tile_module(
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model, t_physical_tile_type_ptr phy_block_type,
const e_side& border_side, const bool& duplicate_grid_pin,
const bool& group_config_block,
const bool& verbose) {
const bool& group_config_block, const bool& verbose) {
/* Create a Module for the top-level physical block, and add to module manager
*/
std::string grid_module_name = generate_grid_block_module_name(
@ -1164,19 +1180,23 @@ static void build_physical_tile_module(
/* Identify if this sub module includes configuration bits,
* we will update the memory module and instance list
*/
if (0 < find_module_num_config_bits(module_manager, pb_module,
circuit_lib, sram_model,
group_config_block ? CONFIG_MEM_FEEDTHROUGH : sram_orgz_type)) {
/* Only add logical configurable children here. Since we will add a physical memory block at this level */
module_manager.add_configurable_child(grid_module, pb_module,
pb_instance_id, group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
if (0 < find_module_num_config_bits(
module_manager, pb_module, circuit_lib, sram_model,
group_config_block ? CONFIG_MEM_FEEDTHROUGH : sram_orgz_type)) {
/* Only add logical configurable children here. Since we will add a
* physical memory block at this level */
module_manager.add_configurable_child(
grid_module, pb_module, pb_instance_id,
group_config_block ? ModuleManager::e_config_child_type::LOGICAL
: ModuleManager::e_config_child_type::UNIFIED);
}
}
}
/* TODO: Add a physical memory block */
if (group_config_block) {
add_physical_memory_module(module_manager, decoder_lib, grid_module, circuit_lib, sram_orgz_type, sram_model);
add_physical_memory_module(module_manager, decoder_lib, grid_module,
circuit_lib, sram_orgz_type, sram_model);
}
/* Add grid ports(pins) to the module */
@ -1264,10 +1284,13 @@ static void build_physical_tile_module(
* we just need to find all the I/O ports from the child modules and build a
* list of it
*/
ModuleManager::e_config_child_type config_child_type = group_config_block ? ModuleManager::e_config_child_type::PHYSICAL : ModuleManager::e_config_child_type::LOGICAL;
ModuleManager::e_config_child_type config_child_type =
group_config_block ? ModuleManager::e_config_child_type::PHYSICAL
: ModuleManager::e_config_child_type::LOGICAL;
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type, config_child_type);
module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type,
config_child_type);
if (0 < module_num_config_bits) {
add_pb_sram_ports_to_module_manager(module_manager, grid_module,
circuit_lib, sram_model, sram_orgz_type,
@ -1278,7 +1301,8 @@ static void build_physical_tile_module(
* This is a one-shot addition that covers all the memory modules in this pb
* module!
*/
if (0 < module_manager.num_configurable_children(grid_module, config_child_type)) {
if (0 < module_manager.num_configurable_children(grid_module,
config_child_type)) {
add_pb_module_nets_memory_config_bus(
module_manager, decoder_lib, grid_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model), config_child_type);
@ -1357,17 +1381,17 @@ void build_grid_modules(
std::set<e_side> io_type_sides =
find_physical_io_tile_located_sides(device_ctx.grid, &physical_tile);
for (const e_side& io_type_side : io_type_sides) {
build_physical_tile_module(module_manager, decoder_lib,
device_annotation, circuit_lib,
sram_orgz_type, sram_model, &physical_tile,
io_type_side, duplicate_grid_pin, group_config_block, verbose);
build_physical_tile_module(
module_manager, decoder_lib, device_annotation, circuit_lib,
sram_orgz_type, sram_model, &physical_tile, io_type_side,
duplicate_grid_pin, group_config_block, verbose);
}
} else {
/* For CLB and heterogenenous blocks */
build_physical_tile_module(module_manager, decoder_lib, device_annotation,
circuit_lib, sram_orgz_type, sram_model,
&physical_tile, NUM_SIDES, duplicate_grid_pin, group_config_block,
verbose);
&physical_tile, NUM_SIDES, duplicate_grid_pin,
group_config_block, verbose);
}
}
VTR_LOG("Done\n");

293
openfpga/src/fabric/build_memory_modules.cpp
View File

@ -3,19 +3,21 @@
* the memories that are affiliated to multiplexers and other programmable
* circuit models, such as IOPADs, LUTs, etc.
********************************************************************/
#include "build_memory_modules.h"
#include <algorithm>
#include <ctime>
#include <string>
#include "command_exit_codes.h"
#include "build_decoder_modules.h"
#include "build_memory_modules.h"
#include "circuit_library_utils.h"
#include "command_exit_codes.h"
#include "decoder_library_utils.h"
#include "memory_utils.h"
#include "module_manager.h"
#include "module_manager_utils.h"
#include "mux_graph.h"
#include "mux_utils.h"
#include "memory_utils.h"
#include "openfpga_naming.h"
#include "openfpga_reserved_words.h"
#include "vtr_assert.h"
@ -173,7 +175,11 @@ static void add_module_nets_to_cmos_memory_config_chain_module(
const CircuitLibrary& circuit_lib, const CircuitPortId& model_input_port,
const CircuitPortId& model_output_port) {
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL).size();
mem_index <
module_manager
.configurable_children(parent_module,
ModuleManager::e_config_child_type::LOGICAL)
.size();
++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
@ -193,28 +199,30 @@ static void add_module_nets_to_cmos_memory_config_chain_module(
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
net_sink_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_module_id = module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
} else {
/* Find the port name of previous memory module */
std::string src_port_name = circuit_lib.port_prefix(model_output_port);
net_src_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
net_src_module_id = module_manager.configurable_children(
parent_module,
ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
parent_module,
ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
net_sink_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_module_id = module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
}
@ -248,9 +256,15 @@ static void add_module_nets_to_cmos_memory_config_chain_module(
/* Find the port name of previous memory module */
std::string src_port_name = circuit_lib.port_prefix(model_output_port);
ModuleId net_src_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL).back();
module_manager
.configurable_children(parent_module,
ModuleManager::e_config_child_type::LOGICAL)
.back();
size_t net_src_instance_id =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::LOGICAL).back();
module_manager
.configurable_child_instances(parent_module,
ModuleManager::e_config_child_type::LOGICAL)
.back();
ModulePortId net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
@ -310,7 +324,11 @@ static void add_module_nets_to_cmos_memory_scan_chain_module(
const CircuitLibrary& circuit_lib, const CircuitPortId& model_input_port,
const CircuitPortId& model_output_port) {
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL).size();
mem_index <
module_manager
.configurable_children(parent_module,
ModuleManager::e_config_child_type::LOGICAL)
.size();
++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
@ -330,28 +348,30 @@ static void add_module_nets_to_cmos_memory_scan_chain_module(
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
net_sink_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_module_id = module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
} else {
/* Find the port name of previous memory module */
std::string src_port_name = circuit_lib.port_prefix(model_output_port);
net_src_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
net_src_module_id = module_manager.configurable_children(
parent_module,
ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
parent_module,
ModuleManager::e_config_child_type::LOGICAL)[mem_index - 1];
net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
net_sink_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_module_id = module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::LOGICAL)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
}
@ -479,8 +499,9 @@ static void build_memory_flatten_module(ModuleManager& module_manager,
size_t sram_mem_instance =
module_manager.num_instance(mem_module, sram_mem_module);
module_manager.add_child_module(mem_module, sram_mem_module);
module_manager.add_configurable_child(mem_module, sram_mem_module,
sram_mem_instance, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
mem_module, sram_mem_module, sram_mem_instance,
ModuleManager::e_config_child_type::UNIFIED);
/* Build module nets */
/* Wire inputs of parent module to inputs of child modules */
@ -612,8 +633,9 @@ static void build_memory_chain_module(ModuleManager& module_manager,
size_t sram_mem_instance =
module_manager.num_instance(mem_module, sram_mem_module);
module_manager.add_child_module(mem_module, sram_mem_module);
module_manager.add_configurable_child(mem_module, sram_mem_module,
sram_mem_instance, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
mem_module, sram_mem_module, sram_mem_instance,
ModuleManager::e_config_child_type::UNIFIED);
/* Build module nets to wire outputs of sram modules to outputs of memory
* module */
@ -829,8 +851,9 @@ static void build_frame_memory_module(ModuleManager& module_manager,
size_t sram_instance =
module_manager.num_instance(mem_module, sram_mem_module);
module_manager.add_child_module(mem_module, sram_mem_module);
module_manager.add_configurable_child(mem_module, sram_mem_module,
sram_instance, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
mem_module, sram_mem_module, sram_instance,
ModuleManager::e_config_child_type::UNIFIED);
/* Wire data_in port to SRAM BL port */
ModulePortId sram_bl_port = module_manager.find_module_port(
@ -890,7 +913,8 @@ static void build_frame_memory_module(ModuleManager& module_manager,
add_module_global_ports_from_child_modules(module_manager, mem_module);
/* Add the decoder as the last configurable children */
module_manager.add_configurable_child(mem_module, decoder_module, 0, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
mem_module, decoder_module, 0, ModuleManager::e_config_child_type::UNIFIED);
}
/*********************************************************************
@ -964,10 +988,12 @@ static int build_feedthrough_memory_module(ModuleManager& module_manager,
/* Add module ports */
/* Input: memory inputs */
BasicPort in_port(std::string(MEMORY_FEEDTHROUGH_DATA_IN_PORT_NAME), num_mems);
BasicPort in_port(std::string(MEMORY_FEEDTHROUGH_DATA_IN_PORT_NAME),
num_mems);
ModulePortId mem_in_port = module_manager.add_port(
mem_module, in_port, ModuleManager::MODULE_INPUT_PORT);
BasicPort inb_port(std::string(MEMORY_FEEDTHROUGH_DATA_IN_INV_PORT_NAME), num_mems);
BasicPort inb_port(std::string(MEMORY_FEEDTHROUGH_DATA_IN_INV_PORT_NAME),
num_mems);
ModulePortId mem_inb_port = module_manager.add_port(
mem_module, inb_port, ModuleManager::MODULE_INPUT_PORT);
@ -975,7 +1001,8 @@ static int build_feedthrough_memory_module(ModuleManager& module_manager,
BasicPort out_port(std::string(CONFIGURABLE_MEMORY_DATA_OUT_NAME), num_mems);
ModulePortId mem_out_port = module_manager.add_port(
mem_module, out_port, ModuleManager::MODULE_OUTPUT_PORT);
BasicPort outb_port(std::string(CONFIGURABLE_MEMORY_INVERTED_DATA_OUT_NAME), num_mems);
BasicPort outb_port(std::string(CONFIGURABLE_MEMORY_INVERTED_DATA_OUT_NAME),
num_mems);
ModulePortId mem_outb_port = module_manager.add_port(
mem_module, outb_port, ModuleManager::MODULE_OUTPUT_PORT);
@ -987,8 +1014,8 @@ static int build_feedthrough_memory_module(ModuleManager& module_manager,
}
module_manager.add_module_net_source(mem_module, net, mem_module, 0,
mem_in_port, in_port.pins()[pin_id]);
module_manager.add_module_net_sink(
mem_module, net, mem_module, 0, mem_out_port, out_port.pins()[pin_id]);
module_manager.add_module_net_sink(mem_module, net, mem_module, 0,
mem_out_port, out_port.pins()[pin_id]);
}
for (size_t pin_id = 0; pin_id < inb_port.pins().size(); ++pin_id) {
ModuleNetId net = module_manager.create_module_net(mem_module);
@ -997,14 +1024,13 @@ static int build_feedthrough_memory_module(ModuleManager& module_manager,
}
module_manager.add_module_net_source(mem_module, net, mem_module, 0,
mem_inb_port, inb_port.pins()[pin_id]);
module_manager.add_module_net_sink(
mem_module, net, mem_module, 0, mem_outb_port, outb_port.pins()[pin_id]);
module_manager.add_module_net_sink(mem_module, net, mem_module, 0,
mem_outb_port, outb_port.pins()[pin_id]);
}
return CMD_EXEC_SUCCESS;
}
/*********************************************************************
* Generate Verilog modules for the memories that are used
* by multiplexers
@ -1070,7 +1096,7 @@ static void build_mux_memory_module(
* | | | |
* v v ... v v
* +----------------+
* | Memory Module |
* | Memory Module |
* +----------------+
* | | ... | |
* v v v v SRAM ports of multiplexer
@ -1079,8 +1105,7 @@ static void build_mux_memory_module(
* +---------------------+
********************************************************************/
static int build_mux_feedthrough_memory_module(
ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type, const CircuitModelId& mux_model,
const MuxGraph& mux_graph) {
int status = CMD_EXEC_SUCCESS;
@ -1100,7 +1125,8 @@ static int build_mux_feedthrough_memory_module(
mux_graph.num_inputs()),
std::string(MEMORY_FEEDTHROUGH_MODULE_POSTFIX));
status = build_feedthrough_memory_module(module_manager, module_name, num_config_bits);
status = build_feedthrough_memory_module(module_manager, module_name,
num_config_bits);
break;
}
case CIRCUIT_MODEL_DESIGN_RRAM:
@ -1118,7 +1144,6 @@ static int build_mux_feedthrough_memory_module(
return status;
}
/*********************************************************************
* Build modules for
* the memories that are affiliated to multiplexers and other programmable
@ -1134,14 +1159,15 @@ static int build_mux_feedthrough_memory_module(
* memory modules.
* Take another example, the memory circuit can implement the scan-chain or
* memory-bank organization for the memories.
* If we need feedthrough memory blocks, build the memory modules which contain only feedthrough wires
* If we need feedthrough memory blocks, build the memory modules which contain
*only feedthrough wires
********************************************************************/
int build_memory_modules(ModuleManager& module_manager,
DecoderLibrary& arch_decoder_lib,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const bool& require_feedthrough_memory) {
DecoderLibrary& arch_decoder_lib,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const bool& require_feedthrough_memory) {
int status = CMD_EXEC_SUCCESS;
vtr::ScopedStartFinishTimer timer("Build memory modules");
@ -1161,8 +1187,8 @@ int build_memory_modules(ModuleManager& module_manager,
sram_orgz_type, mux_model, mux_graph);
/* Create feedthrough memory module */
if (require_feedthrough_memory) {
status = build_mux_feedthrough_memory_module(module_manager, circuit_lib,
sram_orgz_type, mux_model, mux_graph);
status = build_mux_feedthrough_memory_module(
module_manager, circuit_lib, sram_orgz_type, mux_model, mux_graph);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1205,7 +1231,8 @@ int build_memory_modules(ModuleManager& module_manager,
sram_orgz_type, module_name, sram_models[0], num_mems);
/* Create feedthrough memory module */
if (require_feedthrough_memory) {
status = build_feedthrough_memory_module(module_manager, module_name, num_mems);
status =
build_feedthrough_memory_module(module_manager, module_name, num_mems);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1230,8 +1257,8 @@ static void add_module_output_nets_to_memory_group_module(
const std::string& mem_module_output_name, const ModuleId& child_module,
const size_t& output_pin_start_index, const size_t& child_instance) {
/* Wire inputs of parent module to inputs of child modules */
ModulePortId src_port_id = module_manager.find_module_port(
child_module, mem_module_output_name);
ModulePortId src_port_id =
module_manager.find_module_port(child_module, mem_module_output_name);
ModulePortId sink_port_id =
module_manager.find_module_port(mem_module, mem_module_output_name);
for (size_t pin_id = 0;
@ -1280,7 +1307,8 @@ int build_memory_group_module(ModuleManager& module_manager,
module_manager.add_port(mem_module, out_port,
ModuleManager::MODULE_OUTPUT_PORT);
std::string outb_port_name = generate_configurable_memory_inverted_data_out_name();
std::string outb_port_name =
generate_configurable_memory_inverted_data_out_name();
BasicPort outb_port(outb_port_name, num_mems);
module_manager.add_port(mem_module, outb_port,
ModuleManager::MODULE_OUTPUT_PORT);
@ -1290,25 +1318,33 @@ int build_memory_group_module(ModuleManager& module_manager,
size_t mem_outb_pin_start_index = 0;
for (size_t ichild = 0; ichild < child_modules.size(); ++ichild) {
ModuleId child_module = child_modules[ichild];
size_t child_instance = module_manager.num_instance(mem_module, child_module);
size_t child_instance =
module_manager.num_instance(mem_module, child_module);
module_manager.add_child_module(mem_module, child_module, false);
module_manager.add_configurable_child(mem_module, child_module, child_instance, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
mem_module, child_module, child_instance,
ModuleManager::e_config_child_type::UNIFIED);
/* Wire outputs of child module to outputs of parent module */
add_module_output_nets_to_memory_group_module(
module_manager, mem_module, out_port_name,
child_module, mem_out_pin_start_index, child_instance);
module_manager, mem_module, out_port_name, child_module,
mem_out_pin_start_index, child_instance);
add_module_output_nets_to_memory_group_module(
module_manager, mem_module, outb_port_name,
child_module, mem_outb_pin_start_index, child_instance);
module_manager, mem_module, outb_port_name, child_module,
mem_outb_pin_start_index, child_instance);
/* Update pin counter */
ModulePortId child_out_port_id = module_manager.find_module_port(child_module, out_port_name);
mem_out_pin_start_index += module_manager.module_port(child_module, child_out_port_id).get_width();
ModulePortId child_out_port_id =
module_manager.find_module_port(child_module, out_port_name);
mem_out_pin_start_index +=
module_manager.module_port(child_module, child_out_port_id).get_width();
ModulePortId child_outb_port_id = module_manager.find_module_port(child_module, outb_port_name);
mem_outb_pin_start_index += module_manager.module_port(child_module, child_outb_port_id).get_width();
ModulePortId child_outb_port_id =
module_manager.find_module_port(child_module, outb_port_name);
mem_outb_pin_start_index +=
module_manager.module_port(child_module, child_outb_port_id).get_width();
}
/* Check pin counter */
VTR_ASSERT(mem_out_pin_start_index == num_mems && mem_outb_pin_start_index == num_mems);
VTR_ASSERT(mem_out_pin_start_index == num_mems &&
mem_outb_pin_start_index == num_mems);
/* Add global ports to the pb_module:
* This is a much easier job after adding sub modules (instances),
@ -1342,10 +1378,12 @@ int build_memory_group_module(ModuleManager& module_manager,
* we just need to find all the I/O ports from the child modules and build a
* list of it
*/
ModuleManager::e_config_child_type config_child_type = ModuleManager::e_config_child_type::PHYSICAL;
ModuleManager::e_config_child_type config_child_type =
ModuleManager::e_config_child_type::PHYSICAL;
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, mem_module, circuit_lib, sram_model, sram_orgz_type, config_child_type);
module_manager, mem_module, circuit_lib, sram_model, sram_orgz_type,
config_child_type);
if (0 < module_num_config_bits) {
add_sram_ports_to_module_manager(module_manager, mem_module, circuit_lib,
sram_model, sram_orgz_type,
@ -1356,10 +1394,11 @@ int build_memory_group_module(ModuleManager& module_manager,
* This is a one-shot addition that covers all the memory modules in this pb
* module!
*/
if (0 < module_manager.num_configurable_children(mem_module, config_child_type)) {
add_module_nets_memory_config_bus(module_manager, decoder_lib, mem_module,
sram_orgz_type,
circuit_lib.design_tech_type(sram_model), config_child_type);
if (0 <
module_manager.num_configurable_children(mem_module, config_child_type)) {
add_module_nets_memory_config_bus(
module_manager, decoder_lib, mem_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model), config_child_type);
}
return CMD_EXEC_SUCCESS;
@ -1368,12 +1407,20 @@ int build_memory_group_module(ModuleManager& module_manager,
/*****************************************************************************
* This function creates a physical memory module and add it the current module
* The following tasks will be accomplished:
* - Traverse all the logical configurable children in the module tree, starting from the current module
* - Build a list of the leaf logical configurable children and count the total memory sizes, the memory size for each physical memory submodule. Note that the physical memory submodule should be cached already in each leaf logical configurable children
* - Get the physical memory module required by each leaf logical configurable child
* - Create a dedicated module name for the physical memory (check if already exists, if yes, skip creating a new module)
* - Traverse all the logical configurable children in the module tree, starting
*from the current module
* - Build a list of the leaf logical configurable children and count the total
*memory sizes, the memory size for each physical memory submodule. Note that
*the physical memory submodule should be cached already in each leaf logical
*configurable children
* - Get the physical memory module required by each leaf logical configurable
*child
* - Create a dedicated module name for the physical memory (check if already
*exists, if yes, skip creating a new module)
* - Instanciate the module
* - Built nets. Note that only the output ports of the physical memory block is required, since they should drive the dedicated memory ports of logical configurable children
* - Built nets. Note that only the output ports of the physical memory block is
*required, since they should drive the dedicated memory ports of logical
*configurable children
*****************************************************************************/
int add_physical_memory_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
@ -1384,49 +1431,70 @@ int add_physical_memory_module(ModuleManager& module_manager,
int status = CMD_EXEC_SUCCESS;
std::vector<ModuleId> required_phy_mem_modules;
status = rec_find_physical_memory_children(static_cast<const ModuleManager&>(module_manager), curr_module, required_phy_mem_modules);
status = rec_find_physical_memory_children(
static_cast<const ModuleManager&>(module_manager), curr_module,
required_phy_mem_modules);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, curr_module, circuit_lib, sram_model, CONFIG_MEM_FEEDTHROUGH, ModuleManager::e_config_child_type::LOGICAL);
module_manager, curr_module, circuit_lib, sram_model,
CONFIG_MEM_FEEDTHROUGH, ModuleManager::e_config_child_type::LOGICAL);
/* No need to build a memory when there are no configuration bits required */
if (module_num_config_bits == 0) {
return CMD_EXEC_SUCCESS;
}
std::string phy_mem_module_name = generate_physical_memory_module_name(module_manager.module_name(curr_module), module_num_config_bits);
std::string phy_mem_module_name = generate_physical_memory_module_name(
module_manager.module_name(curr_module), module_num_config_bits);
ModuleId phy_mem_module = module_manager.find_module(phy_mem_module_name);
if (!module_manager.valid_module_id(phy_mem_module)) {
status = build_memory_group_module(module_manager, decoder_lib, circuit_lib, sram_orgz_type, phy_mem_module_name, sram_model, required_phy_mem_modules, module_num_config_bits);
status = build_memory_group_module(module_manager, decoder_lib, circuit_lib,
sram_orgz_type, phy_mem_module_name,
sram_model, required_phy_mem_modules,
module_num_config_bits);
}
if (status != CMD_EXEC_SUCCESS) {
VTR_LOG_ERROR("Failed to create the physical memory module '%s'!\n", phy_mem_module_name.c_str());
VTR_LOG_ERROR("Failed to create the physical memory module '%s'!\n",
phy_mem_module_name.c_str());
return CMD_EXEC_FATAL_ERROR;
}
phy_mem_module = module_manager.find_module(phy_mem_module_name);
if (!module_manager.valid_module_id(phy_mem_module)) {
VTR_LOG_ERROR("Failed to create the physical memory module '%s'!\n", phy_mem_module_name.c_str());
VTR_LOG_ERROR("Failed to create the physical memory module '%s'!\n",
phy_mem_module_name.c_str());
return CMD_EXEC_FATAL_ERROR;
}
/* Add the physical memory module to the current module */
size_t phy_mem_instance = module_manager.num_instance(curr_module, phy_mem_module);
size_t phy_mem_instance =
module_manager.num_instance(curr_module, phy_mem_module);
module_manager.add_child_module(curr_module, phy_mem_module, false);
/* Register in the physical configurable children list */
module_manager.add_configurable_child(curr_module, phy_mem_module, phy_mem_instance, ModuleManager::e_config_child_type::PHYSICAL);
module_manager.add_configurable_child(
curr_module, phy_mem_module, phy_mem_instance,
ModuleManager::e_config_child_type::PHYSICAL);
/* Build nets between the data output of the physical memory module and the outputs of the logical configurable children */
/* Build nets between the data output of the physical memory module and the
* outputs of the logical configurable children */
size_t curr_mem_pin_index = 0;
std::map<e_circuit_model_port_type, std::string> mem2mem_port_map;
mem2mem_port_map[CIRCUIT_MODEL_PORT_BL] = std::string(CONFIGURABLE_MEMORY_DATA_OUT_NAME);
mem2mem_port_map[CIRCUIT_MODEL_PORT_BLB] = std::string(CONFIGURABLE_MEMORY_INVERTED_DATA_OUT_NAME);
for (size_t ichild = 0; ichild < module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::PHYSICAL).size(); ++ichild) {
for (e_circuit_model_port_type port_type : {CIRCUIT_MODEL_PORT_BL, CIRCUIT_MODEL_PORT_BLB}) {
mem2mem_port_map[CIRCUIT_MODEL_PORT_BL] =
std::string(CONFIGURABLE_MEMORY_DATA_OUT_NAME);
mem2mem_port_map[CIRCUIT_MODEL_PORT_BLB] =
std::string(CONFIGURABLE_MEMORY_INVERTED_DATA_OUT_NAME);
for (size_t ichild = 0;
ichild < module_manager
.configurable_children(
curr_module, ModuleManager::e_config_child_type::PHYSICAL)
.size();
++ichild) {
for (e_circuit_model_port_type port_type :
{CIRCUIT_MODEL_PORT_BL, CIRCUIT_MODEL_PORT_BLB}) {
std::string src_port_name = mem2mem_port_map[port_type];
std::string des_port_name =
generate_sram_port_name(CONFIG_MEM_FEEDTHROUGH, port_type);
generate_sram_port_name(CONFIG_MEM_FEEDTHROUGH, port_type);
/* Try to find these ports in the module manager */
ModulePortId src_port_id =
module_manager.find_module_port(phy_mem_module, src_port_name);
@ -1436,15 +1504,16 @@ int add_physical_memory_module(ModuleManager& module_manager,
BasicPort src_port =
module_manager.module_port(phy_mem_module, src_port_id);
ModuleId des_module = module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
size_t des_instance = module_manager.configurable_child_instances(curr_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
ModuleId des_module = module_manager.configurable_children(
curr_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
size_t des_instance = module_manager.configurable_child_instances(
curr_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
ModulePortId des_port_id =
module_manager.find_module_port(des_module, des_port_name);
if (!module_manager.valid_module_port_id(des_module, des_port_id)) {
return CMD_EXEC_FATAL_ERROR;
}
BasicPort des_port =
module_manager.module_port(des_module, des_port_id);
BasicPort des_port = module_manager.module_port(des_module, des_port_id);
/* Build nets */
for (size_t ipin = 0; ipin < des_port.pins().size(); ++ipin) {
/* Create a net and add source and sink to it */
@ -1463,17 +1532,28 @@ int add_physical_memory_module(ModuleManager& module_manager,
}
}
/* TODO: Recursively update the logical configurable child with the physical memory module parent and its instance id */
/* TODO: Recursively update the logical configurable child with the physical
* memory module parent and its instance id */
std::map<ModuleId, size_t> logical_mem_child_inst_count;
status = rec_update_logical_memory_children_with_physical_mapping(module_manager, curr_module, phy_mem_module, logical_mem_child_inst_count);
status = rec_update_logical_memory_children_with_physical_mapping(
module_manager, curr_module, phy_mem_module, logical_mem_child_inst_count);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
/* Sanity check */
std::map<ModuleId, size_t> required_mem_child_inst_count;
for (ModuleId curr_child_module : module_manager.child_modules(phy_mem_module)) {
if (logical_mem_child_inst_count[curr_child_module] != module_manager.num_instance(phy_mem_module, curr_child_module)) {
VTR_LOG_ERROR("Expect the %lu instances of module '%s' under its parent '%s' while only updated %lu during logical-to-physical configurable child mapping sync-up!\n", module_manager.num_instance(phy_mem_module, curr_child_module), module_manager.module_name(curr_child_module).c_str(), module_manager.module_name(phy_mem_module).c_str(), logical_mem_child_inst_count[curr_child_module]);
for (ModuleId curr_child_module :
module_manager.child_modules(phy_mem_module)) {
if (logical_mem_child_inst_count[curr_child_module] !=
module_manager.num_instance(phy_mem_module, curr_child_module)) {
VTR_LOG_ERROR(
"Expect the %lu instances of module '%s' under its parent '%s' while "
"only updated %lu during logical-to-physical configurable child "
"mapping sync-up!\n",
module_manager.num_instance(phy_mem_module, curr_child_module),
module_manager.module_name(curr_child_module).c_str(),
module_manager.module_name(phy_mem_module).c_str(),
logical_mem_child_inst_count[curr_child_module]);
return CMD_EXEC_FATAL_ERROR;
}
}
@ -1481,5 +1561,4 @@ int add_physical_memory_module(ModuleManager& module_manager,
return status;
}
} /* end namespace openfpga */

10
openfpga/src/fabric/build_memory_modules.h
View File

@ -23,11 +23,11 @@ std::vector<ModuleNetId> add_module_output_nets_to_chain_mem_modules(
const size_t& child_index, const size_t& child_instance);
int build_memory_modules(ModuleManager& module_manager,
DecoderLibrary& arch_decoder_lib,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const bool& require_feedthrough_memory);
DecoderLibrary& arch_decoder_lib,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const bool& require_feedthrough_memory);
int build_memory_group_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,

86
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -14,10 +14,10 @@
#include "vtr_time.h"
/* Headers from openfpgautil library */
#include "build_memory_modules.h"
#include "build_module_graph_utils.h"
#include "build_routing_module_utils.h"
#include "build_routing_modules.h"
#include "build_memory_modules.h"
#include "module_manager_utils.h"
#include "openfpga_naming.h"
#include "openfpga_reserved_words.h"
@ -231,7 +231,8 @@ static void build_switch_block_mux_module(
* modules
*/
std::string mem_instance_name = generate_sb_memory_instance_name(
SWITCH_BLOCK_MEM_INSTANCE_PREFIX, chan_side, chan_node_id, std::string(""), group_config_block);
SWITCH_BLOCK_MEM_INSTANCE_PREFIX, chan_side, chan_node_id, std::string(""),
group_config_block);
module_manager.set_child_instance_name(sb_module, mem_module, mem_instance_id,
mem_instance_name);
@ -241,16 +242,22 @@ static void build_switch_block_mux_module(
module_manager, sb_module, mux_module, mux_instance_id, mem_module,
mem_instance_id, circuit_lib, mux_model);
/* Update memory and instance list */
size_t config_child_id = module_manager.num_configurable_children(sb_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(sb_module, mem_module, mem_instance_id, group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
size_t config_child_id = module_manager.num_configurable_children(
sb_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(
sb_module, mem_module, mem_instance_id,
group_config_block ? ModuleManager::e_config_child_type::LOGICAL
: ModuleManager::e_config_child_type::UNIFIED);
/* For logical memory, define the physical memory here */
if (group_config_block) {
std::string physical_mem_module_name =
generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size,
std::string(MEMORY_MODULE_POSTFIX));
ModuleId physical_mem_module = module_manager.find_module(physical_mem_module_name);
ModuleId physical_mem_module =
module_manager.find_module(physical_mem_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(physical_mem_module));
module_manager.set_logical2physical_configurable_child(sb_module, config_child_id, physical_mem_module);
module_manager.set_logical2physical_configurable_child(
sb_module, config_child_id, physical_mem_module);
}
}
@ -482,7 +489,8 @@ static void build_switch_block_module(
/* Build a physical memory block */
if (group_config_block) {
add_physical_memory_module(module_manager, decoder_lib, sb_module, circuit_lib, sram_orgz_type, sram_model);
add_physical_memory_module(module_manager, decoder_lib, sb_module,
circuit_lib, sram_orgz_type, sram_model);
}
/* Add global ports to the pb_module:
@ -510,10 +518,13 @@ static void build_switch_block_module(
* we just need to find all the I/O ports from the child modules and build a
* list of it
*/
ModuleManager::e_config_child_type config_child_type = group_config_block ? ModuleManager::e_config_child_type::PHYSICAL : ModuleManager::e_config_child_type::LOGICAL;
ModuleManager::e_config_child_type config_child_type =
group_config_block ? ModuleManager::e_config_child_type::PHYSICAL
: ModuleManager::e_config_child_type::LOGICAL;
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, sb_module, circuit_lib, sram_model, sram_orgz_type, config_child_type);
module_manager, sb_module, circuit_lib, sram_model, sram_orgz_type,
config_child_type);
if (0 < module_num_config_bits) {
add_pb_sram_ports_to_module_manager(module_manager, sb_module, circuit_lib,
sram_model, sram_orgz_type,
@ -524,7 +535,8 @@ static void build_switch_block_module(
* primitive modules This is a one-shot addition that covers all the memory
* modules in this primitive module!
*/
if (0 < module_manager.num_configurable_children(sb_module, config_child_type)) {
if (0 <
module_manager.num_configurable_children(sb_module, config_child_type)) {
add_pb_module_nets_memory_config_bus(
module_manager, decoder_lib, sb_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model), config_child_type);
@ -726,7 +738,7 @@ static void build_connection_block_mux_module(
if (group_config_block) {
mem_module_name =
generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size,
std::string(MEMORY_FEEDTHROUGH_MODULE_POSTFIX));
std::string(MEMORY_FEEDTHROUGH_MODULE_POSTFIX));
}
ModuleId mem_module = module_manager.find_module(mem_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
@ -752,16 +764,22 @@ static void build_connection_block_mux_module(
module_manager, cb_module, mux_module, mux_instance_id, mem_module,
mem_instance_id, circuit_lib, mux_model);
/* Update memory and instance list */
size_t config_child_id = module_manager.num_configurable_children(cb_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(cb_module, mem_module, mem_instance_id, group_config_block ? ModuleManager::e_config_child_type::LOGICAL : ModuleManager::e_config_child_type::UNIFIED);
size_t config_child_id = module_manager.num_configurable_children(
cb_module, ModuleManager::e_config_child_type::LOGICAL);
module_manager.add_configurable_child(
cb_module, mem_module, mem_instance_id,
group_config_block ? ModuleManager::e_config_child_type::LOGICAL
: ModuleManager::e_config_child_type::UNIFIED);
/* For logical memory, define the physical memory here */
if (group_config_block) {
std::string physical_mem_module_name =
generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size,
std::string(MEMORY_MODULE_POSTFIX));
ModuleId physical_mem_module = module_manager.find_module(physical_mem_module_name);
ModuleId physical_mem_module =
module_manager.find_module(physical_mem_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(physical_mem_module));
module_manager.set_logical2physical_configurable_child(cb_module, config_child_id, physical_mem_module);
module_manager.set_logical2physical_configurable_child(
cb_module, config_child_id, physical_mem_module);
}
}
@ -795,8 +813,8 @@ static void build_connection_block_interc_modules(
/* Print the multiplexer, fan_in >= 2 */
build_connection_block_mux_module(
module_manager, cb_module, device_annotation, grids, rr_graph, rr_gsb,
cb_type, circuit_lib, cb_ipin_side, ipin_index,
input_port_to_module_nets, group_config_block);
cb_type, circuit_lib, cb_ipin_side, ipin_index, input_port_to_module_nets,
group_config_block);
} /*Nothing should be done else*/
}
@ -861,8 +879,7 @@ static void build_connection_block_module(
const RRGraphView& rr_graph, const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model, const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const bool& group_config_block,
const t_rr_type& cb_type, const bool& group_config_block,
const bool& verbose) {
/* Create the netlist */
vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type),
@ -985,13 +1002,15 @@ static void build_connection_block_module(
++inode) {
build_connection_block_interc_modules(
module_manager, cb_module, device_annotation, grids, rr_graph, rr_gsb,
cb_type, circuit_lib, cb_ipin_side, inode, input_port_to_module_nets, group_config_block);
cb_type, circuit_lib, cb_ipin_side, inode, input_port_to_module_nets,
group_config_block);
}
}
/* Build a physical memory block */
if (group_config_block) {
add_physical_memory_module(module_manager, decoder_lib, cb_module, circuit_lib, sram_orgz_type, sram_model);
add_physical_memory_module(module_manager, decoder_lib, cb_module,
circuit_lib, sram_orgz_type, sram_model);
}
/* Add global ports to the pb_module:
@ -1019,10 +1038,13 @@ static void build_connection_block_module(
* we just need to find all the I/O ports from the child modules and build a
* list of it
*/
ModuleManager::e_config_child_type config_child_type = group_config_block ? ModuleManager::e_config_child_type::PHYSICAL : ModuleManager::e_config_child_type::LOGICAL;
ModuleManager::e_config_child_type config_child_type =
group_config_block ? ModuleManager::e_config_child_type::PHYSICAL
: ModuleManager::e_config_child_type::LOGICAL;
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, cb_module, circuit_lib, sram_model, sram_orgz_type, config_child_type);
module_manager, cb_module, circuit_lib, sram_model, sram_orgz_type,
config_child_type);
if (0 < module_num_config_bits) {
add_pb_sram_ports_to_module_manager(module_manager, cb_module, circuit_lib,
sram_model, sram_orgz_type,
@ -1033,7 +1055,8 @@ static void build_connection_block_module(
* primitive modules This is a one-shot addition that covers all the memory
* modules in this primitive module!
*/
if (0 < module_manager.num_configurable_children(cb_module, config_child_type)) {
if (0 <
module_manager.num_configurable_children(cb_module, config_child_type)) {
add_pb_module_nets_memory_config_bus(
module_manager, decoder_lib, cb_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model), config_child_type);
@ -1052,8 +1075,7 @@ static void build_flatten_connection_block_modules(
const DeviceRRGSB& device_rr_gsb, const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model, const t_rr_type& cb_type,
const bool& group_config_block,
const bool& verbose) {
const bool& group_config_block, const bool& verbose) {
/* Build unique X-direction connection block modules */
vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
@ -1089,8 +1111,7 @@ void build_flatten_routing_modules(
const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation,
const DeviceRRGSB& device_rr_gsb, const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model,
const bool& group_config_block,
const CircuitModelId& sram_model, const bool& group_config_block,
const bool& verbose) {
vtr::ScopedStartFinishTimer timer("Build routing modules...");
@ -1112,11 +1133,13 @@ void build_flatten_routing_modules(
build_flatten_connection_block_modules(
module_manager, decoder_lib, device_ctx, device_annotation, device_rr_gsb,
circuit_lib, sram_orgz_type, sram_model, CHANX, group_config_block, verbose);
circuit_lib, sram_orgz_type, sram_model, CHANX, group_config_block,
verbose);
build_flatten_connection_block_modules(
module_manager, decoder_lib, device_ctx, device_annotation, device_rr_gsb,
circuit_lib, sram_orgz_type, sram_model, CHANY, group_config_block, verbose);
circuit_lib, sram_orgz_type, sram_model, CHANY, group_config_block,
verbose);
}
/********************************************************************
@ -1135,8 +1158,7 @@ void build_unique_routing_modules(
const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation,
const DeviceRRGSB& device_rr_gsb, const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model,
const bool& group_config_block,
const CircuitModelId& sram_model, const bool& group_config_block,
const bool& verbose) {
vtr::ScopedStartFinishTimer timer("Build unique routing modules...");

6
openfpga/src/fabric/build_routing_modules.h
View File

@ -24,8 +24,7 @@ void build_flatten_routing_modules(
const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation,
const DeviceRRGSB& device_rr_gsb, const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model,
const bool& group_config_block,
const CircuitModelId& sram_model, const bool& group_config_block,
const bool& verbose);
void build_unique_routing_modules(
@ -33,8 +32,7 @@ void build_unique_routing_modules(
const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation,
const DeviceRRGSB& device_rr_gsb, const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model,
const bool& group_config_block,
const CircuitModelId& sram_model, const bool& group_config_block,
const bool& verbose);
} /* end namespace openfpga */

24
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -1331,8 +1331,9 @@ static int build_tile_module(
if (0 < find_module_num_config_bits(module_manager, pb_module,
circuit_lib, sram_model,
sram_orgz_type)) {
module_manager.add_configurable_child(tile_module, pb_module,
pb_instance, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
tile_module, pb_module, pb_instance,
ModuleManager::e_config_child_type::UNIFIED);
}
VTR_LOGV(
verbose,
@ -1378,8 +1379,9 @@ static int build_tile_module(
if (0 < find_module_num_config_bits(module_manager, cb_module,
circuit_lib, sram_model,
sram_orgz_type)) {
module_manager.add_configurable_child(tile_module, cb_module,
cb_instance, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
tile_module, cb_module, cb_instance,
ModuleManager::e_config_child_type::UNIFIED);
}
VTR_LOGV(verbose,
"Added connection block module '%s' (instance: '%s') to "
@ -1417,8 +1419,9 @@ static int build_tile_module(
sb_instance_name);
if (0 < find_module_num_config_bits(module_manager, sb_module, circuit_lib,
sram_model, sram_orgz_type)) {
module_manager.add_configurable_child(tile_module, sb_module,
sb_instance, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
tile_module, sb_module, sb_instance,
ModuleManager::e_config_child_type::UNIFIED);
}
VTR_LOGV(
verbose,
@ -1468,7 +1471,8 @@ static int build_tile_module(
*/
size_t module_num_config_bits =
find_module_num_config_bits_from_child_modules(
module_manager, tile_module, circuit_lib, sram_model, sram_orgz_type, ModuleManager::e_config_child_type::LOGICAL);
module_manager, tile_module, circuit_lib, sram_model, sram_orgz_type,
ModuleManager::e_config_child_type::LOGICAL);
if (0 < module_num_config_bits) {
add_pb_sram_ports_to_module_manager(module_manager, tile_module,
circuit_lib, sram_model, sram_orgz_type,
@ -1479,10 +1483,12 @@ static int build_tile_module(
* This is a one-shot addition that covers all the memory modules in this pb
* module!
*/
if (0 < module_manager.num_configurable_children(tile_module, ModuleManager::e_config_child_type::LOGICAL)) {
if (0 < module_manager.num_configurable_children(
tile_module, ModuleManager::e_config_child_type::LOGICAL)) {
add_pb_module_nets_memory_config_bus(
module_manager, decoder_lib, tile_module, sram_orgz_type,
circuit_lib.design_tech_type(sram_model), ModuleManager::e_config_child_type::LOGICAL);
circuit_lib.design_tech_type(sram_model),
ModuleManager::e_config_child_type::LOGICAL);
}
VTR_LOGV(verbose, "Done\n");

5
openfpga/src/fabric/build_top_module.cpp
View File

@ -134,7 +134,10 @@ int build_top_module(
* module!
*/
if (false == frame_view) {
if (0 < module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size()) {
if (0 < module_manager
.configurable_children(
top_module, ModuleManager::e_config_child_type::PHYSICAL)
.size()) {
add_top_module_nets_memory_config_bus(
module_manager, decoder_lib, blwl_sr_banks, top_module, circuit_lib,
config_protocol, circuit_lib.design_tech_type(sram_model),

6
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1076,7 +1076,11 @@ static void organize_top_module_tile_based_memory_modules(
const CircuitModelId& sram_model, const DeviceGrid& grids,
const vtr::Matrix<size_t>& tile_instance_ids, const FabricTile& fabric_tile) {
/* Ensure clean vectors to return */
VTR_ASSERT(true == module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).empty());
VTR_ASSERT(true ==
module_manager
.configurable_children(
top_module, ModuleManager::e_config_child_type::PHYSICAL)
.empty());
std::vector<vtr::Point<size_t>> tile_coords;
bool positive_direction = true;

102
openfpga/src/fabric/build_top_module_memory.cpp
View File

@ -86,8 +86,7 @@ static void organize_top_module_tile_cb_modules(
module_manager.add_configurable_child(
top_module, cb_module,
cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)],
ModuleManager::e_config_child_type::UNIFIED,
config_coord);
ModuleManager::e_config_child_type::UNIFIED, config_coord);
}
}
@ -174,7 +173,8 @@ static void organize_top_module_tile_memory_modules(
rr_gsb.get_sb_y() * 2 + 1);
module_manager.add_configurable_child(
top_module, sb_module,
sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()], ModuleManager::e_config_child_type::UNIFIED, config_coord);
sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()],
ModuleManager::e_config_child_type::UNIFIED, config_coord);
}
}
@ -221,8 +221,7 @@ static void organize_top_module_tile_memory_modules(
module_manager.add_configurable_child(
top_module, grid_module,
grid_instance_ids[tile_coord.x()][tile_coord.y()],
ModuleManager::e_config_child_type::UNIFIED,
config_coord);
ModuleManager::e_config_child_type::UNIFIED, config_coord);
}
}
@ -272,14 +271,21 @@ void build_top_module_configurable_regions(
"Build configurable regions for the top module");
/* Ensure we have valid configurable children */
VTR_ASSERT(false == module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).empty());
VTR_ASSERT(false ==
module_manager
.configurable_children(
top_module, ModuleManager::e_config_child_type::PHYSICAL)
.empty());
/* Ensure that our region definition is valid */
VTR_ASSERT(1 <= config_protocol.num_regions());
/* Exclude decoders from the list */
size_t num_configurable_children =
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size();
module_manager
.configurable_children(top_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size();
if (CONFIG_MEM_MEMORY_BANK == config_protocol.type() ||
CONFIG_MEM_QL_MEMORY_BANK == config_protocol.type()) {
num_configurable_children -= 2;
@ -294,7 +300,10 @@ void build_top_module_configurable_regions(
bool create_region = true;
ConfigRegionId curr_region = ConfigRegionId::INVALID();
for (size_t ichild = 0;
ichild < module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size();
ichild < module_manager
.configurable_children(
top_module, ModuleManager::e_config_child_type::PHYSICAL)
.size();
++ichild) {
if (true == create_region) {
curr_region = module_manager.add_config_region(top_module);
@ -303,8 +312,11 @@ void build_top_module_configurable_regions(
/* Add the child to a region */
module_manager.add_configurable_child_to_region(
top_module, curr_region,
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild],
module_manager.configurable_child_instances(top_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild], ichild);
module_manager.configurable_children(
top_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild],
module_manager.configurable_child_instances(
top_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild],
ichild);
/* See if the current region is full or not:
* For the last region, we will keep adding until we finish all the children
@ -430,7 +442,11 @@ void organize_top_module_memory_modules(
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const bool& compact_routing_hierarchy) {
/* Ensure clean vectors to return */
VTR_ASSERT(true == module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).empty());
VTR_ASSERT(true ==
module_manager
.configurable_children(
top_module, ModuleManager::e_config_child_type::PHYSICAL)
.empty());
/* First, organize the I/O tiles on the border */
/* Special for the I/O tileas on RIGHT and BOTTOM,
@ -533,7 +549,11 @@ void organize_top_module_memory_modules(
void shuffle_top_module_configurable_children(
ModuleManager& module_manager, const ModuleId& top_module,
const ConfigProtocol& config_protocol) {
size_t num_keys = module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size();
size_t num_keys =
module_manager
.configurable_children(top_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size();
std::vector<size_t> shuffled_keys;
shuffled_keys.reserve(num_keys);
for (size_t ikey = 0; ikey < num_keys; ++ikey) {
@ -544,11 +564,14 @@ void shuffle_top_module_configurable_children(
/* Cache the configurable children and their instances */
std::vector<ModuleId> orig_configurable_children =
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL);
module_manager.configurable_children(
top_module, ModuleManager::e_config_child_type::PHYSICAL);
std::vector<size_t> orig_configurable_child_instances =
module_manager.configurable_child_instances(top_module, ModuleManager::e_config_child_type::PHYSICAL);
module_manager.configurable_child_instances(
top_module, ModuleManager::e_config_child_type::PHYSICAL);
std::vector<vtr::Point<int>> orig_configurable_child_coordinates =
module_manager.configurable_child_coordinates(top_module, ModuleManager::e_config_child_type::PHYSICAL);
module_manager.configurable_child_coordinates(
top_module, ModuleManager::e_config_child_type::PHYSICAL);
/* Reorganize the configurable children */
module_manager.clear_configurable_children(top_module);
@ -654,10 +677,10 @@ int load_top_module_memory_modules_from_fabric_key(
}
/* Now we can add the child to configurable children of the top module */
module_manager.add_configurable_child(top_module, instance_info.first,
instance_info.second,
ModuleManager::e_config_child_type::UNIFIED,
fabric_key.key_coordinate(key));
module_manager.add_configurable_child(
top_module, instance_info.first, instance_info.second,
ModuleManager::e_config_child_type::UNIFIED,
fabric_key.key_coordinate(key));
module_manager.add_configurable_child_to_region(
top_module, top_module_config_region, instance_info.first,
instance_info.second, curr_configurable_child_id);
@ -1334,17 +1357,27 @@ static void add_top_module_nets_cmos_memory_bank_config_bus(
* Note: this MUST be done after adding all the module nets to other regular
* configurable children
*/
module_manager.add_configurable_child(top_module, bl_decoder_module,
curr_bl_decoder_instance_id, ModuleManager::e_config_child_type::PHYSICAL);
module_manager.add_configurable_child(
top_module, bl_decoder_module, curr_bl_decoder_instance_id,
ModuleManager::e_config_child_type::PHYSICAL);
module_manager.add_configurable_child_to_region(
top_module, config_region, bl_decoder_module, curr_bl_decoder_instance_id,
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size() - 1);
module_manager
.configurable_children(top_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size() -
1);
module_manager.add_configurable_child(top_module, wl_decoder_module,
curr_wl_decoder_instance_id, ModuleManager::e_config_child_type::PHYSICAL);
module_manager.add_configurable_child(
top_module, wl_decoder_module, curr_wl_decoder_instance_id,
ModuleManager::e_config_child_type::PHYSICAL);
module_manager.add_configurable_child_to_region(
top_module, config_region, wl_decoder_module, curr_wl_decoder_instance_id,
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size() - 1);
module_manager
.configurable_children(top_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size() -
1);
}
}
@ -1764,8 +1797,8 @@ static void add_top_module_nets_cmos_memory_frame_decoder_config_bus(
for (size_t mem_index = 0; mem_index < configurable_children.size();
++mem_index) {
ModuleId child_module = configurable_children[mem_index];
size_t child_instance =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
size_t child_instance = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
ModulePortId child_din_port = module_manager.find_module_port(
child_module, std::string(DECODER_DATA_IN_PORT_NAME));
BasicPort child_din_port_info =
@ -1799,8 +1832,8 @@ static void add_top_module_nets_cmos_memory_frame_decoder_config_bus(
for (size_t mem_index = 0; mem_index < configurable_children.size();
++mem_index) {
ModuleId child_module = configurable_children[mem_index];
size_t child_instance =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
size_t child_instance = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
ModulePortId child_en_port = module_manager.find_module_port(
child_module, std::string(DECODER_ENABLE_PORT_NAME));
BasicPort child_en_port_info =
@ -1819,12 +1852,17 @@ static void add_top_module_nets_cmos_memory_frame_decoder_config_bus(
}
/* Add the decoder as the last configurable children */
module_manager.add_configurable_child(parent_module, decoder_module,
decoder_instance, ModuleManager::e_config_child_type::PHYSICAL);
module_manager.add_configurable_child(
parent_module, decoder_module, decoder_instance,
ModuleManager::e_config_child_type::PHYSICAL);
/* Register the configurable child to configuration region */
module_manager.add_configurable_child_to_region(
parent_module, config_region, decoder_module, decoder_instance,
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size() - 1);
module_manager
.configurable_children(parent_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size() -
1);
}
/*********************************************************************

72
openfpga/src/fabric/build_top_module_memory_bank.cpp
View File

@ -58,7 +58,11 @@ static void add_module_nets_to_ql_memory_bank_shift_register_module(
const std::string& chain_head_port_name,
const std::string& chain_tail_port_name) {
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size();
mem_index <
module_manager
.configurable_children(parent_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size();
++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
@ -78,28 +82,30 @@ static void add_module_nets_to_ql_memory_bank_shift_register_module(
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
net_sink_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
net_sink_module_id = module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
} else {
/* Find the port name of previous memory module */
std::string src_port_name = circuit_lib.port_prefix(model_output_port);
net_src_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index - 1];
net_src_module_id = module_manager.configurable_children(
parent_module,
ModuleManager::e_config_child_type::PHYSICAL)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index - 1];
parent_module,
ModuleManager::e_config_child_type::PHYSICAL)[mem_index - 1];
net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
net_sink_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
net_sink_module_id = module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
}
@ -133,9 +139,15 @@ static void add_module_nets_to_ql_memory_bank_shift_register_module(
/* Find the port name of previous memory module */
std::string src_port_name = circuit_lib.port_prefix(model_output_port);
ModuleId net_src_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).back();
module_manager
.configurable_children(parent_module,
ModuleManager::e_config_child_type::PHYSICAL)
.back();
size_t net_src_instance_id =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL).back();
module_manager
.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)
.back();
ModulePortId net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
@ -244,8 +256,9 @@ static ModuleId build_bl_shift_register_chain_module(
size_t sram_mem_instance =
module_manager.num_instance(mem_module, sram_mem_module);
module_manager.add_child_module(mem_module, sram_mem_module);
module_manager.add_configurable_child(mem_module, sram_mem_module,
sram_mem_instance, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
mem_module, sram_mem_module, sram_mem_instance,
ModuleManager::e_config_child_type::UNIFIED);
/* Build module nets to wire bl outputs of sram modules to BL outputs of
* memory module */
@ -362,8 +375,9 @@ static ModuleId build_wl_shift_register_chain_module(
size_t sram_mem_instance =
module_manager.num_instance(mem_module, sram_mem_module);
module_manager.add_child_module(mem_module, sram_mem_module);
module_manager.add_configurable_child(mem_module, sram_mem_module,
sram_mem_instance, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
mem_module, sram_mem_module, sram_mem_instance,
ModuleManager::e_config_child_type::UNIFIED);
/* Build module nets to wire wl outputs of sram modules to WL outputs of
* memory module */
@ -698,11 +712,16 @@ static void add_top_module_nets_cmos_ql_memory_bank_bl_decoder_config_bus(
* Note: this MUST be done after adding all the module nets to other regular
* configurable children
*/
module_manager.add_configurable_child(top_module, bl_decoder_module,
curr_bl_decoder_instance_id, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
top_module, bl_decoder_module, curr_bl_decoder_instance_id,
ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child_to_region(
top_module, config_region, bl_decoder_module, curr_bl_decoder_instance_id,
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size() - 1);
module_manager
.configurable_children(top_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size() -
1);
}
}
@ -967,11 +986,16 @@ static void add_top_module_nets_cmos_ql_memory_bank_wl_decoder_config_bus(
* Note: this MUST be done after adding all the module nets to other regular
* configurable children
*/
module_manager.add_configurable_child(top_module, wl_decoder_module,
curr_wl_decoder_instance_id, ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child(
top_module, wl_decoder_module, curr_wl_decoder_instance_id,
ModuleManager::e_config_child_type::UNIFIED);
module_manager.add_configurable_child_to_region(
top_module, config_region, wl_decoder_module, curr_wl_decoder_instance_id,
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size() - 1);
module_manager
.configurable_children(top_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size() -
1);
}
}

24
openfpga/src/fabric/fabric_key_writer.cpp
View File

@ -32,7 +32,10 @@ static int add_module_keys_to_fabric_key(const ModuleManager& module_manager,
return CMD_EXEC_SUCCESS;
}
/* Bypass modules which does not have any configurable children */
if (module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::PHYSICAL).empty()) {
if (module_manager
.configurable_children(curr_module,
ModuleManager::e_config_child_type::PHYSICAL)
.empty()) {
return CMD_EXEC_SUCCESS;
}
/* Now create the module and add subkey one by one */
@ -41,12 +44,15 @@ static int add_module_keys_to_fabric_key(const ModuleManager& module_manager,
return CMD_EXEC_FATAL_ERROR;
}
size_t num_config_child =
module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::PHYSICAL).size();
module_manager
.configurable_children(curr_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size();
for (size_t ichild = 0; ichild < num_config_child; ++ichild) {
ModuleId child_module =
module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
size_t child_instance =
module_manager.configurable_child_instances(curr_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
ModuleId child_module = module_manager.configurable_children(
curr_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
size_t child_instance = module_manager.configurable_child_instances(
curr_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
FabricSubKeyId sub_key = fabric_key.create_module_key(key_module_id);
fabric_key.set_sub_key_name(sub_key,
@ -111,7 +117,11 @@ int write_fabric_key_to_xml_file(
/* Build a fabric key database by visiting all the configurable children */
FabricKey fabric_key;
size_t num_keys = module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size();
size_t num_keys =
module_manager
.configurable_children(top_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size();
fabric_key.reserve_keys(num_keys);

158
openfpga/src/fabric/module_manager.cpp
View File

@ -84,7 +84,7 @@ std::vector<ModuleId> ModuleManager::configurable_children(
if (type == ModuleManager::e_config_child_type::LOGICAL) {
return logical_configurable_children_[parent_module];
}
}
VTR_ASSERT(type == ModuleManager::e_config_child_type::PHYSICAL);
return physical_configurable_children_[parent_module];
}
@ -121,7 +121,8 @@ std::vector<ModuleId> ModuleManager::logical2physical_configurable_children(
}
/* Find all the instances of configurable child modules under a parent module */
std::vector<size_t> ModuleManager::logical2physical_configurable_child_instances(
std::vector<size_t>
ModuleManager::logical2physical_configurable_child_instances(
const ModuleId& parent_module) const {
/* Validate the module_id */
VTR_ASSERT(valid_module_id(parent_module));
@ -130,7 +131,8 @@ std::vector<size_t> ModuleManager::logical2physical_configurable_child_instances
}
/* Find all the instances of configurable child modules under a parent module */
std::vector<ModuleId> ModuleManager::logical2physical_configurable_child_parents(
std::vector<ModuleId>
ModuleManager::logical2physical_configurable_child_parents(
const ModuleId& parent_module) const {
/* Validate the module_id */
VTR_ASSERT(valid_module_id(parent_module));
@ -412,7 +414,8 @@ size_t ModuleManager::instance_id(const ModuleId& parent_module,
return size_t(-1);
}
size_t ModuleManager::num_configurable_children(const ModuleId& parent_module, const e_config_child_type& type) const {
size_t ModuleManager::num_configurable_children(
const ModuleId& parent_module, const e_config_child_type& type) const {
VTR_ASSERT(valid_module_id(parent_module));
if (type == ModuleManager::e_config_child_type::LOGICAL) {
return logical_configurable_children_[parent_module].size();
@ -657,15 +660,20 @@ bool ModuleManager::net_sink_exist(const ModuleId& module,
return false;
}
bool ModuleManager::unified_configurable_children(const ModuleId& curr_module) const {
if (logical_configurable_children_[curr_module].size() != physical_configurable_children_[curr_module].size()) {
bool ModuleManager::unified_configurable_children(
const ModuleId& curr_module) const {
if (logical_configurable_children_[curr_module].size() !=
physical_configurable_children_[curr_module].size()) {
return false;
}
for (size_t ichild = 0; ichild < logical_configurable_children_[curr_module].size(); ++ichild) {
if (logical_configurable_children_[curr_module][ichild] != physical_configurable_children_[curr_module][ichild]) {
for (size_t ichild = 0;
ichild < logical_configurable_children_[curr_module].size(); ++ichild) {
if (logical_configurable_children_[curr_module][ichild] !=
physical_configurable_children_[curr_module][ichild]) {
return false;
}
if (logical_configurable_child_instances_[curr_module][ichild] != physical_configurable_child_instances_[curr_module][ichild]) {
if (logical_configurable_child_instances_[curr_module][ichild] !=
physical_configurable_child_instances_[curr_module][ichild]) {
return false;
}
}
@ -977,88 +985,129 @@ void ModuleManager::add_configurable_child(const ModuleId& parent_module,
/* Ensure that the instance id is in range */
VTR_ASSERT(child_instance < num_instance(parent_module, child_module));
if (type == ModuleManager::e_config_child_type::LOGICAL || type == ModuleManager::e_config_child_type::UNIFIED) {
if (type == ModuleManager::e_config_child_type::LOGICAL ||
type == ModuleManager::e_config_child_type::UNIFIED) {
logical_configurable_children_[parent_module].push_back(child_module);
logical_configurable_child_instances_[parent_module].push_back(child_instance);
logical_configurable_child_instances_[parent_module].push_back(
child_instance);
}
if (type == ModuleManager::e_config_child_type::PHYSICAL || type == ModuleManager::e_config_child_type::UNIFIED) {
if (type == ModuleManager::e_config_child_type::PHYSICAL ||
type == ModuleManager::e_config_child_type::UNIFIED) {
physical_configurable_children_[parent_module].push_back(child_module);
physical_configurable_child_instances_[parent_module].push_back(child_instance);
physical_configurable_child_instances_[parent_module].push_back(
child_instance);
physical_configurable_child_regions_[parent_module].push_back(
ConfigRegionId::INVALID());
physical_configurable_child_coordinates_[parent_module].push_back(coord);
}
if (type == ModuleManager::e_config_child_type::UNIFIED) {
logical2physical_configurable_children_[parent_module].push_back(child_module);
logical2physical_configurable_child_instances_[parent_module].push_back(child_instance);
logical2physical_configurable_child_parents_[parent_module].push_back(parent_module);
logical2physical_configurable_children_[parent_module].push_back(
child_module);
logical2physical_configurable_child_instances_[parent_module].push_back(
child_instance);
logical2physical_configurable_child_parents_[parent_module].push_back(
parent_module);
} else if (type == ModuleManager::e_config_child_type::LOGICAL) {
logical2physical_configurable_children_[parent_module].emplace_back();
logical2physical_configurable_child_instances_[parent_module].emplace_back();
logical2physical_configurable_child_instances_[parent_module]
.emplace_back();
logical2physical_configurable_child_parents_[parent_module].emplace_back();
}
}
void ModuleManager::set_logical2physical_configurable_child(const ModuleId& parent_module, const size_t& logical_child_id, const ModuleId& physical_child_module) {
void ModuleManager::set_logical2physical_configurable_child(
const ModuleId& parent_module, const size_t& logical_child_id,
const ModuleId& physical_child_module) {
/* Sanity checks */
VTR_ASSERT(valid_module_id(parent_module));
VTR_ASSERT(logical_child_id < num_configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL));
VTR_ASSERT(logical_child_id <
num_configurable_children(
parent_module, ModuleManager::e_config_child_type::LOGICAL));
/* Create the pair */
logical2physical_configurable_children_[parent_module][logical_child_id] = physical_child_module;
logical2physical_configurable_children_[parent_module][logical_child_id] =
physical_child_module;
}
void ModuleManager::set_logical2physical_configurable_child_instance(const ModuleId& parent_module, const size_t& logical_child_id, const size_t& physical_child_instance) {
void ModuleManager::set_logical2physical_configurable_child_instance(
const ModuleId& parent_module, const size_t& logical_child_id,
const size_t& physical_child_instance) {
/* Sanity checks */
VTR_ASSERT(valid_module_id(parent_module));
VTR_ASSERT(logical_child_id < num_configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL));
VTR_ASSERT(logical_child_id <
num_configurable_children(
parent_module, ModuleManager::e_config_child_type::LOGICAL));
/* Create the pair */
logical2physical_configurable_child_instances_[parent_module][logical_child_id] = physical_child_instance;
logical2physical_configurable_child_instances_[parent_module]
[logical_child_id] =
physical_child_instance;
}
void ModuleManager::set_logical2physical_configurable_child_parent_module(const ModuleId& parent_module, const size_t& logical_child_id, const ModuleId& physical_child_parent_module) {
void ModuleManager::set_logical2physical_configurable_child_parent_module(
const ModuleId& parent_module, const size_t& logical_child_id,
const ModuleId& physical_child_parent_module) {
/* Sanity checks */
VTR_ASSERT(valid_module_id(parent_module));
VTR_ASSERT(logical_child_id < num_configurable_children(parent_module, ModuleManager::e_config_child_type::LOGICAL));
VTR_ASSERT(logical_child_id <
num_configurable_children(
parent_module, ModuleManager::e_config_child_type::LOGICAL));
/* Create the pair */
logical2physical_configurable_child_parents_[parent_module][logical_child_id] = physical_child_parent_module;
logical2physical_configurable_child_parents_[parent_module]
[logical_child_id] =
physical_child_parent_module;
}
void ModuleManager::reserve_configurable_child(const ModuleId& parent_module,
const size_t& num_children,
const e_config_child_type& type) {
void ModuleManager::reserve_configurable_child(
const ModuleId& parent_module, const size_t& num_children,
const e_config_child_type& type) {
VTR_ASSERT(valid_module_id(parent_module));
if (type == ModuleManager::e_config_child_type::LOGICAL || type == ModuleManager::e_config_child_type::UNIFIED) {
/* Do reserve when the number of children is larger than current size of lists
if (type == ModuleManager::e_config_child_type::LOGICAL ||
type == ModuleManager::e_config_child_type::UNIFIED) {
/* Do reserve when the number of children is larger than current size of
* lists
*/
if (num_children > logical_configurable_children_[parent_module].size()) {
logical_configurable_children_[parent_module].reserve(num_children);
}
if (num_children > logical_configurable_child_instances_[parent_module].size()) {
logical_configurable_child_instances_[parent_module].reserve(num_children);
if (num_children >
logical_configurable_child_instances_[parent_module].size()) {
logical_configurable_child_instances_[parent_module].reserve(
num_children);
}
if (num_children > logical2physical_configurable_children_[parent_module].size()) {
logical2physical_configurable_children_[parent_module].reserve(num_children);
if (num_children >
logical2physical_configurable_children_[parent_module].size()) {
logical2physical_configurable_children_[parent_module].reserve(
num_children);
}
if (num_children > logical2physical_configurable_child_instances_[parent_module].size()) {
logical2physical_configurable_child_instances_[parent_module].reserve(num_children);
if (num_children >
logical2physical_configurable_child_instances_[parent_module].size()) {
logical2physical_configurable_child_instances_[parent_module].reserve(
num_children);
}
if (num_children > logical2physical_configurable_child_parents_[parent_module].size()) {
logical2physical_configurable_child_parents_[parent_module].reserve(num_children);
if (num_children >
logical2physical_configurable_child_parents_[parent_module].size()) {
logical2physical_configurable_child_parents_[parent_module].reserve(
num_children);
}
}
if (type == ModuleManager::e_config_child_type::PHYSICAL || type == ModuleManager::e_config_child_type::UNIFIED) {
if (type == ModuleManager::e_config_child_type::PHYSICAL ||
type == ModuleManager::e_config_child_type::UNIFIED) {
if (num_children > physical_configurable_children_[parent_module].size()) {
physical_configurable_children_[parent_module].reserve(num_children);
}
if (num_children > physical_configurable_child_instances_[parent_module].size()) {
physical_configurable_child_instances_[parent_module].reserve(num_children);
if (num_children >
physical_configurable_child_instances_[parent_module].size()) {
physical_configurable_child_instances_[parent_module].reserve(
num_children);
}
if (num_children > physical_configurable_child_regions_[parent_module].size()) {
if (num_children >
physical_configurable_child_regions_[parent_module].size()) {
physical_configurable_child_regions_[parent_module].reserve(num_children);
}
if (num_children > physical_configurable_child_coordinates_[parent_module].size()) {
physical_configurable_child_coordinates_[parent_module].reserve(num_children);
if (num_children >
physical_configurable_child_coordinates_[parent_module].size()) {
physical_configurable_child_coordinates_[parent_module].reserve(
num_children);
}
}
}
@ -1088,15 +1137,19 @@ void ModuleManager::add_configurable_child_to_region(
/* Ensure that the child module is in the configurable children list */
VTR_ASSERT(child_module ==
configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[config_child_id]);
configurable_children(
parent_module,
ModuleManager::e_config_child_type::PHYSICAL)[config_child_id]);
VTR_ASSERT(child_instance ==
configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[config_child_id]);
configurable_child_instances(
parent_module,
ModuleManager::e_config_child_type::PHYSICAL)[config_child_id]);
/* If the child is already in another region, error out */
if ((true ==
valid_region_id(
parent_module,
physical_configurable_child_regions_[parent_module][config_child_id])) &&
if ((true == valid_region_id(
parent_module,
physical_configurable_child_regions_[parent_module]
[config_child_id])) &&
(config_region !=
physical_configurable_child_regions_[parent_module][config_child_id])) {
VTR_LOGF_ERROR(
@ -1104,7 +1157,8 @@ void ModuleManager::add_configurable_child_to_region(
"Try to add a configurable child '%s[%lu]' to region '%lu' which is "
"already added to another region '%lu'!\n",
module_name(child_module).c_str(), child_instance, size_t(config_region),
size_t(physical_configurable_child_regions_[parent_module][config_child_id]));
size_t(
physical_configurable_child_regions_[parent_module][config_child_id]));
exit(1);
}

97
openfpga/src/fabric/module_manager.h
View File

@ -68,17 +68,14 @@ class ModuleManager {
NUM_MODULE_USAGE_TYPES
};
/* Type of configurable child:
* - logical: represent a logical configurable block, which may not contain a physical memory inside
* - physical: represent a physical configurable block, which contains a physical memory inside
/* Type of configurable child:
* - logical: represent a logical configurable block, which may not contain a
* physical memory inside
* - physical: represent a physical configurable block, which contains a
* physical memory inside
* - unified: a unified block whose physical memory is also the logical memory
*/
enum class e_config_child_type {
LOGICAL,
PHYSICAL,
UNIFIED,
NUM_TYPES
};
enum class e_config_child_type { LOGICAL, PHYSICAL, UNIFIED, NUM_TYPES };
public: /* Public Constructors */
public: /* Type implementations */
@ -196,8 +193,10 @@ class ModuleManager {
*/
std::vector<size_t> logical2physical_configurable_child_instances(
const ModuleId& parent_module) const;
/* Find all the parent modules of physical configurable child modules under a parent module
* Note that a physical configurable child module may be at another module; Only the logical child module is under the current parent module
/* Find all the parent modules of physical configurable child modules under a
* parent module Note that a physical configurable child module may be at
* another module; Only the logical child module is under the current parent
* module
*/
std::vector<ModuleId> logical2physical_configurable_child_parents(
const ModuleId& parent_module) const;
@ -265,7 +264,8 @@ class ModuleManager {
const ModuleId& child_module,
const std::string& instance_name) const;
/** @brief Count the number of logical configurable children */
size_t num_configurable_children(const ModuleId& parent_module, const e_config_child_type& type) const;
size_t num_configurable_children(const ModuleId& parent_module,
const e_config_child_type& type) const;
/* Find the type of a port */
ModuleManager::e_module_port_type port_type(const ModuleId& module,
const ModulePortId& port) const;
@ -323,7 +323,9 @@ class ModuleManager {
const ModuleId& sink_module, const size_t& instance_id,
const ModulePortId& sink_port, const size_t& sink_pin);
/** @brief Check if the configurable children under a given module are unified or not. If unified, it means that the logical configurable children are the same as the physical configurable children */
/** @brief Check if the configurable children under a given module are unified
* or not. If unified, it means that the logical configurable children are the
* same as the physical configurable children */
bool unified_configurable_children(const ModuleId& curr_module) const;
private: /* Private accessors */
@ -388,14 +390,21 @@ class ModuleManager {
*/
void add_configurable_child(
const ModuleId& module, const ModuleId& child_module,
const size_t& child_instance,
const e_config_child_type& type,
const size_t& child_instance, const e_config_child_type& type,
const vtr::Point<int> coord = vtr::Point<int>(-1, -1));
/** @brief Create a pair of mapping from a logical configurable child to a physical configurable child */
void set_logical2physical_configurable_child(const ModuleId& parent_module, const size_t& logical_child_id, const ModuleId& physical_child_module);
/** @brief Create a pair of mapping from a logical configurable child to a physical configurable child */
void set_logical2physical_configurable_child_instance(const ModuleId& parent_module, const size_t& logical_child_id, const size_t& physical_child_instance);
void set_logical2physical_configurable_child_parent_module(const ModuleId& parent_module, const size_t& logical_child_id, const ModuleId& physical_child_parent_module);
/** @brief Create a pair of mapping from a logical configurable child to a
* physical configurable child */
void set_logical2physical_configurable_child(
const ModuleId& parent_module, const size_t& logical_child_id,
const ModuleId& physical_child_module);
/** @brief Create a pair of mapping from a logical configurable child to a
* physical configurable child */
void set_logical2physical_configurable_child_instance(
const ModuleId& parent_module, const size_t& logical_child_id,
const size_t& physical_child_instance);
void set_logical2physical_configurable_child_parent_module(
const ModuleId& parent_module, const size_t& logical_child_id,
const ModuleId& physical_child_parent_module);
/* Reserved a number of configurable children for memory efficiency */
void reserve_configurable_child(const ModuleId& module,
const size_t& num_children,
@ -405,8 +414,8 @@ class ModuleManager {
ConfigRegionId add_config_region(const ModuleId& module);
/* Add a configurable child module to a region
* Note:
* - The child module must be added as a physical configurable child to the parent
* module before calling this function!
* - The child module must be added as a physical configurable child to the
* parent module before calling this function!
*/
void add_configurable_child_to_region(const ModuleId& parent_module,
const ConfigRegionId& config_region,
@ -550,41 +559,49 @@ class ModuleManager {
* from the children_ list This is really dependent how the configuration
* protocol is organized which should be made by users/designers
* Note that there could be two types of configurable children under a module
* - logical: only contains virtual/feedthough memory blocks. A logical configurable child can only contain logical subchild. Logical memory block is required for architecture bitstream generation, because it carries logical information (the location of memory to its programmable resources)
* - physical: contains physical memory blocks. Logical memory blocks are mapped to the physical memory block. A physical memory block may contain coordinates and configuration regions which are required for fabric bitstream generation.
* - logical: only contains virtual/feedthough memory blocks. A logical
* configurable child can only contain logical subchild. Logical memory block
* is required for architecture bitstream generation, because it carries
* logical information (the location of memory to its programmable resources)
* - physical: contains physical memory blocks. Logical memory blocks are
* mapped to the physical memory block. A physical memory block may contain
* coordinates and configuration regions which are required for fabric
* bitstream generation.
*/
vtr::vector<ModuleId, std::vector<ModuleId>>
logical_configurable_children_; /* Child modules with configurable memory bits that
this module contain */
logical_configurable_children_; /* Child modules with configurable memory
bits that this module contain */
vtr::vector<ModuleId, std::vector<size_t>>
logical_configurable_child_instances_; /* Instances of child modules with
configurable memory bits that this module
contain */
vtr::vector<ModuleId, std::vector<ModuleId>>
logical2physical_configurable_children_; /* Child modules with configurable memory bits that
this module contain */
logical2physical_configurable_children_; /* Child modules with configurable
memory bits that this module contain */
vtr::vector<ModuleId, std::vector<size_t>>
logical2physical_configurable_child_instances_; /* Instances of child modules with
configurable memory bits that this module
contain */
logical2physical_configurable_child_instances_; /* Instances of child
modules with configurable memory bits that
this module contain */
vtr::vector<ModuleId, std::vector<ModuleId>>
logical2physical_configurable_child_parents_; /* Parent modules with configurable memory bits that
this module contain */
logical2physical_configurable_child_parents_; /* Parent modules with
configurable memory bits that this module contain
*/
vtr::vector<ModuleId, std::vector<ModuleId>>
physical_configurable_children_; /* Child modules with configurable memory bits that
this module contain */
physical_configurable_children_; /* Child modules with configurable memory
bits that this module contain */
vtr::vector<ModuleId, std::vector<size_t>>
physical_configurable_child_instances_; /* Instances of child modules with
configurable memory bits that this module
contain */
vtr::vector<ModuleId, std::vector<ConfigRegionId>>
physical_configurable_child_regions_; /* Instances of child modules with configurable
memory bits that this module contain */
physical_configurable_child_regions_; /* Instances of child modules with
configurable memory bits that this module
contain */
vtr::vector<ModuleId, std::vector<vtr::Point<int>>>
physical_configurable_child_coordinates_; /* Relative coorindates of child modules
with configurable memory bits that this
module contain */
physical_configurable_child_coordinates_; /* Relative coorindates of child
modules with configurable memory bits
that this module contain */
/* Configurable regions to group the physical configurable children
* Note:

27
openfpga/src/fpga_bitstream/build_device_bitstream.cpp
View File

@ -35,15 +35,19 @@ static size_t rec_estimate_device_bitstream_num_blocks(
* actually configurable memory elements
* We skip them in couting
*/
if (0 == module_manager.num_configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL)) {
if (0 == module_manager.num_configurable_children(
top_module, ModuleManager::e_config_child_type::PHYSICAL)) {
return 0;
}
size_t num_configurable_children =
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size();
module_manager
.configurable_children(top_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size();
for (size_t ichild = 0; ichild < num_configurable_children; ++ichild) {
ModuleId child_module =
module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
ModuleId child_module = module_manager.configurable_children(
top_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
num_blocks +=
rec_estimate_device_bitstream_num_blocks(module_manager, child_module);
}
@ -68,7 +72,8 @@ static size_t rec_estimate_device_bitstream_num_bits(
/* If a child module has no configurable children, this is a leaf node
* We can count it in. Otherwise, we should go recursively.
*/
if (0 == module_manager.num_configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)) {
if (0 == module_manager.num_configurable_children(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)) {
return 1;
}
@ -105,7 +110,10 @@ static size_t rec_estimate_device_bitstream_num_bits(
VTR_ASSERT_SAFE(parent_module != top_module);
size_t num_configurable_children =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size();
module_manager
.configurable_children(parent_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size();
/* Frame-based configuration protocol will have 1 decoder
* if there are more than 1 configurable children
@ -116,8 +124,8 @@ static size_t rec_estimate_device_bitstream_num_bits(
}
for (size_t ichild = 0; ichild < num_configurable_children; ++ichild) {
ModuleId child_module =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
ModuleId child_module = module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild];
num_bits += rec_estimate_device_bitstream_num_bits(
module_manager, top_module, child_module, config_protocol);
}
@ -193,7 +201,8 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
/* Reserve child blocks for the top level block */
bitstream_manager.reserve_child_blocks(
top_block, count_module_manager_module_configurable_children(
openfpga_ctx.module_graph(), top_module, ModuleManager::e_config_child_type::PHYSICAL));
openfpga_ctx.module_graph(), top_module,
ModuleManager::e_config_child_type::PHYSICAL));
/* Create bitstream from grids */
VTR_LOGV(verbose, "Building grid bitstream...\n");

43
openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
View File

@ -74,12 +74,17 @@ static void rec_build_module_fabric_dependent_chain_bitstream(
} else {
for (size_t child_id = 0;
child_id <
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size();
module_manager
.configurable_children(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)
.size();
++child_id) {
ModuleId child_module =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_id];
size_t child_instance =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_id];
ModuleId child_module = module_manager.configurable_children(
parent_module,
ModuleManager::e_config_child_type::PHYSICAL)[child_id];
size_t child_instance = module_manager.configurable_child_instances(
parent_module,
ModuleManager::e_config_child_type::PHYSICAL)[child_id];
/* Get the instance name and ensure it is not empty */
std::string instance_name = module_manager.instance_name(
parent_module, child_module, child_instance);
@ -196,7 +201,8 @@ static void rec_build_module_fabric_dependent_memory_bank_bitstream(
* - no need to exclude decoders as they are not there
*/
std::vector<ModuleId> configurable_children =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL);
module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::PHYSICAL);
size_t num_configurable_children = configurable_children.size();
@ -211,8 +217,9 @@ static void rec_build_module_fabric_dependent_memory_bank_bitstream(
for (size_t child_id = 0; child_id < num_configurable_children;
++child_id) {
ModuleId child_module = configurable_children[child_id];
size_t child_instance =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_id];
size_t child_instance = module_manager.configurable_child_instances(
parent_module,
ModuleManager::e_config_child_type::PHYSICAL)[child_id];
/* Get the instance name and ensure it is not empty */
std::string instance_name = module_manager.instance_name(
@ -323,10 +330,11 @@ static void rec_build_module_fabric_dependent_frame_bitstream(
config_region);
} else {
VTR_ASSERT(top_module != parent_module);
configurable_children =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL);
configurable_children = module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::PHYSICAL);
configurable_child_instances =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL);
module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::PHYSICAL);
}
size_t num_configurable_children = configurable_children.size();
@ -360,10 +368,13 @@ static void rec_build_module_fabric_dependent_frame_bitstream(
/* The max address code size is the max address code size of all the
* configurable children in all the regions
*/
for (const ModuleId& child_module :
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)) {
for (const ModuleId& child_module : module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)) {
/* Bypass any decoder module (which no configurable children */
if (module_manager.configurable_children(child_module, ModuleManager::e_config_child_type::PHYSICAL).empty()) {
if (module_manager
.configurable_children(
child_module, ModuleManager::e_config_child_type::PHYSICAL)
.empty()) {
continue;
}
const ModulePortId& child_addr_port_id =
@ -493,8 +504,8 @@ static void rec_build_module_fabric_dependent_frame_bitstream(
parent_modules.back(), config_region);
} else {
VTR_ASSERT(top_module != parent_modules.back());
configurable_children =
module_manager.configurable_children(parent_modules.back(), ModuleManager::e_config_child_type::PHYSICAL);
configurable_children = module_manager.configurable_children(
parent_modules.back(), ModuleManager::e_config_child_type::PHYSICAL);
}
ModuleId decoder_module = configurable_children.back();

8
openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp
View File

@ -123,7 +123,8 @@ static void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(
* - no need to exclude decoders as they are not there
*/
std::vector<ModuleId> configurable_children =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL);
module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::PHYSICAL);
size_t num_configurable_children = configurable_children.size();
@ -138,8 +139,9 @@ static void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(
for (size_t child_id = 0; child_id < num_configurable_children;
++child_id) {
ModuleId child_module = configurable_children[child_id];
size_t child_instance =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_id];
size_t child_instance = module_manager.configurable_child_instances(
parent_module,
ModuleManager::e_config_child_type::PHYSICAL)[child_id];
/* Get the instance name and ensure it is not empty */
std::string instance_name = module_manager.instance_name(

39
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -636,7 +636,8 @@ static void rec_build_physical_block_bitstream(
VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
/* Skip module with no configurable children */
if (0 == module_manager.num_configurable_children(pb_module, ModuleManager::e_config_child_type::LOGICAL)) {
if (0 == module_manager.num_configurable_children(
pb_module, ModuleManager::e_config_child_type::LOGICAL)) {
return;
}
@ -644,17 +645,20 @@ static void rec_build_physical_block_bitstream(
* manager */
std::string pb_block_name = generate_physical_block_instance_name(
physical_pb_type, pb_graph_node_index);
/* If there are no physical memory blocks under the current module, use the previous module, which is the physical memory block */
/* If there are no physical memory blocks under the current module, use the
* previous module, which is the physical memory block */
ConfigBlockId pb_configurable_block = parent_configurable_block;
if (0 < module_manager.num_configurable_children(pb_module, ModuleManager::e_config_child_type::PHYSICAL)) {
if (0 < module_manager.num_configurable_children(
pb_module, ModuleManager::e_config_child_type::PHYSICAL)) {
pb_configurable_block = bitstream_manager.add_block(pb_block_name);
bitstream_manager.add_child_block(parent_configurable_block,
pb_configurable_block);
/* Reserve child blocks for new created block */
bitstream_manager.reserve_child_blocks(
parent_configurable_block,
count_module_manager_module_configurable_children(module_manager,
pb_module, ModuleManager::e_config_child_type::PHYSICAL));
count_module_manager_module_configurable_children(
module_manager, pb_module,
ModuleManager::e_config_child_type::PHYSICAL));
}
/* Recursively finish all the child pb_types*/
@ -750,7 +754,8 @@ static void build_physical_block_bitstream(
VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
/* Skip module with no configurable children */
if (0 == module_manager.num_configurable_children(grid_module, ModuleManager::e_config_child_type::LOGICAL)) {
if (0 == module_manager.num_configurable_children(
grid_module, ModuleManager::e_config_child_type::LOGICAL)) {
return;
}
@ -772,14 +777,26 @@ static void build_physical_block_bitstream(
/* Reserve child blocks for new created block */
bitstream_manager.reserve_child_blocks(
grid_configurable_block, count_module_manager_module_configurable_children(
module_manager, grid_module, ModuleManager::e_config_child_type::PHYSICAL));
module_manager, grid_module,
ModuleManager::e_config_child_type::PHYSICAL));
/* Create a dedicated block for the non-unified configurable child */
if (!module_manager.unified_configurable_children(grid_module)) {
VTR_ASSERT(1 == module_manager.configurable_children(grid_module, ModuleManager::e_config_child_type::PHYSICAL).size());
std::string phy_mem_instance_name = module_manager.instance_name(grid_module, module_manager.configurable_children(grid_module, ModuleManager::e_config_child_type::PHYSICAL)[0], module_manager.configurable_child_instances(grid_module, ModuleManager::e_config_child_type::PHYSICAL)[0]);
ConfigBlockId grid_grouped_config_block = bitstream_manager.add_block(phy_mem_instance_name);
bitstream_manager.add_child_block(grid_configurable_block, grid_grouped_config_block);
VTR_ASSERT(1 ==
module_manager
.configurable_children(
grid_module, ModuleManager::e_config_child_type::PHYSICAL)
.size());
std::string phy_mem_instance_name = module_manager.instance_name(
grid_module,
module_manager.configurable_children(
grid_module, ModuleManager::e_config_child_type::PHYSICAL)[0],
module_manager.configurable_child_instances(
grid_module, ModuleManager::e_config_child_type::PHYSICAL)[0]);
ConfigBlockId grid_grouped_config_block =
bitstream_manager.add_block(phy_mem_instance_name);
bitstream_manager.add_child_block(grid_configurable_block,
grid_grouped_config_block);
grid_configurable_block = grid_grouped_config_block;
}

58
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -486,8 +486,9 @@ static void build_connection_block_bitstreams(
VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
/* Bypass empty blocks which have none configurable children */
if (0 == count_module_manager_module_configurable_children(module_manager,
cb_module, ModuleManager::e_config_child_type::LOGICAL)) {
if (0 == count_module_manager_module_configurable_children(
module_manager, cb_module,
ModuleManager::e_config_child_type::LOGICAL)) {
continue;
}
@ -527,15 +528,27 @@ static void build_connection_block_bitstreams(
/* Reserve child blocks for new created block */
bitstream_manager.reserve_child_blocks(
cb_configurable_block,
count_module_manager_module_configurable_children(module_manager,
cb_module, ModuleManager::e_config_child_type::PHYSICAL));
count_module_manager_module_configurable_children(
module_manager, cb_module,
ModuleManager::e_config_child_type::PHYSICAL));
/* Create a dedicated block for the non-unified configurable child */
if (!module_manager.unified_configurable_children(cb_module)) {
VTR_ASSERT(1 == module_manager.configurable_children(cb_module, ModuleManager::e_config_child_type::PHYSICAL).size());
std::string phy_mem_instance_name = module_manager.instance_name(cb_module, module_manager.configurable_children(cb_module, ModuleManager::e_config_child_type::PHYSICAL)[0], module_manager.configurable_child_instances(cb_module, ModuleManager::e_config_child_type::PHYSICAL)[0]);
ConfigBlockId cb_grouped_config_block = bitstream_manager.add_block(phy_mem_instance_name);
bitstream_manager.add_child_block(cb_configurable_block, cb_grouped_config_block);
VTR_ASSERT(1 ==
module_manager
.configurable_children(
cb_module, ModuleManager::e_config_child_type::PHYSICAL)
.size());
std::string phy_mem_instance_name = module_manager.instance_name(
cb_module,
module_manager.configurable_children(
cb_module, ModuleManager::e_config_child_type::PHYSICAL)[0],
module_manager.configurable_child_instances(
cb_module, ModuleManager::e_config_child_type::PHYSICAL)[0]);
ConfigBlockId cb_grouped_config_block =
bitstream_manager.add_block(phy_mem_instance_name);
bitstream_manager.add_child_block(cb_configurable_block,
cb_grouped_config_block);
cb_configurable_block = cb_grouped_config_block;
}
@ -602,8 +615,9 @@ void build_routing_bitstream(
VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
/* Bypass empty blocks which have none configurable children */
if (0 == count_module_manager_module_configurable_children(module_manager,
sb_module, ModuleManager::e_config_child_type::LOGICAL)) {
if (0 == count_module_manager_module_configurable_children(
module_manager, sb_module,
ModuleManager::e_config_child_type::LOGICAL)) {
continue;
}
@ -638,15 +652,27 @@ void build_routing_bitstream(
/* Reserve child blocks for new created block */
bitstream_manager.reserve_child_blocks(
sb_configurable_block,
count_module_manager_module_configurable_children(module_manager,
sb_module, ModuleManager::e_config_child_type::PHYSICAL));
count_module_manager_module_configurable_children(
module_manager, sb_module,
ModuleManager::e_config_child_type::PHYSICAL));
/* Create a dedicated block for the non-unified configurable child */
if (!module_manager.unified_configurable_children(sb_module)) {
VTR_ASSERT(1 == module_manager.configurable_children(sb_module, ModuleManager::e_config_child_type::PHYSICAL).size());
std::string phy_mem_instance_name = module_manager.instance_name(sb_module, module_manager.configurable_children(sb_module, ModuleManager::e_config_child_type::PHYSICAL)[0], module_manager.configurable_child_instances(sb_module, ModuleManager::e_config_child_type::PHYSICAL)[0]);
ConfigBlockId sb_grouped_config_block = bitstream_manager.add_block(phy_mem_instance_name);
bitstream_manager.add_child_block(sb_configurable_block, sb_grouped_config_block);
VTR_ASSERT(1 ==
module_manager
.configurable_children(
sb_module, ModuleManager::e_config_child_type::PHYSICAL)
.size());
std::string phy_mem_instance_name = module_manager.instance_name(
sb_module,
module_manager.configurable_children(
sb_module, ModuleManager::e_config_child_type::PHYSICAL)[0],
module_manager.configurable_child_instances(
sb_module, ModuleManager::e_config_child_type::PHYSICAL)[0]);
ConfigBlockId sb_grouped_config_block =
bitstream_manager.add_block(phy_mem_instance_name);
bitstream_manager.add_child_block(sb_configurable_block,
sb_grouped_config_block);
sb_configurable_block = sb_grouped_config_block;
}

19
openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
View File

@ -49,13 +49,17 @@ static void rec_print_pnr_sdc_constrain_configurable_chain(
ModuleId& previous_module) {
/* For each configurable child, we will go one level down in priority */
for (size_t child_index = 0;
child_index < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size();
child_index <
module_manager
.configurable_children(parent_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size();
++child_index) {
std::string child_module_path = parent_module_path;
ModuleId child_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_index];
size_t child_instance_id =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_index];
ModuleId child_module_id = module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_index];
size_t child_instance_id = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_index];
std::string child_instance_name;
if (true ==
module_manager
@ -79,7 +83,10 @@ static void rec_print_pnr_sdc_constrain_configurable_chain(
/* If there is no configurable children any more, this is a leaf module, print
* a SDC command for disable timing */
if (0 < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size()) {
if (0 < module_manager
.configurable_children(parent_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size()) {
return;
}

19
openfpga/src/fpga_sdc/sdc_memory_utils.cpp
View File

@ -45,13 +45,17 @@ void rec_print_pnr_sdc_disable_configurable_memory_module_output(
/* For each configurable child, we will go one level down in priority */
for (size_t child_index = 0;
child_index < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size();
child_index <
module_manager
.configurable_children(parent_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size();
++child_index) {
std::string child_module_path = parent_module_path;
ModuleId child_module_id =
module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_index];
size_t child_instance_id =
module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_index];
ModuleId child_module_id = module_manager.configurable_children(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_index];
size_t child_instance_id = module_manager.configurable_child_instances(
parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_index];
std::string child_instance_name;
if (true ==
module_manager
@ -96,7 +100,10 @@ void rec_print_pnr_sdc_disable_configurable_memory_module_output(
/* If there is no configurable children any more, this is a leaf module, print
* a SDC command for disable timing */
if (0 < module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size()) {
if (0 < module_manager
.configurable_children(parent_module,
ModuleManager::e_config_child_type::PHYSICAL)
.size()) {
return;
}

78
openfpga/src/utils/memory_utils.cpp
View File

@ -3,6 +3,7 @@
* generating ports for memory modules
*********************************************************************/
#include "memory_utils.h"
#include "command_exit_codes.h"
#include "decoder_library_utils.h"
#include "openfpga_naming.h"
@ -344,7 +345,8 @@ std::vector<std::string> generate_sram_port_names(
case CONFIG_MEM_FEEDTHROUGH:
/* Feed through wires are all inputs */
model_port_types.push_back(CIRCUIT_MODEL_PORT_BL); /* Indicate mem port */
model_port_types.push_back(CIRCUIT_MODEL_PORT_BLB); /* Indicate mem_inv port */
model_port_types.push_back(
CIRCUIT_MODEL_PORT_BLB); /* Indicate mem_inv port */
break;
case CONFIG_MEM_SCAN_CHAIN:
model_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
@ -495,43 +497,81 @@ size_t estimate_num_configurable_children_to_skip_by_config_protocol(
return num_child_to_skip;
}
int rec_find_physical_memory_children(const ModuleManager& module_manager, const ModuleId& curr_module, std::vector<ModuleId>& physical_memory_children) {
if (module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL).empty()) {
int rec_find_physical_memory_children(
const ModuleManager& module_manager, const ModuleId& curr_module,
std::vector<ModuleId>& physical_memory_children) {
if (module_manager
.configurable_children(curr_module,
ModuleManager::e_config_child_type::LOGICAL)
.empty()) {
return CMD_EXEC_SUCCESS;
}
for (size_t ichild = 0; ichild < module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL).size(); ++ichild) {
ModuleId logical_child = module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL)[ichild];
if (module_manager.configurable_children(logical_child, ModuleManager::e_config_child_type::LOGICAL).empty()) {
for (size_t ichild = 0;
ichild < module_manager
.configurable_children(
curr_module, ModuleManager::e_config_child_type::LOGICAL)
.size();
++ichild) {
ModuleId logical_child = module_manager.configurable_children(
curr_module, ModuleManager::e_config_child_type::LOGICAL)[ichild];
if (module_manager
.configurable_children(logical_child,
ModuleManager::e_config_child_type::LOGICAL)
.empty()) {
/* This is a leaf node, get the physical memory module */
physical_memory_children.push_back(module_manager.logical2physical_configurable_children(curr_module)[ichild]);
physical_memory_children.push_back(
module_manager.logical2physical_configurable_children(
curr_module)[ichild]);
} else {
rec_find_physical_memory_children(module_manager, logical_child, physical_memory_children);
rec_find_physical_memory_children(module_manager, logical_child,
physical_memory_children);
}
}
return CMD_EXEC_SUCCESS;
return CMD_EXEC_SUCCESS;
}
int rec_update_logical_memory_children_with_physical_mapping(ModuleManager& module_manager, const ModuleId& curr_module, const ModuleId& phy_mem_module, std::map<ModuleId, size_t>& logical_mem_child_inst_count) {
if (module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL).empty()) {
int rec_update_logical_memory_children_with_physical_mapping(
ModuleManager& module_manager, const ModuleId& curr_module,
const ModuleId& phy_mem_module,
std::map<ModuleId, size_t>& logical_mem_child_inst_count) {
if (module_manager
.configurable_children(curr_module,
ModuleManager::e_config_child_type::LOGICAL)
.empty()) {
return CMD_EXEC_SUCCESS;
}
for (size_t ichild = 0; ichild < module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL).size(); ++ichild) {
ModuleId logical_child = module_manager.configurable_children(curr_module, ModuleManager::e_config_child_type::LOGICAL)[ichild];
if (module_manager.configurable_children(logical_child, ModuleManager::e_config_child_type::LOGICAL).empty()) {
for (size_t ichild = 0;
ichild < module_manager
.configurable_children(
curr_module, ModuleManager::e_config_child_type::LOGICAL)
.size();
++ichild) {
ModuleId logical_child = module_manager.configurable_children(
curr_module, ModuleManager::e_config_child_type::LOGICAL)[ichild];
if (module_manager
.configurable_children(logical_child,
ModuleManager::e_config_child_type::LOGICAL)
.empty()) {
/* This is a leaf node, update its physical information */
ModuleId phy_mem_submodule = module_manager.logical2physical_configurable_children(curr_module)[ichild];
ModuleId phy_mem_submodule =
module_manager.logical2physical_configurable_children(
curr_module)[ichild];
auto result = logical_mem_child_inst_count.find(phy_mem_submodule);
if (result == logical_mem_child_inst_count.end()) {
logical_mem_child_inst_count[phy_mem_submodule] = 0;
}
module_manager.set_logical2physical_configurable_child_instance(curr_module, ichild, logical_mem_child_inst_count[phy_mem_submodule]);
module_manager.set_logical2physical_configurable_child_parent_module(curr_module, ichild, phy_mem_module);
module_manager.set_logical2physical_configurable_child_instance(
curr_module, ichild, logical_mem_child_inst_count[phy_mem_submodule]);
module_manager.set_logical2physical_configurable_child_parent_module(
curr_module, ichild, phy_mem_module);
logical_mem_child_inst_count[phy_mem_submodule]++;
} else {
rec_update_logical_memory_children_with_physical_mapping(module_manager, logical_child, phy_mem_module, logical_mem_child_inst_count);
rec_update_logical_memory_children_with_physical_mapping(
module_manager, logical_child, phy_mem_module,
logical_mem_child_inst_count);
}
}
return CMD_EXEC_SUCCESS;
return CMD_EXEC_SUCCESS;
}
} /* end namespace openfpga */

22
openfpga/src/utils/memory_utils.h
View File

@ -55,17 +55,25 @@ size_t estimate_num_configurable_children_to_skip_by_config_protocol(
/**
* @brief Find the physical memory child modules with a given root module
* This function will walk through the module tree in a recursive way until reaching the leaf node (which require configurable memories)
* Return a list of modules
* This function will walk through the module tree in a recursive way until
* reaching the leaf node (which require configurable memories) Return a list of
* modules
*/
int rec_find_physical_memory_children(const ModuleManager& module_manager, const ModuleId& curr_module, std::vector<ModuleId>& physical_memory_children);
int rec_find_physical_memory_children(
const ModuleManager& module_manager, const ModuleId& curr_module,
std::vector<ModuleId>& physical_memory_children);
/**
* @brief Update all the mappings between logical-to-physical memory children with a given root module
* This function will walk through the module tree in a recursive way until reaching the leaf node (which require configurable memories)
* Keep a scoreboard of instance number for checking. Note that when calling this the function, use an empty scoreboard!
* @brief Update all the mappings between logical-to-physical memory children
* with a given root module This function will walk through the module tree in a
* recursive way until reaching the leaf node (which require configurable
* memories) Keep a scoreboard of instance number for checking. Note that when
* calling this the function, use an empty scoreboard!
*/
int rec_update_logical_memory_children_with_physical_mapping(ModuleManager& module_manager, const ModuleId& curr_module, const ModuleId& phy_mem_module, std::map<ModuleId, size_t>& logical_mem_child_inst_count);
int rec_update_logical_memory_children_with_physical_mapping(
ModuleManager& module_manager, const ModuleId& curr_module,
const ModuleId& phy_mem_module,
std::map<ModuleId, size_t>& logical_mem_child_inst_count);
} /* end namespace openfpga */

70
openfpga/src/utils/module_manager_memory_utils.cpp
View File

@ -39,7 +39,10 @@ static bool submodule_memory_modules_match_fabric_key(
const FabricKey& fabric_key, const FabricKeyModuleId& key_module_id) {
/* If the length does not match, conclusion is easy to be made */
size_t len_module_memory =
module_manager.configurable_children(module_id, ModuleManager::e_config_child_type::PHYSICAL).size();
module_manager
.configurable_children(module_id,
ModuleManager::e_config_child_type::PHYSICAL)
.size();
size_t len_fabric_sub_key = fabric_key.sub_keys(key_module_id).size();
if (len_module_memory != len_fabric_sub_key) {
return false;
@ -65,9 +68,11 @@ static bool submodule_memory_modules_match_fabric_key(
inst_info.second = fabric_key.sub_key_value(key_id);
}
if (inst_info.first !=
module_manager.configurable_children(module_id, ModuleManager::e_config_child_type::PHYSICAL)[ikey] ||
module_manager.configurable_children(
module_id, ModuleManager::e_config_child_type::PHYSICAL)[ikey] ||
inst_info.second !=
module_manager.configurable_child_instances(module_id, ModuleManager::e_config_child_type::PHYSICAL)[ikey]) {
module_manager.configurable_child_instances(
module_id, ModuleManager::e_config_child_type::PHYSICAL)[ikey]) {
return false;
}
}
@ -143,7 +148,8 @@ static bool update_submodule_memory_modules_from_fabric_key(
/* Now we can add the child to configurable children of the top module */
module_manager.add_configurable_child(module_id, inst_info.first,
inst_info.second, config_child_type, vtr::Point<int>());
inst_info.second, config_child_type,
vtr::Point<int>());
}
return CMD_EXEC_SUCCESS;
}
@ -156,7 +162,9 @@ static int remove_submodule_nets_cmos_memory_chain_config_bus(
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type) {
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module, config_child_type).size();
mem_index <
module_manager.configurable_children(parent_module, config_child_type)
.size();
++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
@ -173,8 +181,8 @@ static int remove_submodule_nets_cmos_memory_chain_config_bus(
} else {
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
net_src_module_id =
module_manager.configurable_children(parent_module, config_child_type)[mem_index - 1];
net_src_module_id = module_manager.configurable_children(
parent_module, config_child_type)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index - 1];
net_src_port_id =
@ -203,9 +211,12 @@ static int remove_submodule_nets_cmos_memory_chain_config_bus(
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
ModuleId net_src_module_id =
module_manager.configurable_children(parent_module, config_child_type).back();
module_manager.configurable_children(parent_module, config_child_type)
.back();
size_t net_src_instance_id =
module_manager.configurable_child_instances(parent_module, config_child_type).back();
module_manager
.configurable_child_instances(parent_module, config_child_type)
.back();
ModulePortId net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
@ -304,7 +315,9 @@ static int rebuild_submodule_nets_cmos_memory_chain_config_bus(
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type) {
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module, config_child_type).size();
mem_index <
module_manager.configurable_children(parent_module, config_child_type)
.size();
++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
@ -325,17 +338,17 @@ static int rebuild_submodule_nets_cmos_memory_chain_config_bus(
/* Find the port name of next memory module */
std::string sink_port_name = generate_configuration_chain_head_name();
net_sink_module_id =
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
net_sink_module_id = module_manager.configurable_children(
parent_module, config_child_type)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
} else {
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
net_src_module_id =
module_manager.configurable_children(parent_module, config_child_type)[mem_index - 1];
net_src_module_id = module_manager.configurable_children(
parent_module, config_child_type)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index - 1];
net_src_port_id =
@ -343,10 +356,10 @@ static int rebuild_submodule_nets_cmos_memory_chain_config_bus(
/* Find the port name of next memory module */
std::string sink_port_name = generate_configuration_chain_head_name();
net_sink_module_id =
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
net_sink_module_id = module_manager.configurable_children(
parent_module, config_child_type)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
}
@ -380,9 +393,12 @@ static int rebuild_submodule_nets_cmos_memory_chain_config_bus(
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
ModuleId net_src_module_id =
module_manager.configurable_children(parent_module, config_child_type).back();
module_manager.configurable_children(parent_module, config_child_type)
.back();
size_t net_src_instance_id =
module_manager.configurable_child_instances(parent_module, config_child_type).back();
module_manager
.configurable_child_instances(parent_module, config_child_type)
.back();
ModulePortId net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
@ -509,20 +525,22 @@ static int load_and_update_submodule_memory_modules_from_fabric_key(
}
/* Do not match, now remove all the nets for the configurable children */
status = remove_submodule_configurable_children_nets(
module_manager, module_id, circuit_lib, config_protocol, ModuleManager::e_config_child_type::PHYSICAL);
module_manager, module_id, circuit_lib, config_protocol,
ModuleManager::e_config_child_type::PHYSICAL);
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
}
/* Overwrite the configurable children list */
status = update_submodule_memory_modules_from_fabric_key(
module_manager, module_id, circuit_lib, config_protocol, ModuleManager::e_config_child_type::PHYSICAL, fabric_key,
key_module_id);
module_manager, module_id, circuit_lib, config_protocol,
ModuleManager::e_config_child_type::PHYSICAL, fabric_key, key_module_id);
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
}
/* TODO: Create the nets for the new list of configurable children */
status = rebuild_submodule_configurable_children_nets(
module_manager, module_id, circuit_lib, config_protocol, ModuleManager::e_config_child_type::PHYSICAL);
module_manager, module_id, circuit_lib, config_protocol,
ModuleManager::e_config_child_type::PHYSICAL);
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
}

152
openfpga/src/utils/module_manager_utils.cpp
View File

@ -86,11 +86,14 @@ void reserve_module_manager_module_nets(ModuleManager& module_manager,
*children as well
******************************************************************************/
size_t count_module_manager_module_configurable_children(
const ModuleManager& module_manager, const ModuleId& module, const ModuleManager::e_config_child_type& config_child_type) {
const ModuleManager& module_manager, const ModuleId& module,
const ModuleManager::e_config_child_type& config_child_type) {
size_t num_config_children = 0;
for (const ModuleId& child : module_manager.configurable_children(module, config_child_type)) {
if (0 != module_manager.configurable_children(child, config_child_type).size()) {
for (const ModuleId& child :
module_manager.configurable_children(module, config_child_type)) {
if (0 !=
module_manager.configurable_children(child, config_child_type).size()) {
num_config_children++;
}
}
@ -1041,7 +1044,8 @@ void add_module_nets_cmos_flatten_memory_config_bus(
module_manager.module_port(net_src_module_id, net_src_port_id);
for (size_t mem_index = 0;
mem_index < module_manager.num_configurable_children(parent_module, config_child_type);
mem_index < module_manager.num_configurable_children(parent_module,
config_child_type);
++mem_index) {
ModuleId net_sink_module_id;
size_t net_sink_instance_id;
@ -1050,10 +1054,10 @@ void add_module_nets_cmos_flatten_memory_config_bus(
/* Find the port name of next memory module */
std::string sink_port_name =
generate_sram_port_name(sram_orgz_type, config_port_type);
net_sink_module_id =
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
net_sink_module_id = module_manager.configurable_children(
parent_module, config_child_type)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
@ -1125,15 +1129,17 @@ void add_module_nets_cmos_memory_bank_bl_config_bus(
module_manager.module_port(net_src_module_id, net_src_port_id);
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module, config_child_type).size();
mem_index <
module_manager.configurable_children(parent_module, config_child_type)
.size();
++mem_index) {
/* Find the port name of next memory module */
std::string sink_port_name =
generate_sram_port_name(sram_orgz_type, config_port_type);
ModuleId net_sink_module_id =
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
size_t net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
ModuleId net_sink_module_id = module_manager.configurable_children(
parent_module, config_child_type)[mem_index];
size_t net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index];
ModulePortId net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
@ -1221,15 +1227,17 @@ void add_module_nets_cmos_memory_bank_wl_config_bus(
module_manager.module_port(net_src_module_id, net_bl_port_id);
for (size_t mem_index = 0;
mem_index < module_manager.configurable_children(parent_module, config_child_type).size();
mem_index <
module_manager.configurable_children(parent_module, config_child_type)
.size();
++mem_index) {
/* Find the port name of next memory module */
std::string sink_port_name =
generate_sram_port_name(sram_orgz_type, config_port_type);
ModuleId net_sink_module_id =
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
size_t net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
ModuleId net_sink_module_id = module_manager.configurable_children(
parent_module, config_child_type)[mem_index];
size_t net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index];
ModulePortId net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
@ -1279,7 +1287,8 @@ void add_module_nets_cmos_memory_chain_config_bus(
const e_config_protocol_type& sram_orgz_type,
const ModuleManager::e_config_child_type& config_child_type) {
for (size_t mem_index = 0;
mem_index < module_manager.num_configurable_children(parent_module, config_child_type);
mem_index < module_manager.num_configurable_children(parent_module,
config_child_type);
++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
@ -1300,17 +1309,17 @@ void add_module_nets_cmos_memory_chain_config_bus(
/* Find the port name of next memory module */
std::string sink_port_name = generate_configuration_chain_head_name();
net_sink_module_id =
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
net_sink_module_id = module_manager.configurable_children(
parent_module, config_child_type)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
} else {
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
net_src_module_id =
module_manager.configurable_children(parent_module, config_child_type)[mem_index - 1];
net_src_module_id = module_manager.configurable_children(
parent_module, config_child_type)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index - 1];
net_src_port_id =
@ -1318,10 +1327,10 @@ void add_module_nets_cmos_memory_chain_config_bus(
/* Find the port name of next memory module */
std::string sink_port_name = generate_configuration_chain_head_name();
net_sink_module_id =
module_manager.configurable_children(parent_module, config_child_type)[mem_index];
net_sink_instance_id =
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
net_sink_module_id = module_manager.configurable_children(
parent_module, config_child_type)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index];
net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, sink_port_name);
}
@ -1355,9 +1364,12 @@ void add_module_nets_cmos_memory_chain_config_bus(
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
ModuleId net_src_module_id =
module_manager.configurable_children(parent_module, config_child_type).back();
module_manager.configurable_children(parent_module, config_child_type)
.back();
size_t net_src_instance_id =
module_manager.configurable_child_instances(parent_module, config_child_type).back();
module_manager
.configurable_child_instances(parent_module, config_child_type)
.back();
ModulePortId net_src_port_id =
module_manager.find_module_port(net_src_module_id, src_port_name);
@ -1577,8 +1589,8 @@ static void add_module_nets_cmos_memory_frame_decoder_config_bus(
for (size_t mem_index = 0; mem_index < configurable_children.size();
++mem_index) {
ModuleId child_module = configurable_children[mem_index];
size_t child_instance =
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
size_t child_instance = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index];
ModulePortId child_addr_port = module_manager.find_module_port(
child_module, std::string(DECODER_ADDRESS_PORT_NAME));
BasicPort child_addr_port_info =
@ -1609,8 +1621,8 @@ static void add_module_nets_cmos_memory_frame_decoder_config_bus(
for (size_t mem_index = 0; mem_index < configurable_children.size();
++mem_index) {
ModuleId child_module = configurable_children[mem_index];
size_t child_instance =
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
size_t child_instance = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index];
ModulePortId child_din_port = module_manager.find_module_port(
child_module, std::string(DECODER_DATA_IN_PORT_NAME));
add_module_bus_nets(module_manager, parent_module, parent_module, 0,
@ -1630,8 +1642,8 @@ static void add_module_nets_cmos_memory_frame_decoder_config_bus(
for (size_t mem_index = 0; mem_index < configurable_children.size();
++mem_index) {
ModuleId child_module = configurable_children[mem_index];
size_t child_instance =
module_manager.configurable_child_instances(parent_module, config_child_type)[mem_index];
size_t child_instance = module_manager.configurable_child_instances(
parent_module, config_child_type)[mem_index];
ModulePortId child_en_port = module_manager.find_module_port(
child_module, std::string(DECODER_ENABLE_PORT_NAME));
BasicPort child_en_port_info =
@ -1655,7 +1667,8 @@ static void add_module_nets_cmos_memory_frame_decoder_config_bus(
}
/* Add the decoder as the last configurable children */
module_manager.add_configurable_child(parent_module, decoder_module, 0, config_child_type);
module_manager.add_configurable_child(parent_module, decoder_module, 0,
config_child_type);
}
/*********************************************************************
@ -1671,15 +1684,18 @@ void add_module_nets_cmos_memory_frame_config_bus(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const ModuleId& parent_module,
const ModuleManager::e_config_child_type& config_child_type) {
if (0 == module_manager.num_configurable_children(parent_module, config_child_type)) {
if (0 == module_manager.num_configurable_children(parent_module,
config_child_type)) {
return;
}
if (1 == module_manager.num_configurable_children(parent_module, config_child_type)) {
add_module_nets_cmos_memory_frame_short_config_bus(module_manager,
parent_module, config_child_type);
if (1 == module_manager.num_configurable_children(parent_module,
config_child_type)) {
add_module_nets_cmos_memory_frame_short_config_bus(
module_manager, parent_module, config_child_type);
} else {
VTR_ASSERT(1 < module_manager.num_configurable_children(parent_module, config_child_type));
VTR_ASSERT(1 < module_manager.num_configurable_children(parent_module,
config_child_type));
add_module_nets_cmos_memory_frame_decoder_config_bus(
module_manager, decoder_lib, parent_module, config_child_type);
}
@ -1741,23 +1757,28 @@ static void add_module_nets_cmos_memory_config_bus(
}
case CONFIG_MEM_FEEDTHROUGH:
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL, config_child_type);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL,
config_child_type);
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BLB, config_child_type);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BLB,
config_child_type);
break;
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL, config_child_type);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL,
config_child_type);
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL, config_child_type);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL,
config_child_type);
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WLR, config_child_type);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WLR,
config_child_type);
break;
case CONFIG_MEM_FRAME_BASED:
add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib,
parent_module, config_child_type);
add_module_nets_cmos_memory_frame_config_bus(
module_manager, decoder_lib, parent_module, config_child_type);
break;
default:
VTR_LOGF_ERROR(__FILE__, __LINE__,
@ -1814,21 +1835,26 @@ static void add_pb_module_nets_cmos_memory_config_bus(
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_QL_MEMORY_BANK:
add_module_nets_cmos_memory_bank_bl_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL, config_child_type);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL,
config_child_type);
add_module_nets_cmos_memory_bank_wl_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL, config_child_type);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL,
config_child_type);
add_module_nets_cmos_memory_bank_wl_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WLR, config_child_type);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WLR,
config_child_type);
break;
case CONFIG_MEM_MEMORY_BANK:
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL, config_child_type);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL,
config_child_type);
add_module_nets_cmos_flatten_memory_config_bus(
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL, config_child_type);
module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL,
config_child_type);
break;
case CONFIG_MEM_FRAME_BASED:
add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib,
parent_module, config_child_type);
add_module_nets_cmos_memory_frame_config_bus(
module_manager, decoder_lib, parent_module, config_child_type);
break;
default:
VTR_LOGF_ERROR(__FILE__, __LINE__,
@ -1899,7 +1925,8 @@ void add_module_nets_memory_config_bus(
switch (mem_tech) {
case CIRCUIT_MODEL_DESIGN_CMOS:
add_module_nets_cmos_memory_config_bus(module_manager, decoder_lib,
parent_module, sram_orgz_type, config_child_type);
parent_module, sram_orgz_type,
config_child_type);
break;
case CIRCUIT_MODEL_DESIGN_RRAM:
/* TODO: */
@ -1931,7 +1958,8 @@ void add_pb_module_nets_memory_config_bus(
switch (mem_tech) {
case CIRCUIT_MODEL_DESIGN_CMOS:
add_pb_module_nets_cmos_memory_config_bus(module_manager, decoder_lib,
parent_module, sram_orgz_type, config_child_type);
parent_module, sram_orgz_type,
config_child_type);
break;
case CIRCUIT_MODEL_DESIGN_RRAM:
/* TODO: */
@ -2420,9 +2448,11 @@ size_t find_module_num_config_bits_from_child_modules(
/* If there are more than 2 configurable children, we need a decoder
* Otherwise, we can just short wire the address port to the children
*/
if (1 < module_manager.num_configurable_children(module_id, config_child_type)) {
if (1 < module_manager.num_configurable_children(module_id,
config_child_type)) {
num_config_bits += find_mux_local_decoder_addr_size(
module_manager.num_configurable_children(module_id, config_child_type));
module_manager.num_configurable_children(module_id,
config_child_type));
}
break;

3
openfpga/src/utils/module_manager_utils.h
View File

@ -42,7 +42,8 @@ void reserve_module_manager_module_nets(ModuleManager& module_manager,
const ModuleId& module);
size_t count_module_manager_module_configurable_children(
const ModuleManager& module_manager, const ModuleId& module, const ModuleManager::e_config_child_type& config_child_type);
const ModuleManager& module_manager, const ModuleId& module,
const ModuleManager::e_config_child_type& config_child_type);
std::pair<ModuleId, size_t> find_module_manager_instance_module_info(
const ModuleManager& module_manager, const ModuleId& parent,